CN103985636B - 调整多阈值电压的FinFET/三栅极沟道掺杂 - Google Patents
调整多阈值电压的FinFET/三栅极沟道掺杂 Download PDFInfo
- Publication number
- CN103985636B CN103985636B CN201310177806.3A CN201310177806A CN103985636B CN 103985636 B CN103985636 B CN 103985636B CN 201310177806 A CN201310177806 A CN 201310177806A CN 103985636 B CN103985636 B CN 103985636B
- Authority
- CN
- China
- Prior art keywords
- fin
- dummy gate
- mid portion
- annealing process
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 claims abstract description 94
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 150000002500 ions Chemical class 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims abstract description 14
- 238000004528 spin coating Methods 0.000 claims description 40
- 238000000137 annealing Methods 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 36
- 239000010410 layer Substances 0.000 claims description 33
- 238000001953 recrystallisation Methods 0.000 claims description 17
- 239000000126 substance Substances 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000011800 void material Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000007943 implant Substances 0.000 description 9
- 230000006735 deficit Effects 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 230000008439 repair process Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004567 concrete Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000037230 mobility Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
控制鳍式场效应晶体管(FinFET)内阈值电压的实施例方法包括:在鳍的中间部分的上方形成虚拟栅极,鳍的中间部分设置在未受虚拟栅极保护的鳍的外部部分之间;去除鳍的外部部分且用外延生长的含硅材料代替鳍的外部部分;在虚拟栅极和外延生长的含硅材料的上方应用旋涂光刻胶,然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶;蚀刻掉虚拟栅极的硬掩膜和多晶硅,以露出虚拟栅极的栅氧化物,其中,栅氧化物设置在鳍的中间部分的上方;以及穿过设置在鳍的中间部分上方的栅氧化物,将离子注入到鳍的中间部分中。
Description
技术领域
本发明总体上涉及半导体领域,更具体地,涉及调整多阈值电压的FinFET/三栅极沟道掺杂。
背景技术
半导体器件用于大量的电子器件中,例如,电脑、手机等。半导体器件包括集成电路,这些集成电路是通过在半导体晶圆的上方沉积许多类型的薄膜材料和图案化这些薄膜材料以在半导体晶圆上形成集成电路。集成电路包括场效应晶体管(FET),如金属氧化物半导体(MOS)晶体管。
半导体行业的目标之一是继续缩小单个FET的尺寸和提高单个FET的速度。为实现这些目标,在子32nm的晶体管节点中使用鳍式FET(FinFETs)或多栅极晶体管。FinFETs不仅提高了面密度,而且增强了沟道的栅极控制。
通过使用常规沟道掺杂方法(如,用离子注入和退火),在22nm的节点几何尺寸的FinFET技术可实行多阈值电压(Vth)。
当鳍形成前使用常规的离子注入时,我们所要面对的挑战之一是,鳍形成之后,由于相对薄的鳍(例如,宽为10nm-15nm和高为30nm-50nm)和大的面容比(至少是部分原因),使得在后续的工艺步骤中会出现掺杂物损耗。掺杂物损耗可能导致随机掺杂扰动(RDF),这直接影响了阈值电压可控性。随机掺杂扰动也可能是鳍的宽度/高度发生变化而导致的结果,这样会引起鳍的面容比的变化。
对于块体硅(Si)而言,控制FinFET中的多阈值电压的另一种方法是在形成鳍之后进行离子注入。但是,这种集成方法所要面临的挑战之一是,离子注入之后,需要进行退火步骤以重结晶鳍。对于独立鳍而言,在室温下进行常规离子注入之后,它们是非晶的,用于鳍重结晶的晶种是氧化填充物内部的剩余鳍体。重结晶工艺可能采用高级别的晶格缺陷,这样必然导致鳍内的迁移率退化。
发明内容
为解决上述问题,本发明提供了一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法,包括:在鳍的中间部分的上方形成虚拟栅极,鳍的中间部分设置在鳍的未受虚拟栅极保护的外部部分之间;去除鳍的外部部分并用外延生长的含硅材料代替鳍的外部部分;在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除虚拟栅极的硬掩膜上方的旋涂光刻胶;蚀刻掉硬掩膜和虚拟栅极的多晶硅,以露出虚拟栅极的栅氧化物,栅氧化物设置在鳍的中间部分的上方;以及穿过设置在鳍的中间部分上方的栅氧化物,将离子注入到鳍的中间部分中。
该方法进一步包括:在注入离子之后,去除剩余的旋涂光刻胶,然后进行退火工艺以重结晶鳍。
该方法进一步包括:在大约25℃到大约600℃之间的温度条件下进行离子注入。
该方法进一步包括:进行退火工艺以重结晶鳍,在离子注入之后立即进行退火工艺。
该方法进一步包括:进行退火工艺以重结晶鳍,当沿着设置在鳍的中间部分上方的栅氧化物设置虚拟隔离件时,进行退火工艺。
该方法进一步包括:进行退火工艺以重结晶鳍,在设置于鳍的中间部分上方的栅氧化物的上方形成保护层之后进行退火工艺。
该方法进一步包括:通过化学下游蚀刻去除虚拟栅极的硬掩膜上方的旋涂光刻胶。
该方法进一步包括:通过干蚀刻、湿蚀刻、化学下游蚀刻、化学氧化去除和它们的组合中的一种工艺,蚀刻掉硬掩膜。
该方法进一步包括:通过干蚀刻、湿蚀刻、化学下游蚀刻和它们的组合中的一种工艺,蚀刻掉虚拟栅极的多晶硅。
该方法进一步包括:在形成虚拟栅极之前,在鳍的中间部分中形成轻掺杂漏极。
其中,外延生长的含硅材料是硅锗(SiGe)。
其中,外延生长的含硅材料是掺杂有碳化物的硅(SiC)、掺杂有磷的硅(SiP)和掺杂有碳和磷的硅(SiCP)中的一种。
此外,还提供了一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法,包括:在鳍的中间部分的上方形成虚拟栅极,鳍的中间部分设置在鳍的未受虚拟栅极保护的外部部分之间;去除鳍的外部部分并用外延生长的含硅材料代替鳍的外部部分;在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除虚拟栅极的硬掩膜上方的旋涂光刻胶;蚀刻掉硬掩膜和虚拟栅极的多晶硅的一部分,以露出虚拟栅极的栅氧化物并形成多晶硅隔离件,栅氧化物设置在鳍的中间部分的上方;以及穿过设置在鳍的中间部分上方的栅氧化物,将离子注入到鳍的中间部分中。
该方法进一步包括:在大约25℃到大约600℃之间的温度条件下进行离子注入。
该方法进一步包括:进行退火工艺以重结晶鳍,在离子注入之后立即进行退火工艺。
该方法进一步包括:进行退火工艺以重结晶鳍,在去除多晶硅隔离件之前进行退火工艺。
此外,还提供了一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法,包括:在鳍的中间部分的上方形成虚拟栅极;用外延生长的含硅材料代替鳍的未受虚拟栅极保护的外部部分;在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除虚拟栅极的硬掩膜上方的旋涂光刻胶;蚀刻掉硬掩膜和虚拟栅极的多晶硅,以露出虚拟栅极的栅氧化物,栅氧化物设置在鳍的中间部分的上方;
穿过设置在鳍的中间部分上方的栅氧化物,将离子注入到鳍的中间部分中;以及
进行退火工艺以重结晶鳍。
该方法进一步包括:在注入离子之后,去除剩余的旋涂光刻胶,然后在大约25℃到大约600℃之间的温度条件下进行离子注入。
该方法进一步包括:在离子注入之后,立即进行退火工艺。
该方法进一步包括:在设置于鳍的所述中间部分上方的所述栅氧化物的上方形成虚拟隔离件和保护层中的至少一个之后,进行所述退火工艺。
附图说明
为了更全面地理解实施例及其优势,现将结合附图所进行的描述作为参考,其中:
图1示出了实施例FinFET;
图2A-图2C示出了当露出虚拟栅极的硬掩膜时的图1中所示的实施例FinFET的截面图和顶视图;
图3A-图3C示出了在去除虚拟栅极的硬掩膜之后的图2A-图2C中所示的实施例FinFET的截面图和顶视图;
图4A-图4C示出了去除虚拟栅极的多晶硅之后的图3A-图3C中所示的实施例FinFET的截面图和顶视图;
图5A-图5C示出了离子注入工艺过程中的图4A-图4C中所示的实施例FinFET的截面图和顶视图;
图6A-图6C示出了去除任何剩余旋涂光刻胶之后的图5A-图5C中所示的实施例FinFET的截面图和顶视图;
图7A-图7C示出了进行退火工艺以修补鳍内的残留损伤之后的图6A-图6C中所示的实施例FinFET的截面图和顶视图;
图8A-图8C示出了去除虚拟栅极的多晶硅的一部分以形成隔离件之后的图3A-图3C中所示的实施例FinFET的截面图和顶视图;
图9A-图9C示出了在离子注入工艺过程中的图8A-图8C中所示实施例FinFET的截面图和顶视图;
图10A-图10C示出了去除任意剩余旋涂光刻胶之后的图9A-图9C中所示的实施例FinFET的截面图和顶视图;
图11A-图11C示出了进行退火工艺以修补鳍内残留损伤之后的图10A-图10C中所示的实施例FinFET的截面图和顶视图;
图12A-图12C示出了去除隔离件之后的图11A-图11C中所示的实施例FinFET的截面图和顶面图;
图13示出了在鳍式场效应晶体管(FinFET)中控制阈值电压的方法;
图14示出了在鳍式场效应晶体管(FinFET)中控制阈值电压的方法;以及
图15示出了在鳍式场效应晶体管(FinFET)中控制阈值电压的方法。
除非另有说明,否则不同图中的相应数字和符号常常表示相应的部分。绘制的图只用于清楚地说明实施例的相关方面,因此无需按比例绘制。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
根据具体环境中的实施例来描述本发明,即,FinFET。但是,本发明也可应用于其他集成电路、电子结构等中。
现参见图1,其示出了实施例FinFET10。本文的实施例FinFET10指代且表示双栅极器件和三栅极器件。如图所示,实施例FinFET10包括支撑设置在绝缘体16中的鳍14的衬底12。在一个实施例中,衬底12和鳍14的低部是块体硅或含硅材料。在一个实施例中,绝缘体16是氧化物或表示浅沟道隔离(STI)区。
突出于绝缘体16的表面的鳍14包括位于外部部分20之间的中间部分18。如图1所示,虚拟栅极22保护中间部分18。反之,表示FinFET10的源极和漏极的外部部分20通常不受虚拟栅极22的保护但是邻近虚拟栅极22。
在一个实施例中,最初由块体硅形成的鳍14的外部部分20被去除且由外延生长的含硅材料24代替。在一个实施例中,外延生长的含硅材料24包括用于p型FinFET(亦称pFET)的硅锗(SiGe)。在一个实施例中,外延生长的含硅材料24包括用于n型FinFET(亦称nFET)的重掺杂碳的硅(SiC)、重掺杂磷的硅(SiP)、或两者的组合(SiCP)。
仍参见图1,在虚拟栅极22的对侧上设置隔离件26。如图所示,隔离件26通常沿任何一侧的长度方向靠近虚拟栅极22的侧面。此外,每个隔离件26的一部分越过鳍14的顶部。在一个实施例中,由氮化物或其他合适的隔离件材料形成隔离件26。
图2A-图2B示出了通常分别沿A-A线和B-B线切开的图1中所示的实施例FinFET10的截面图。图2C示出了图1中所示的FinFET10的顶视图。如图2A-图2C共同所示,在一个实施例中,虚拟栅极22包括栅氧化物28、多晶硅层30和硬掩膜层32。如图2B所示,虚拟栅极22的栅氧化物28封装或覆盖鳍14的中间部分18。在一个实施例中,在鳍14中形成轻掺杂漏极且至少部分轻掺杂漏极受虚拟栅极22的栅氧化物28保护。
现参见图2A-图2C,用以提高阈值电压良好控制的沟道掺杂FinFET10的工艺流开始。实际上,旋涂用栅氧化物28包裹鳍14的中间部分18以及用外延生长的含硅材料24(如,硅锗、碳化硅等)代替形成鳍14的外部部分20的块体硅后,应用旋涂光刻胶34。之后,适当地开槽或去除旋涂光刻胶34,以露出图2A中所示的虚拟栅极22的硬掩膜层32。在一个实施例中,通过化学下游蚀刻(CDE)去除硬掩膜32上方的旋涂光刻胶34。
现参见图3A-图3C,露出后,去除图2A-图2C中所示的硬掩膜层32。在一个实施例中,通过蚀刻去除硬掩膜32。在一个实施例中,通过干蚀刻、湿蚀刻、化学下游蚀刻(CDE)、化学氧化去除(COR)和其组合中的一种,蚀刻掉硬掩膜32。通过去除硬掩膜32,露出下层多晶硅层30。
现参见图4A-图4C,去除图2A-图2C所示的硬掩膜32之后,去除多晶硅层30。在一个实施例中,通过干蚀刻、湿蚀刻、化学下游蚀刻(CDE)、和其组合中的一种,去除虚拟栅极22的多晶硅层30。通过去除多晶硅层30,露出保护鳍14的中间部分18的栅氧化物28。
现参见图5A-图5C,去除图4A-图4C中所示的多晶硅层30且露出栅氧化物28之后,进行离子注入36。实际上,穿过设置在鳍14的中间部分18上方的栅氧化物28,将离子注入到鳍14的中间部分18中。在一个实施例中,在温度范围介于大约25℃(如,室温)到大约600℃之间进行离子注入36。在一个实施例中,离子注入36采用n型掺杂物或p型掺杂物。在一个实施例中,离子注入36具有正入射,即,离子束垂直于晶圆表面。在一个实施例中,离子注入36具有角度入射或倾斜入射。实际上,可以使用不同角度将掺杂物原子设置在需要的位置。
由于注入鳍14的中间部分18的离子必须穿过栅氧化物28,所以,可以更准确地控制掺杂物等级或浓度。此外,由于使用后鳍掺杂集成方案,所以掺杂物损耗会更少。换句话说,在离子注入36和通过后栅极集成方案实现完全填充之间存在更少的工艺步骤。
现参见图6A-图6C,离子注入36之后,去除剩余的任意旋涂光刻胶34(参见图5A-图5C)。之后,参见图7A-图7C,进行退火工艺38以修补鳍14内的残留损伤。在一个实施例中,在温度范围介于大约800℃到大约1200℃之间,进行退火工艺38,时间介于大约1微秒(μs)至大约10秒(s)之间。在一个实施例中,离子注入36之后,立即进行退火工艺38,以试图修补鳍14的损伤以及活化掺杂原子。
现参见图8A-图8C,不去除图3A-图3C所示的整个多晶硅层30,而只去除多晶硅层30的一部分,以形成多晶硅隔离件40。如图所示,多晶硅隔离件40靠近栅氧化物28且用于保护鳍14的中间部分18。现参见图9A-图9C,在形成多晶硅隔离件40之后,进行离子注入36。像之前那样,穿过设置在鳍14的中间部分18上方的栅氧化物28,将离子注入到鳍14的中间部分18中。
现参见图10A-图10C,在离子注入36之后,去除剩余的任何旋涂光刻胶34(参见图9A-图9C)。之后,如图11A-图11C所示,进行退火工艺38以修补鳍14内的残留损伤。在一个实施例中,多晶硅隔离件40最小化了退火工艺过程中的掺杂物损耗。例如,在形成多晶硅隔离件40之后,使用具有正入射的离子注入,鳍14和多晶硅隔离件40均掺杂有大约相同的掺杂物浓度。与不使用多晶硅隔离件40相比,在退火工艺过程中,掺杂外的扩散被抑制。因此,允许使用更少的注入剂量,以实现鳍14中的相同掺杂浓度。
接着,如图12A-图12C所示,去除多晶硅隔离件40。在一个实施例中,通过干蚀刻、湿蚀刻、化学下游蚀刻、和其组合中的一种,去除多晶硅隔离件40。
在一个实施例中,在图5A-图5C中所示的离子注入36后,在进行如图7A-图7C中所示的退火工艺38之前,可在栅氧化物28的上方形成虚拟多晶硅层30(例如,如图3A-图3C),以试图防止鳍14受到残留损伤。在一个实施例中,可能会形成这样的虚拟多晶硅层30,而不会形成多晶硅隔离件40。
现参见图13,其示出了控制FinFET10中阈值电压的实施例方法42。在方框44中,在鳍14的中间部分的上方形成虚拟栅极22。如图1所示,鳍14的中间部分18设置在未受虚拟栅极22保护的鳍的外部部分20之间。在方框46中,鳍14的外部部分20被去除且由外延生长的含硅材料24代替。
在方框48中,在虚拟栅极22和外延生长的含硅材料24的上方应用旋涂光刻胶34,然后去除虚拟栅极22的硬掩膜层32上方的旋涂光刻胶34。在方框50中,蚀刻掉虚拟栅极22的硬掩膜层32和多晶硅层30,以露出虚拟栅极22的栅氧化物28。如图1所示,栅氧化物28设置在鳍14的中间部分18的上方。在方框52中,穿过设置在鳍14的中间部分18上方的栅氧化物28,将离子注入到鳍14的中间部分18中。如上述,离子注入之后,可去除任何剩余的旋涂光刻胶34,并且可进行用于修补鳍内残留损伤的退火工艺。
现参见图14,其示出了控制FinFET10内阈值电压的实施例方法54。在方框56中,在鳍14的中间部分的上方形成虚拟栅极22。如图1所示,鳍14的中间部分18设置在未受虚拟栅极22保护的鳍的外部部分20之间。在方框58中,鳍14的外部部分20被去除且由外延生长的含硅材料24代替。
在方框60中,在虚拟栅极22和外延生长的含硅材料24的上方应用旋涂光刻胶34,然后去除虚拟栅极22的硬掩膜层32上方的旋涂光刻胶34。在方框62中,蚀刻掉虚拟栅极22的硬掩膜层32和多晶硅层30的一部分,以露出虚拟栅极22的栅氧化物28和形成多晶硅隔离件40。如图1所示,栅氧化物28设置在鳍14的中间部分18的上方。在方框64中,穿过设置在鳍14的中间部分18上方的栅氧化物28,将离子注入到鳍14的中间部分18中。如上所述,注入离子之后,可去除任意剩余的旋涂光刻胶34,并且可进行修补鳍14内残留损伤的退火工艺。
现参见图15,其示出了控制FinFET10内阈值电压的实施例方法66。在方框68中,在鳍14的中间部分的上方形成虚拟栅极22。如图1所示,鳍14的中间部分18设置在未受虚拟栅极22保护的鳍的外部部分20之间。在方法70中,鳍14的外部部分20被去除且由外延生长的含硅材料24代替。
在方框72中,在虚拟栅极22和外延生长的含硅材料24的上方应用旋涂光刻胶34,然后去除虚拟栅极22的硬掩膜层32上方的旋涂光刻胶34。在方框74中,蚀刻掉虚拟栅极22的硬掩膜层32和多晶硅层30的一部分,以露出虚拟栅极22的栅氧化物28和形成多晶硅隔离件40。如图1所示,栅氧化物28设置在鳍14的中间部分18的上方。在方框76中,穿过设置在鳍14的中间部分18上方的栅氧化物28,将离子注入到鳍14的中间部分18中。在方框78中,可进行修补鳍14内残留损伤的退火工艺。
综上所述,应该了解,形成本发明中的实施例FinFET10的一个或多个工艺提供了诸多优点。例如,可精确地控制鳍14内的掺杂物等级或浓度。这是因为(至少是部分原因)用栅氧化物28的薄层、虚拟多晶硅隔离件40、和/或新的虚拟多晶硅层(未示出)封装或保护鳍14。并且,使用虚拟多晶硅隔离件40和/或新的虚拟多晶硅层(未示出)可更好地封装或保护鳍14。此外,形成实施例FinFET10的工艺允许用于pFETs的epi-SixGey鳍以及用于nFETs的epi-SixCy、SiP和SiCP鳍保留应力。
控制鳍式场效应晶体管(FinFET)的阈值电压的实施例方法包括:在鳍的中间部分的上方形成虚拟栅极,鳍的中间部分设置在未受虚拟栅极保护的鳍的外部部分之间;去除鳍的外部部分且用外延生长的含硅材料代替鳍的外部部分;在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶;蚀刻掉虚拟栅极的硬掩膜和多晶硅以露出虚拟栅极的栅氧化物,栅氧化物设置在鳍的中间部分的上方;以及穿过设置在鳍的中间部分的上方的栅氧化层,将离子注入到鳍的中间部分中。
控制鳍式场效应晶体管(FinFET)的阈值电压的实施例方法包括:在鳍的中间部分的上方形成虚拟栅极,鳍的中间部分设置在未受虚拟栅极保护的鳍的外部部分之间;去除鳍的外部部分且用外延生长的含硅材料代替鳍的外部部分;在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶;蚀刻掉虚拟栅极的硬掩膜层和多晶硅层的一部分以露出虚拟栅极的栅氧化物和形成多晶硅隔离件,其中,栅氧化物设置在鳍的中间部分的上方;以及穿过设置在鳍的中间部分的上方的栅氧化物,将离子注入到鳍的中间部分中。
控制鳍式场效应晶体管(FinFET)内阈值电压的实施例方法包括:在鳍的中间部分的上方形成虚拟栅极;用外延生长的含硅材料代替未受虚拟栅极保护的鳍的外部部分;在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶;蚀刻掉虚拟栅极的硬掩膜层和多晶硅层以露出虚拟栅极的栅氧化物,栅氧化物设置在鳍的中间部分的上方;穿过设置在鳍的中间部分的上方的栅氧化物,将离子注入到鳍的中间部分中;以及进行退火工艺以使鳍重结晶。
虽然本发明提供了示出的实施例,但是,本说明并不构成限制意义。参考本说明,示出的实施例的不同修改和组合以及其他实施例对本领域的技术人员来说是显而易见的。因此,所附权利要求包括任何这样的修改或实施例。
Claims (18)
1.一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法,包括:
在鳍的中间部分的上方形成虚拟栅极,所述鳍的所述中间部分设置在所述鳍的未受所述虚拟栅极保护的外部部分之间;
去除所述鳍的所述外部部分并用外延生长的含硅材料代替所述鳍的所述外部部分;
在所述虚拟栅极和所述外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除所述虚拟栅极的硬掩膜上方的所述旋涂光刻胶;
蚀刻掉所述硬掩膜和所述虚拟栅极的多晶硅,以露出所述虚拟栅极的栅氧化物,所述栅氧化物设置在所述鳍的所述中间部分的上方;
穿过设置在所述鳍的所述中间部分上方的所述栅氧化物,将离子注入到所述鳍的所述中间部分中;以及
进行退火工艺以重结晶所述鳍,当沿着设置在所述鳍的所述中间部分上方的所述栅氧化物设置虚拟隔离件时,进行所述退火工艺。
2.根据权利要求1所述的方法,进一步包括:在注入所述离子之后,去除剩余的旋涂光刻胶,然后进行退火工艺以重结晶所述鳍。
3.根据权利要求1所述的方法,进一步包括:在25℃到600℃之间的温度条件下进行离子注入。
4.根据权利要求1所述的方法,进一步包括:进行退火工艺以重结晶所述鳍,在离子注入之后立即进行所述退火工艺。
5.根据权利要求1所述的方法,进一步包括:进行退火工艺以重结晶所述鳍,在设置于所述鳍的所述中间部分上方的所述栅氧化物的上方形成保护层之后进行所述退火工艺。
6.根据权利要求1所述的方法,进一步包括:通过化学下游蚀刻去除所述虚拟栅极的所述硬掩膜上方的所述旋涂光刻胶。
7.根据权利要求1所述的方法,进一步包括:通过干蚀刻、湿蚀刻、化学下游蚀刻、化学氧化去除和它们的组合中的一种工艺,蚀刻掉所述硬掩膜。
8.根据权利要求1所述的方法,进一步包括:通过干蚀刻、湿蚀刻、化学下游蚀刻和它们的组合中的一种工艺,蚀刻掉所述虚拟栅极的所述多晶硅。
9.根据权利要求1所述的方法,进一步包括:在形成所述虚拟栅极之前,在所述鳍的所述中间部分中形成轻掺杂漏极。
10.根据权利要求1所述的方法,其中,所述外延生长的含硅材料是硅锗(SiGe)。
11.根据权利要求1所述的方法,其中,所述外延生长的含硅材料是掺杂有碳化物的硅(SiC)、掺杂有磷的硅(SiP)和掺杂有碳和磷的硅(SiCP)中的一种。
12.一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法,包括:
在鳍的中间部分的上方形成虚拟栅极,所述鳍的所述中间部分设置在所述鳍的未受所述虚拟栅极保护的外部部分之间;
去除所述鳍的所述外部部分并用外延生长的含硅材料代替所述鳍的所述外部部分;
在所述虚拟栅极和所述外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除所述虚拟栅极的硬掩膜上方的所述旋涂光刻胶;
蚀刻掉所述硬掩膜和所述虚拟栅极的多晶硅的一部分,以露出所述虚拟栅极的栅氧化物并形成多晶硅隔离件,所述栅氧化物设置在所述鳍的所述中间部分的上方;以及
穿过设置在所述鳍的所述中间部分上方的所述栅氧化物,将离子注入到所述鳍的所述中间部分中。
13.根据权利要求12所述的方法,进一步包括:在25℃到600℃之间的温度条件下进行离子注入。
14.根据权利要求12所述的方法,进一步包括:进行退火工艺以重结晶所述鳍,在离子注入之后立即进行所述退火工艺。
15.根据权利要求12所述的方法,进一步包括:进行退火工艺以重结晶所述鳍,在去除所述多晶硅隔离件之前进行所述退火工艺。
16.一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法,包括:
在鳍的中间部分的上方形成虚拟栅极;
用外延生长的含硅材料代替所述鳍的未受所述虚拟栅极保护的外部部分;
在所述虚拟栅极和所述外延生长的含硅材料的上方涂覆旋涂光刻胶,然后去除所述虚拟栅极的硬掩膜上方的所述旋涂光刻胶;
蚀刻掉所述硬掩膜和所述虚拟栅极的多晶硅,以露出所述虚拟栅极的栅氧化物,所述栅氧化物设置在所述鳍的所述中间部分的上方;
穿过设置在所述鳍的所述中间部分上方的所述栅氧化物,将离子注入到所述鳍的所述中间部分中;
在设置于所述鳍的所述中间部分上方的所述栅氧化物的上方形成虚拟隔离件和保护层中的至少一个;以及
进行退火工艺以重结晶所述鳍。
17.根据权利要求16所述的方法,进一步包括:在注入所述离子之后,去除剩余的旋涂光刻胶,其中,在25℃到600℃之间的温度条件下进行所述离子注入。
18.根据权利要求16所述的方法,进一步包括:在离子注入之后,立即进行所述退火工艺。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/763,280 US8853025B2 (en) | 2013-02-08 | 2013-02-08 | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
US13/763,280 | 2013-02-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103985636A CN103985636A (zh) | 2014-08-13 |
CN103985636B true CN103985636B (zh) | 2017-04-12 |
Family
ID=51277555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310177806.3A Active CN103985636B (zh) | 2013-02-08 | 2013-05-14 | 调整多阈值电压的FinFET/三栅极沟道掺杂 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8853025B2 (zh) |
CN (1) | CN103985636B (zh) |
Families Citing this family (222)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9064892B2 (en) | 2011-08-30 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same |
US9368619B2 (en) | 2013-02-08 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for inducing strain in vertical semiconductor columns |
US9466668B2 (en) | 2013-02-08 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inducing localized strain in vertical nanowire transistors |
US9209247B2 (en) | 2013-05-10 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned wrapped-around structure |
US9455335B2 (en) * | 2013-11-14 | 2016-09-27 | Varian Semiconductor Equiment Associates, Inc | Techniques for ion implantation of non-planar field effect transistors |
US9853154B2 (en) | 2014-01-24 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Embedded source or drain region of transistor with downward tapered region under facet region |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9461170B2 (en) | 2014-04-23 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company Ltd. | FinFET with ESD protection |
US9299803B2 (en) | 2014-07-16 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for semiconductor device fabrication |
US10263108B2 (en) | 2014-08-22 | 2019-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal-insensitive epitaxy formation |
DE102015100860A1 (de) | 2014-08-22 | 2016-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metallunempfindliche Epitaxiebildung |
US9385197B2 (en) | 2014-08-29 | 2016-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor structure with contact over source/drain structure and method for forming the same |
US9450093B2 (en) | 2014-10-15 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device structure and manufacturing method thereof |
US9349652B1 (en) | 2014-12-12 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor device with different threshold voltages |
US9780214B2 (en) | 2014-12-22 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including Fin- FET and manufacturing method thereof |
US9515071B2 (en) | 2014-12-24 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Asymmetric source/drain depths |
US9876114B2 (en) | 2014-12-30 | 2018-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D FinFET metal gate |
US9450046B2 (en) | 2015-01-08 | 2016-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor structure with fin structure and wire structure and method for forming the same |
US9991384B2 (en) | 2015-01-15 | 2018-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
US9391078B1 (en) | 2015-01-16 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for finFET devices |
US9349859B1 (en) | 2015-01-29 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Top metal pads as local interconnectors of vertical transistors |
US9406680B1 (en) | 2015-02-13 | 2016-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
US9991343B2 (en) | 2015-02-26 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company Ltd. | LDD-free semiconductor structure and manufacturing method of the same |
US9564493B2 (en) | 2015-03-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same |
US9406675B1 (en) | 2015-03-16 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company Ltd. | FinFET structure and method of manufacturing the same |
US9570557B2 (en) | 2015-04-29 | 2017-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Tilt implantation for STI formation in FinFET structures |
US10483262B2 (en) | 2015-05-15 | 2019-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual nitride stressor for semiconductor device and method of manufacturing |
US9530889B2 (en) | 2015-05-21 | 2016-12-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9647071B2 (en) | 2015-06-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFET structures and methods of forming the same |
US9449975B1 (en) | 2015-06-15 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices and methods of forming |
US9685368B2 (en) | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
US9818872B2 (en) | 2015-06-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9583623B2 (en) | 2015-07-31 | 2017-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof |
US9666581B2 (en) | 2015-08-21 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with source/drain structure and method of fabrication thereof |
US10164096B2 (en) | 2015-08-21 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9647122B2 (en) | 2015-09-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
US10032873B2 (en) | 2015-09-15 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
US9680017B2 (en) | 2015-09-16 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including Fin FET and manufacturing method thereof |
US10121858B2 (en) | 2015-10-30 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Elongated semiconductor structure planarization |
US9960273B2 (en) | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
US11264452B2 (en) | 2015-12-29 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hetero-tunnel field-effect transistor (TFET) having a tunnel barrier formed directly above channel region, directly below first source/drain region and adjacent gate electrode |
DE102016119024B4 (de) | 2015-12-29 | 2023-12-21 | Taiwan Semiconductor Manufacturing Co. Ltd. | Verfahren zum Herstellen einer FinFET-Vorrichtung mit epitaktischen Elementen mit flacher Oberseite |
US10490552B2 (en) | 2015-12-29 | 2019-11-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device having flat-top epitaxial features and method of making the same |
US9825036B2 (en) | 2016-02-23 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for semiconductor device |
US10002867B2 (en) | 2016-03-07 | 2018-06-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
US9748389B1 (en) | 2016-03-25 | 2017-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for semiconductor device fabrication with improved source drain epitaxy |
US10340383B2 (en) * | 2016-03-25 | 2019-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having stressor layer |
US10163898B2 (en) | 2016-04-25 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods of forming FinFETs |
US10079291B2 (en) | 2016-05-04 | 2018-09-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
US9899382B2 (en) | 2016-06-01 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure with different gate profile and method for forming the same |
US10008414B2 (en) | 2016-06-28 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for widening Fin widths for small pitch FinFET devices |
US10115624B2 (en) | 2016-06-30 | 2018-10-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of semiconductor integrated circuit fabrication |
US10164098B2 (en) | 2016-06-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device |
US9640540B1 (en) | 2016-07-19 | 2017-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for an SRAM circuit |
US9870926B1 (en) | 2016-07-28 | 2018-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10032877B2 (en) | 2016-08-02 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of forming same |
US10157918B2 (en) | 2016-08-03 | 2018-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10008418B2 (en) | 2016-09-30 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of semiconductor integrated circuit fabrication |
US10026840B2 (en) | 2016-10-13 | 2018-07-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure of semiconductor device with source/drain structures |
US10510618B2 (en) | 2016-10-24 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET EPI channels having different heights on a stepped substrate |
US9865589B1 (en) | 2016-10-31 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of fabricating ESD FinFET with improved metal landing in the drain |
CN108074811A (zh) * | 2016-11-10 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管及其形成方法 |
US10872889B2 (en) | 2016-11-17 | 2020-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor component and fabricating method thereof |
US10529861B2 (en) | 2016-11-18 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structures and methods of forming the same |
US10879354B2 (en) | 2016-11-28 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and forming method thereof |
US10276677B2 (en) | 2016-11-28 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US11437516B2 (en) | 2016-11-28 | 2022-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for growing epitaxy structure of finFET device |
US10453943B2 (en) | 2016-11-29 | 2019-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETS and methods of forming FETS |
US9991165B1 (en) | 2016-11-29 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Asymmetric source/drain epitaxy |
US10510888B2 (en) | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9935173B1 (en) | 2016-11-29 | 2018-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure |
US10290546B2 (en) | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Threshold voltage adjustment for a gate-all-around semiconductor structure |
US10490661B2 (en) | 2016-11-29 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dopant concentration boost in epitaxially formed material |
US10115808B2 (en) | 2016-11-29 | 2018-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | finFET device and methods of forming |
US10515951B2 (en) | 2016-11-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US9812363B1 (en) | 2016-11-29 | 2017-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
US9865595B1 (en) | 2016-12-14 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same |
US10049936B2 (en) | 2016-12-15 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same |
US10510762B2 (en) | 2016-12-15 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain formation technique for fin-like field effect transistor |
US10431670B2 (en) | 2016-12-15 | 2019-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Source and drain formation technique for fin-like field effect transistor |
TWI746673B (zh) | 2016-12-15 | 2021-11-21 | 台灣積體電路製造股份有限公司 | 鰭式場效電晶體裝置及其共形傳遞摻雜方法 |
US10276691B2 (en) | 2016-12-15 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conformal transfer doping method for fin-like field effect transistor |
CN108666210A (zh) * | 2017-03-31 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US10483266B2 (en) | 2017-04-20 | 2019-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flexible merge scheme for source/drain epitaxy regions |
US10475908B2 (en) | 2017-04-25 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabricating the same |
US10373879B2 (en) | 2017-04-26 | 2019-08-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with contracted isolation feature and formation method thereof |
US10522643B2 (en) | 2017-04-26 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate |
US10522417B2 (en) | 2017-04-27 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with different liners for PFET and NFET and method of fabricating thereof |
US10319832B2 (en) | 2017-04-28 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
US10043712B1 (en) | 2017-05-17 | 2018-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
US10147787B1 (en) | 2017-05-31 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
US10347764B2 (en) | 2017-06-30 | 2019-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof |
TWI743252B (zh) | 2017-06-30 | 2021-10-21 | 台灣積體電路製造股份有限公司 | 鰭狀場效電晶體裝置與其形成方法 |
US10269940B2 (en) | 2017-06-30 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10516037B2 (en) | 2017-06-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming shaped source/drain epitaxial layers of a semiconductor device |
US10727226B2 (en) | 2017-07-18 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and method for forming the same |
US10529833B2 (en) | 2017-08-28 | 2020-01-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with a fin and gate structure and method making the same |
US10453753B2 (en) | 2017-08-31 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET |
US10276718B2 (en) | 2017-08-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET having a relaxation prevention anchor |
US10483378B2 (en) | 2017-08-31 | 2019-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial features confined by dielectric fins and spacers |
US10163904B1 (en) | 2017-08-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure |
US10505040B2 (en) | 2017-09-25 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device having a gate with ferroelectric layer |
US10153278B1 (en) | 2017-09-28 | 2018-12-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
US10516032B2 (en) | 2017-09-28 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device |
US10510580B2 (en) | 2017-09-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy fin structures and methods of forming same |
US10804367B2 (en) | 2017-09-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate stacks for stack-fin channel I/O devices and nanowire channel core devices |
US10276697B1 (en) | 2017-10-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance FET with improved reliability performance |
US10522557B2 (en) | 2017-10-30 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Surface topography by forming spacer-like components |
US10847634B2 (en) | 2017-10-30 | 2020-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field effect transistor and method of forming the same |
US10355105B2 (en) | 2017-10-31 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors and methods of forming the same |
US10163623B1 (en) | 2017-10-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch method with surface modification treatment for forming semiconductor structure |
US11404413B2 (en) | 2017-11-08 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
US10680084B2 (en) | 2017-11-10 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial structures for fin-like field effect transistors |
US10366915B2 (en) | 2017-11-15 | 2019-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET devices with embedded air gaps and the fabrication thereof |
US10680106B2 (en) | 2017-11-15 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming source/drain epitaxial stacks |
US10840358B2 (en) | 2017-11-15 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor structure with source/drain structure having modified shape |
US10510619B2 (en) | 2017-11-17 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for manufacturing the same |
US10497628B2 (en) | 2017-11-22 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming epitaxial structures in fin-like field effect transistors |
US10971493B2 (en) | 2017-11-27 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated circuit device with high mobility and system of forming the integrated circuit |
US10840154B2 (en) | 2017-11-28 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co.. Ltd. | Method for forming semiconductor structure with high aspect ratio |
US10804378B2 (en) | 2017-11-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for semiconductor device fabrication with improved epitaxial source/drain proximity control |
US10276692B1 (en) | 2017-11-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin diode structure and methods thereof |
US10319581B1 (en) | 2017-11-30 | 2019-06-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut metal gate process for reducing transistor spacing |
US10510894B2 (en) | 2017-11-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structure having different distances to adjacent FinFET devices |
US10446669B2 (en) | 2017-11-30 | 2019-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain surface treatment for multi-gate field effect transistors |
US10510874B2 (en) * | 2017-11-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
CN110021528A (zh) * | 2018-01-10 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US10461171B2 (en) | 2018-01-12 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with metal gate stacks |
US10522656B2 (en) | 2018-02-28 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd | Forming epitaxial structures in fin field effect transistors |
US10510776B2 (en) | 2018-03-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device with common active area and method for manufacturing the same |
US10854615B2 (en) | 2018-03-30 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET having non-merging epitaxially grown source/drains |
US10522546B2 (en) | 2018-04-20 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd | FinFET devices with dummy fins having multiple dielectric layers |
US11270994B2 (en) | 2018-04-20 | 2022-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor |
US10269655B1 (en) | 2018-05-30 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10644125B2 (en) | 2018-06-14 | 2020-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gates and manufacturing methods thereof |
US10861973B2 (en) | 2018-06-27 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance transistor with a diffusion blocking layer |
US11302535B2 (en) | 2018-06-27 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Performing annealing process to improve fin quality of a FinFET semiconductor |
US10790352B2 (en) | 2018-06-28 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density capacitor implemented using FinFET |
US10388771B1 (en) | 2018-06-28 | 2019-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device for forming cut-metal-gate feature |
US11296225B2 (en) | 2018-06-29 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
US10840375B2 (en) | 2018-06-29 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuits with channel-strain liner |
US10861969B2 (en) | 2018-07-16 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming FinFET structure with reduced Fin buckling |
US10535667B1 (en) | 2018-07-30 | 2020-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array and semiconductor chip |
US10886226B2 (en) | 2018-07-31 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co, Ltd. | Conductive contact having staircase barrier layers |
US11069692B2 (en) | 2018-07-31 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET SRAM cells with dielectric fins |
US10629490B2 (en) | 2018-07-31 | 2020-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field-effect transistor device and method of fabricating the same |
US10879393B2 (en) | 2018-08-14 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of fabricating semiconductor devices having gate structure with bent sidewalls |
US10916659B2 (en) | 2018-09-18 | 2021-02-09 | International Business Machines Corporation | Asymmetric threshold voltage FinFET device by partial channel doping variation |
US10998241B2 (en) | 2018-09-19 | 2021-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective dual silicide formation using a maskless fabrication process flow |
US11437385B2 (en) | 2018-09-24 | 2022-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET SRAM cells with reduced fin pitch |
US11171209B2 (en) | 2018-09-27 | 2021-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US11349008B2 (en) | 2018-09-27 | 2022-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance transistor having a multilayer ferroelectric structure or a ferroelectric layer with a gradient doping profile |
US11094597B2 (en) | 2018-09-28 | 2021-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with fin structures |
US11289583B2 (en) | 2018-09-28 | 2022-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | High aspect ratio gate structure formation |
US11222958B2 (en) | 2018-09-28 | 2022-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance transistor with external ferroelectric structure |
US10700183B2 (en) | 2018-10-19 | 2020-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure and method for forming the same |
US10971605B2 (en) | 2018-10-22 | 2021-04-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dummy dielectric fin design for parasitic capacitance reduction |
US10833167B2 (en) | 2018-10-26 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finFET) device structure and method for forming the same |
US10950730B2 (en) | 2018-10-31 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Merged source/drain features |
US10868183B2 (en) | 2018-10-31 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and methods of forming the same |
US10868185B2 (en) | 2018-11-27 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of forming the same |
US10879379B2 (en) | 2019-05-30 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-gate device and related methods |
US10868174B1 (en) | 2019-06-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Devices with strained isolation features |
US11133223B2 (en) | 2019-07-16 | 2021-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective epitaxy |
US11282934B2 (en) | 2019-07-26 | 2022-03-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for metal gate electrode and method of fabrication |
US10985266B2 (en) | 2019-08-20 | 2021-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of gap filling for semiconductor device |
US11133386B2 (en) | 2019-08-27 | 2021-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-layer fin structure |
US11489063B2 (en) | 2019-08-30 | 2022-11-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method of manufacturing a source/drain feature in a multi-gate semiconductor structure |
US11094821B2 (en) | 2019-09-17 | 2021-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor structure and method with strain effect |
US11342231B2 (en) | 2019-09-17 | 2022-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit device with low threshold voltage |
US11646311B2 (en) | 2019-09-23 | 2023-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of fabricating the same |
US11164868B2 (en) | 2019-09-24 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
US11621224B2 (en) | 2019-09-26 | 2023-04-04 | Taiwan Semiconductor Manufacturing Co. Ltd. | Contact features and methods of fabricating the same in semiconductor devices |
US11482610B2 (en) | 2019-09-26 | 2022-10-25 | Taiwan Semiconductor Manufacturing Co. | Method of forming a gate structure |
US11670551B2 (en) | 2019-09-26 | 2023-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interface trap charge density reduction |
US11728405B2 (en) | 2019-09-28 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stress-inducing silicon liner in semiconductor devices |
US11018257B2 (en) | 2019-10-18 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure having a plurality of threshold voltages and method of forming the same |
US11417748B2 (en) | 2019-10-30 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of fabricating a semiconductor device |
US11244899B2 (en) | 2020-01-17 | 2022-02-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Butted contacts and methods of fabricating the same in semiconductor devices |
US11610822B2 (en) | 2020-01-31 | 2023-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structures for tuning threshold voltage |
US11557590B2 (en) | 2020-02-19 | 2023-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor gate profile optimization |
US11862712B2 (en) | 2020-02-19 | 2024-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of semiconductor device fabrication including growing epitaxial features using different carrier gases |
US10867101B1 (en) * | 2020-02-24 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage reduction between two transistor devices on a same continuous fin |
US11257950B2 (en) | 2020-02-24 | 2022-02-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method for the semiconductor structure |
US11715781B2 (en) | 2020-02-26 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with improved capacitors |
US11515211B2 (en) | 2020-02-27 | 2022-11-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut EPI process and structures |
US11374128B2 (en) | 2020-02-27 | 2022-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for air gap inner spacer in gate-all-around devices |
US11769820B2 (en) | 2020-02-27 | 2023-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of manufacturing a FinFET by forming a hollow area in the epitaxial source/drain region |
CN113113359A (zh) | 2020-02-27 | 2021-07-13 | 台湾积体电路制造股份有限公司 | 半导体装置的制造方法 |
US11404570B2 (en) | 2020-02-27 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with embedded ferroelectric field effect transistors |
TW202139270A (zh) | 2020-02-27 | 2021-10-16 | 台灣積體電路製造股份有限公司 | 半導體裝置的形成方法 |
DE102020126060A1 (de) | 2020-03-31 | 2021-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mehrschichtige high-k-gatedielektrikumstruktur |
US12022643B2 (en) | 2020-03-31 | 2024-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-layer high-k gate dielectric structure |
US11271096B2 (en) | 2020-04-01 | 2022-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming fin field effect transistor device structure |
US11309398B2 (en) | 2020-04-01 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method for the semiconductor device |
US11670692B2 (en) | 2020-05-13 | 2023-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-all-around devices having self-aligned capping between channel and backside power rail |
US11791218B2 (en) | 2020-05-20 | 2023-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dipole patterning for CMOS devices |
US11302798B2 (en) | 2020-05-29 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with air gate spacer and air gate cap |
US11374006B2 (en) | 2020-06-12 | 2022-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
US11315924B2 (en) | 2020-06-30 | 2022-04-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structure for preventing unintentional merging of epitaxially grown source/drain |
US11355587B2 (en) | 2020-08-06 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain EPI structure for device boost |
US11728391B2 (en) | 2020-08-07 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | 2d-channel transistor structure with source-drain engineering |
US12046479B2 (en) | 2020-08-13 | 2024-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-containing STI liner for SiGe channel |
US12002766B2 (en) | 2020-08-18 | 2024-06-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure having isolations between fins and comprising materials with different thermal expansion coefficients (CTE) |
US11615962B2 (en) | 2020-09-11 | 2023-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods thereof |
US11600533B2 (en) | 2020-09-18 | 2023-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device fabrication methods and structures thereof |
US11349002B2 (en) | 2020-09-25 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof |
US11521971B2 (en) | 2020-11-13 | 2022-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate dielectric having a non-uniform thickness profile |
US11527622B2 (en) | 2021-01-08 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Effective work function tuning via silicide induced interface dipole modulation for metal gates |
US11784218B2 (en) | 2021-01-08 | 2023-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate air spacer protection during source/drain via hole etching |
US11658216B2 (en) | 2021-01-14 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for metal gate boundary isolation |
US12035532B2 (en) | 2021-01-15 | 2024-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory array and memory device |
US11532522B2 (en) | 2021-01-19 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain EPI structure for improving contact quality |
US11626495B2 (en) | 2021-02-26 | 2023-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance |
US11855143B2 (en) | 2021-02-26 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods thereof |
US11688768B2 (en) | 2021-03-05 | 2023-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with source/drain spacers |
US11876119B2 (en) | 2021-03-05 | 2024-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with gate isolation features and fabrication method of the same |
US11658074B2 (en) | 2021-04-08 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device with source/drain modulation |
US11784228B2 (en) | 2021-04-09 | 2023-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process and structure for source/drain contacts |
US11996484B2 (en) | 2021-05-13 | 2024-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers |
US11688645B2 (en) | 2021-06-17 | 2023-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and formation method of semiconductor device with fin structures |
US11942329B2 (en) | 2021-07-23 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation method of semiconductor device with dielectric isolation structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102646599A (zh) * | 2012-04-09 | 2012-08-22 | 北京大学 | 一种大规模集成电路中FinFET的制备方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100487567B1 (ko) * | 2003-07-24 | 2005-05-03 | 삼성전자주식회사 | 핀 전계효과 트랜지스터 형성 방법 |
KR100618893B1 (ko) * | 2005-04-14 | 2006-09-01 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
US7449373B2 (en) * | 2006-03-31 | 2008-11-11 | Intel Corporation | Method of ion implanting for tri-gate devices |
US20080057636A1 (en) * | 2006-08-31 | 2008-03-06 | Richard Lindsay | Strained semiconductor device and method of making same |
US8188546B2 (en) * | 2009-08-18 | 2012-05-29 | International Business Machines Corporation | Multi-gate non-planar field effect transistor structure and method of forming the structure using a dopant implant process to tune device drive current |
US8313999B2 (en) * | 2009-12-23 | 2012-11-20 | Intel Corporation | Multi-gate semiconductor device with self-aligned epitaxial source and drain |
US8685825B2 (en) * | 2011-07-27 | 2014-04-01 | Advanced Ion Beam Technology, Inc. | Replacement source/drain finFET fabrication |
CN103137686B (zh) * | 2011-11-24 | 2016-01-06 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其制造方法 |
US8697523B2 (en) * | 2012-02-06 | 2014-04-15 | International Business Machines Corporation | Integration of SMT in replacement gate FINFET process flow |
US8617957B1 (en) * | 2012-09-10 | 2013-12-31 | International Business Machines Corporation | Fin bipolar transistors having self-aligned collector and emitter regions |
-
2013
- 2013-02-08 US US13/763,280 patent/US8853025B2/en active Active
- 2013-05-14 CN CN201310177806.3A patent/CN103985636B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102646599A (zh) * | 2012-04-09 | 2012-08-22 | 北京大学 | 一种大规模集成电路中FinFET的制备方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103985636A (zh) | 2014-08-13 |
US8853025B2 (en) | 2014-10-07 |
US20140227850A1 (en) | 2014-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103985636B (zh) | 调整多阈值电压的FinFET/三栅极沟道掺杂 | |
US7932144B2 (en) | Semiconductor structure and method of forming the structure | |
JP5043314B2 (ja) | 勾配付き組み込みシリコン−ゲルマニウムのソース−ドレイン及び/又は延長部をもつ、歪みp型mosfetを製造する方法 | |
US8557692B2 (en) | FinFET LDD and source drain implant technique | |
US10720529B2 (en) | Source/drain junction formation | |
US8574995B2 (en) | Source/drain doping method in 3D devices | |
CN104662666B (zh) | 具有屏蔽层的深耗尽型mos晶体管及其方法 | |
US20120276695A1 (en) | Strained thin body CMOS with Si:C and SiGe stressor | |
US9590037B2 (en) | p-FET with strained silicon-germanium channel | |
US8361894B1 (en) | Methods of forming FinFET semiconductor devices with different fin heights | |
TWI469344B (zh) | 具有包含效能增進材料成分之受應變通道區的電晶體 | |
JP2013030776A (ja) | 代用ソース/ドレインフィンfet加工 | |
JP2004207714A (ja) | 二重ゲート型電界効果トランジスタおよびその製造方法 | |
US20170005012A1 (en) | Stacked short and long channel finfets | |
CN103426768B (zh) | 半导体器件制造方法 | |
US7939399B2 (en) | Semiconductor device having a strained semiconductor alloy concentration profile | |
US9947774B2 (en) | Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping | |
US20080057665A1 (en) | Strained semiconductor device and method of making same | |
CN202633241U (zh) | 晶体管 | |
US8399328B2 (en) | Transistor and method for forming the same | |
US20160204226A1 (en) | Stress modulation in field effect transistors in reducing contact resistance and increasing charge carrier mobility | |
CN109087859A (zh) | 一种半导体器件的制造方法 | |
CN100578812C (zh) | 半导体器件以及半导体器件的制造方法 | |
TW201431007A (zh) | 半導體裝置結構及形成互補式金屬氧化物半導體積體電路結構之方法 | |
KR20120044800A (ko) | 반도체 소자 및 이의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |