JP2012504327A5 - - Google Patents
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- Publication number
- JP2012504327A5 JP2012504327A5 JP2011528256A JP2011528256A JP2012504327A5 JP 2012504327 A5 JP2012504327 A5 JP 2012504327A5 JP 2011528256 A JP2011528256 A JP 2011528256A JP 2011528256 A JP2011528256 A JP 2011528256A JP 2012504327 A5 JP2012504327 A5 JP 2012504327A5
- Authority
- JP
- Japan
- Prior art keywords
- forming
- cavity
- protective layer
- temperature
- semiconductor alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102008049733A DE102008049733B3 (de) | 2008-09-30 | 2008-09-30 | Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand zum Kanalgebiet und Verfahren zur Herstellung des Transistors |
| DE102008049733.9 | 2008-09-30 | ||
| US12/552,642 | 2009-09-02 | ||
| US12/552,642 US8071442B2 (en) | 2008-09-30 | 2009-09-02 | Transistor with embedded Si/Ge material having reduced offset to the channel region |
| PCT/EP2009/007002 WO2010037523A1 (en) | 2008-09-30 | 2009-09-29 | A transistor with embedded si/ge material having reduced offset to the channel region |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012504327A JP2012504327A (ja) | 2012-02-16 |
| JP2012504327A5 true JP2012504327A5 (enExample) | 2012-11-08 |
| JP5795735B2 JP5795735B2 (ja) | 2015-10-14 |
Family
ID=42056439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011528256A Active JP5795735B2 (ja) | 2008-09-30 | 2009-09-29 | チャネル領域への減少させられたオフセットを有する埋め込みSi/Ge材質を伴うトランジスタ |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8071442B2 (enExample) |
| JP (1) | JP5795735B2 (enExample) |
| KR (1) | KR101608908B1 (enExample) |
| CN (1) | CN102282668B (enExample) |
| DE (1) | DE102008049733B3 (enExample) |
| WO (1) | WO2010037523A1 (enExample) |
Families Citing this family (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102473642B (zh) * | 2009-07-08 | 2014-11-12 | 株式会社东芝 | 半导体装置及其制造方法 |
| US8299564B1 (en) * | 2009-09-14 | 2012-10-30 | Xilinx, Inc. | Diffusion regions having different depths |
| US8405160B2 (en) * | 2010-05-26 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-strained source/drain structures |
| DE102010029532B4 (de) * | 2010-05-31 | 2012-01-26 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Transistor mit eingebettetem verformungsinduzierenden Material, das in diamantförmigen Aussparungen auf der Grundlage einer Voramorphisierung hergestellt ist |
| US8492234B2 (en) | 2010-06-29 | 2013-07-23 | International Business Machines Corporation | Field effect transistor device |
| DE102010063292B4 (de) | 2010-12-16 | 2016-08-04 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung gering diffundierter Drain- und Sourcegebiete in CMOS-Transistoren für Anwendungen mit hoher Leistungsfähigkeit und geringer Leistung |
| KR20120073727A (ko) * | 2010-12-27 | 2012-07-05 | 삼성전자주식회사 | 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템 |
| DE102010064284B4 (de) * | 2010-12-28 | 2016-03-31 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Herstellung eines Transistors mit einer eingebetteten Sigma-förmigen Halbleiterlegierung mit erhöhter Gleichmäßigkeit |
| US8946064B2 (en) * | 2011-06-16 | 2015-02-03 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
| US8476169B2 (en) * | 2011-10-17 | 2013-07-02 | United Microelectronics Corp. | Method of making strained silicon channel semiconductor structure |
| US8524563B2 (en) * | 2012-01-06 | 2013-09-03 | GlobalFoundries, Inc. | Semiconductor device with strain-inducing regions and method thereof |
| US8866230B2 (en) * | 2012-04-26 | 2014-10-21 | United Microelectronics Corp. | Semiconductor devices |
| US8674447B2 (en) | 2012-04-27 | 2014-03-18 | International Business Machines Corporation | Transistor with improved sigma-shaped embedded stressor and method of formation |
| KR101986534B1 (ko) | 2012-06-04 | 2019-06-07 | 삼성전자주식회사 | 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법 |
| KR101909204B1 (ko) | 2012-06-25 | 2018-10-17 | 삼성전자 주식회사 | 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법 |
| CN103594370B (zh) * | 2012-08-16 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
| US8541281B1 (en) | 2012-08-17 | 2013-09-24 | Globalfoundries Inc. | Replacement gate process flow for highly scaled semiconductor devices |
| US8969190B2 (en) | 2012-08-24 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a layer of silicon on a layer of silicon/germanium |
| KR20140039544A (ko) | 2012-09-24 | 2014-04-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| US9029919B2 (en) | 2013-02-01 | 2015-05-12 | Globalfoundries Inc. | Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer |
| US9040394B2 (en) | 2013-03-12 | 2015-05-26 | Samsung Electronics Co., Ltd. | Method for fabricating a semiconductor device |
| US8951877B2 (en) * | 2013-03-13 | 2015-02-10 | Globalfoundries Inc. | Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment |
| DE102013105705B4 (de) * | 2013-03-13 | 2020-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung und dessen Herstellung |
| US20150048422A1 (en) * | 2013-08-16 | 2015-02-19 | International Business Machines Corporation | A method for forming a crystalline compound iii-v material on a single element substrate |
| US9054217B2 (en) | 2013-09-17 | 2015-06-09 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device having an embedded source/drain |
| CN104517901B (zh) * | 2013-09-29 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的形成方法 |
| US9691898B2 (en) * | 2013-12-19 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Germanium profile for channel strain |
| US9831341B2 (en) * | 2014-06-16 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for integrated circuit |
| US10084063B2 (en) * | 2014-06-23 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
| US10026837B2 (en) * | 2015-09-03 | 2018-07-17 | Texas Instruments Incorporated | Embedded SiGe process for multi-threshold PMOS transistors |
| US20170141228A1 (en) * | 2015-11-16 | 2017-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor and manufacturing method thereof |
| US10141426B2 (en) * | 2016-02-08 | 2018-11-27 | International Business Macahines Corporation | Vertical transistor device |
| CN113611736B (zh) * | 2020-05-29 | 2022-11-22 | 联芯集成电路制造(厦门)有限公司 | 半导体元件及其制作方法 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0135147B1 (ko) * | 1994-07-21 | 1998-04-22 | 문정환 | 트랜지스터 제조방법 |
| JP2701803B2 (ja) * | 1995-08-28 | 1998-01-21 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6071783A (en) * | 1998-08-13 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Pseudo silicon on insulator MOSFET device |
| JP3424667B2 (ja) * | 2000-10-13 | 2003-07-07 | 株式会社デンソー | 半導体基板の製造方法 |
| US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
| CN1303672C (zh) * | 2003-11-11 | 2007-03-07 | 旺宏电子股份有限公司 | 氮化物只读存储器的制造方法 |
| US7045407B2 (en) * | 2003-12-30 | 2006-05-16 | Intel Corporation | Amorphous etch stop for the anisotropic etching of substrates |
| JP4797358B2 (ja) * | 2004-10-01 | 2011-10-19 | 富士電機株式会社 | 半導体装置の製造方法 |
| US20060115949A1 (en) | 2004-12-01 | 2006-06-01 | Freescale Semiconductor, Inc. | Semiconductor fabrication process including source/drain recessing and filling |
| JP4369359B2 (ja) | 2004-12-28 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
| JP2006196910A (ja) | 2005-01-14 | 2006-07-27 | Samsung Electronics Co Ltd | 半導体基板のインサイチュ洗浄方法及びこれを採用する半導体素子の製造方法 |
| US7078285B1 (en) | 2005-01-21 | 2006-07-18 | Sony Corporation | SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material |
| JP5055771B2 (ja) | 2005-02-28 | 2012-10-24 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| US7544576B2 (en) * | 2005-07-29 | 2009-06-09 | Freescale Semiconductor, Inc. | Diffusion barrier for nickel silicides in a semiconductor fabrication process |
| WO2007049510A1 (ja) * | 2005-10-27 | 2007-05-03 | Tokyo Electron Limited | 処理方法及び記録媒体 |
| US7422950B2 (en) * | 2005-12-14 | 2008-09-09 | Intel Corporation | Strained silicon MOS device with box layer between the source and drain regions |
| US7525160B2 (en) | 2005-12-27 | 2009-04-28 | Intel Corporation | Multigate device with recessed strain regions |
| JP4410195B2 (ja) * | 2006-01-06 | 2010-02-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP5119604B2 (ja) * | 2006-03-16 | 2013-01-16 | ソニー株式会社 | 半導体装置の製造方法 |
| US7528072B2 (en) | 2006-04-20 | 2009-05-05 | Texas Instruments Incorporated | Crystallographic preferential etch to define a recessed-region for epitaxial growth |
| JP2007305730A (ja) * | 2006-05-10 | 2007-11-22 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
| DE102006030268B4 (de) | 2006-06-30 | 2008-12-18 | Advanced Micro Devices Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, insbesondere eines FETs |
| US20080220579A1 (en) * | 2007-03-07 | 2008-09-11 | Advanced Micro Devices, Inc. | Stress enhanced mos transistor and methods for its fabrication |
| US7691752B2 (en) | 2007-03-30 | 2010-04-06 | Intel Corporation | Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby |
| DE102007063229B4 (de) * | 2007-12-31 | 2013-01-24 | Advanced Micro Devices, Inc. | Verfahren und Teststruktur zur Überwachung von Prozesseigenschaften für die Herstellung eingebetteter Halbleiterlegierungen in Drain/Source-Gebieten |
| KR100971414B1 (ko) * | 2008-04-18 | 2010-07-21 | 주식회사 하이닉스반도체 | 스트레인드 채널을 갖는 반도체 소자 및 그 제조방법 |
| US7838372B2 (en) * | 2008-05-22 | 2010-11-23 | Infineon Technologies Ag | Methods of manufacturing semiconductor devices and structures thereof |
-
2008
- 2008-09-30 DE DE102008049733A patent/DE102008049733B3/de active Active
-
2009
- 2009-09-02 US US12/552,642 patent/US8071442B2/en active Active
- 2009-09-29 CN CN200980147114.6A patent/CN102282668B/zh active Active
- 2009-09-29 KR KR1020117009991A patent/KR101608908B1/ko active Active
- 2009-09-29 JP JP2011528256A patent/JP5795735B2/ja active Active
- 2009-09-29 WO PCT/EP2009/007002 patent/WO2010037523A1/en not_active Ceased
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