CN103247524B - ∑形凹槽的制作方法 - Google Patents

∑形凹槽的制作方法 Download PDF

Info

Publication number
CN103247524B
CN103247524B CN201310156183.1A CN201310156183A CN103247524B CN 103247524 B CN103247524 B CN 103247524B CN 201310156183 A CN201310156183 A CN 201310156183A CN 103247524 B CN103247524 B CN 103247524B
Authority
CN
China
Prior art keywords
star
semiconductor substrate
etching gas
manufacture method
etch process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310156183.1A
Other languages
English (en)
Other versions
CN103247524A (zh
Inventor
李全波
李芳�
张瑜
方精训
彭树根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201310156183.1A priority Critical patent/CN103247524B/zh
Publication of CN103247524A publication Critical patent/CN103247524A/zh
Priority to US14/086,151 priority patent/US20140322879A1/en
Application granted granted Critical
Publication of CN103247524B publication Critical patent/CN103247524B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

本发明提供一种∑形凹槽的制作方法，包括；提供半导体衬底，所述半导体衬底上形成有栅极，所述栅极和半导体衬底表面形成有保护层；利用等离子体刻蚀工艺和湿法刻蚀工艺，对所述保护层和半导体衬底进行刻蚀，在所述半导体衬底内形成∑形凹槽。于本发明利用等离子体特性，分别选择水平方向刻蚀和聚合物重的刻蚀气体，能够形成∑型凹槽结构。在此基础上再利用湿法刻蚀工艺沿晶向不同速率的特性形成∑形凹槽结构；并且该凹槽结构能够更靠近沟道，侧向距离L和垂直深度D可单独控制，即∑形凹槽的形貌可调，并能增加工艺窗口。

Description

∑形凹槽的制作方法
技术领域
本发明涉及半导体技术领域，尤其涉及∑形凹槽的制作方法
背景技术
随着半导体制造技术的进步，半导体器件的特征尺寸不断缩小，当半导体器件的特征尺寸缩小至40纳米及以下时，需要使用嵌入式锗硅外延(使用embeddedepitaxialSiGe)技术来增强PMOS晶体管的驱动电流。而在锗硅外延生长之前需要形成在半导体衬底上形成凹槽。凹槽的形状有U形和∑形两种，∑形凹槽因为形状更接近沟道，增强驱动电流的效果更佳。
现有的∑形凹槽的制作方法请参考图1-图3所示。首先，提供半导体衬底10，所述半导体衬底10上形成有栅极20。在所述栅极20上形成保护层30，所述保护层30的材质为氮化硅层，用于保护栅极20。然后，请参考图2，进行等离子体刻蚀工艺，在所述半导体衬底10中形成凹槽40，所述凹槽的侧壁垂直于沟槽的底部或与沟槽底部倾斜。接着，请参考图3，进行湿法刻蚀工艺，形成∑形凹槽。
由于∑形凹槽的侧壁方向是在湿法刻蚀工艺中形成，该∑形凹槽的侧向距离L会受到∑形凹槽的垂直深度D限制，当垂直深度D一定时，基本上无法实现增大侧向距离L的尺寸，这使得现有的∑形凹槽的工艺窗口较小，影响了对器件的驱动电流的增强效果。
发明内容
本发明解决的问题是提供了一种∑形凹槽的制作方法，能够使得∑形凹槽能够更加靠近沟道，∑形凹槽的侧向距离和垂直深度可单独控制，实现∑形凹槽的形貌可调，增大了工艺窗口。
为解决上述问题，本发明提供一种∑形凹槽的制作方法，包括：
提供半导体衬底，所述半导体衬底上形成有栅极，所述栅极和半导体衬底表面形成有保护层；
利用等离子体刻蚀工艺和湿法刻蚀工艺，对所述保护层和半导体衬底进行刻蚀，在所述半导体衬底内形成∑形凹槽。
可选地，所述等离子体刻蚀工艺包括：
利用含第一刻蚀气体进行等离子体刻蚀工艺，所述第一刻蚀气体包括含碳的氟化物；利用第二刻蚀气体进行等离子体刻蚀工艺，所述第二刻蚀气体为含氮的氟化物；利用第三刻蚀气体进行等离子体刻蚀工艺，所述第三刻蚀气体包括溴化氢和O2的混合气体。
可选地，所述第一刻蚀气体包括CF4，CF4的流量范围为50-100sccm。
可选地，所述第二刻蚀气体包括NF3，刻蚀腔室的压力范围为60-100mTorr，偏置功率为0W。
可选地，第三刻蚀气体包括HBr和O2形成聚合物气体，所述HBr的流量范围为200-300sccm，O2的流量范围是5-10sccm。
可选地，依次利用所述第一刻蚀气体、第二刻蚀气体和第三刻蚀气体进行所述等离子体刻蚀工艺。
可选地，所述等离子体刻蚀工艺利用LAMkiyo或kiyo45设备进行。
可选地，所述等离子体刻蚀工艺在半导体衬底内形成开口，所述开口的宽度自沿半导体衬底上表面至下表面方向逐渐增大后逐渐减小。
可选地，所述湿法刻蚀工艺包括：采用酸性溶液进行清洗，所述酸性溶液为含有氢氟酸的溶液；
采用含有四甲基氢氧化铵的溶液进行刻蚀。
可选地，所述含有四甲基氢氧化铵溶液中的四甲基氢氧化铵的浓度为5-20％，所述湿法刻蚀工艺温度范围为50-60摄氏度。
可选地，所述保护层的材质为氮化硅，其厚度范围为100-150埃。
可选地，所述∑形凹槽的垂直深度范围为100-200埃，侧墙距离为30-75埃。
与现有技术相比，本发明具有以下优点：
本发明依次采用等离子体刻蚀和湿法刻蚀工艺对半导体衬底进行刻蚀，形成的∑形凹槽的更加接近沟槽，对PMOS晶体管驱动电流的增强效果更佳，并且∑形凹槽的侧向距离可以通过湿法刻蚀工艺进行调节控制，也能通过等离子体刻蚀工艺进行调节控制，所述∑形凹槽的侧墙距离和垂直深度可分别调节，使得侧向距离的调节不依赖于垂直深度，增大了工艺窗口，更好的调整∑形凹槽的形貌；由于本发明采用的等离子体刻蚀工艺在半导体衬底内形成开口，所述开口的宽度自沿半导体衬底上表面至下表面方向逐渐增大后逐渐减小，这样使得最终形成的∑形凹槽的深度和侧向距离更加单独可控制，使得∑形凹槽的深度和侧向距离不受晶向的控制，工艺更加灵活。
附图说明
图1-图3是现有技术的∑形凹槽的制作方法剖面结构示意图；
图4是本发明的∑形凹槽的制作方法流程示意图；
图5-图6是本发明一个实施例的∑形凹槽的制作方法剖面结构示意图。
具体实施方式
本发明提供一种∑形凹槽的制作方法，请参考图4，图4为本发明的∑形凹槽的制作方法流程示意图，所述制作方法包括：
步骤S1，提供半导体衬底，所述半导体衬底上形成有栅极，所述栅极和半导体衬底表面形成有保护层；
步骤S2，利用等离子体刻蚀工艺和湿法刻蚀工艺，对所述保护层和半导体衬底进行刻蚀，在所述半导体衬底内形成∑形凹槽。
下面结合具体实施例对本发明的技术方案进行详细的说明。为了更好说明本发明的技术方案，请参考图5-图6所示的本发明一个实施例的∑形凹槽的制作方法的剖面结构示意图。
请参考图5，提供半导体衬底100，所述半导体衬底100上形成有栅极200。在所述栅极200上形成保护层300，所述保护层300的材质为氮化硅，用于保护栅极200。所述保护层300的厚度范围为100-150埃。
然后，请参考图6，依次进行等离子体刻蚀工艺和湿法刻蚀工艺，在半导体衬底100内形成∑形凹槽500。作为一个实施例，所述等离子体刻蚀工艺包括：
利用含第一刻蚀气体进行等离子体刻蚀工艺，所述第一刻蚀气体包括含碳的氟化物，目的是对要形成∑形凹槽500位置的氮化硅进行刻蚀，将氮化硅去除；利用第二刻蚀气体进行等离子体刻蚀工艺，所述第二刻蚀气体为含氮的氟化物；利用第三刻蚀气体进行等离子体刻蚀工艺，所述第三刻蚀气体包括溴化氢和O2的混合气体，该步骤的聚合物重。
本实施例中，所述第一刻蚀气体包括CF4，CF4的流量范围为50-100sccm；所述第二刻蚀气体包括NF3，刻蚀腔室的压力范围为60-100mTorr，偏置功率为0W；第三刻蚀气体包括HBr和O2形成聚合物气体，所述HBr的流量范围为200-300sccm，O2的流量范围是5-10sccm。
作为本发明的一个实施例，依次利用所述第一刻蚀气体、第二刻蚀气体和第三刻蚀气体进行所述等离子体刻蚀工艺。所述等离子体刻蚀工艺利用LAMkiyo或kiyo45设备进行。
所述等离子体刻蚀工艺的目的是在半导体衬底100内形成开口，所述开口的宽度自沿半导体衬底100的上表面至下表面方向逐渐增大后逐渐减小，这样使得最终形成的∑形凹槽500的深度和侧向距离更加单独可控制，使得∑形凹槽500的深度和侧向距离不受晶向的控制，工艺更加灵活。
所述湿法刻蚀工艺包括：
首先采用酸性溶液进行清洗，所述酸性溶液为含有氢氟酸的溶液，目的是清除等离子体刻蚀工艺后半导体衬底表面的聚合物以及氧化物残留；
然后采用含有四甲基氢氧化铵的溶液进行刻蚀，其中所述含有四甲基氢氧化铵溶液中的四甲基氢氧化铵的浓度为5-20％，所述湿法刻蚀工艺温度范围为50-60摄氏度。
由于本发明利用等离子体特性，分别选择水平方向刻蚀和聚合物重的刻蚀气体，能够形成∑型凹槽结构。在此基础上再利用湿法刻蚀工艺沿晶向不同速率的特性形成∑形凹槽结构；并且该凹槽结构能够更靠近沟道，侧向距离L和垂直深度D可单独控制，即∑形凹槽500的形貌可调，并能增加工艺窗口。作为一个实施例，所述∑形凹槽500的垂直深度范围为100-200埃，侧墙距离为30-75埃。
综上，本发明依次采用等离子体刻蚀和湿法刻蚀工艺对半导体衬底进行刻蚀，形成的∑形凹槽的更加接近沟槽，对PMOS晶体管驱动电流的增强效果更佳，并且∑形凹槽的侧向距离可以通过湿法刻蚀工艺进行调节控制，也能通过等离子体刻蚀工艺进行调节控制，所述∑形凹槽的侧墙距离和垂直深度可分别调节，使得侧向距离的调节不依赖于垂直深度，增大了工艺窗口，更好的调整∑形凹槽的形貌。由于本发明采用的等离子体刻蚀工艺在半导体衬底内形成开口，所述开口的宽度自沿半导体衬底上表面至下表面方向逐渐增大后逐渐减小，这样使得最终形成的∑形凹槽的深度和侧向距离更加单独可控制，使得∑形凹槽的深度和侧向距离不受晶向的控制，工艺更加灵活。
因此，上述较佳实施例仅为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (11)

1.一种∑形凹槽的制作方法，在其特征在于，包括：
提供半导体衬底，所述半导体衬底上形成有栅极，所述栅极和半导体衬底表面形成有保护层；
利用等离子体刻蚀工艺和湿法刻蚀工艺，对所述保护层和半导体衬底进行刻蚀，在所述半导体衬底内形成∑形凹槽；
所述等离子体刻蚀工艺包括：利用含第一刻蚀气体进行等离子体刻蚀工艺，并将氮化硅保护层完全去除，所述第一刻蚀气体包括含碳的氟化物；利用第二刻蚀气体进行等离子体刻蚀工艺，所述第二刻蚀气体为含氮的氟化物；利用第三刻蚀气体进行等离子体刻蚀工艺，所述第三刻蚀气体包括溴化氢和O2的混合气体。
2.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述第一刻蚀气体包括CF4，CF4的流量范围为50-100sccm。
3.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述第二刻蚀气体包括NF3，刻蚀腔室的压力范围为60-100mTorr，偏置功率为0W。
4.如权利要求1所述的∑形凹槽的制作方法，其特征在于，第三刻蚀气体包括HBr和O2形成聚合物气体，所述HBr的流量范围为200-300sccm，O2的流量范围是5-10sccm。
5.如权利要求1所述的∑形凹槽的制作方法，其特征在于，依次利用所述第一刻蚀气体、第二刻蚀气体和第三刻蚀气体进行所述等离子体刻蚀工艺。
6.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述等离子体刻蚀工艺利用LAMkiyo或kiyo45设备进行。
7.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述等离子体刻蚀工艺在半导体衬底内形成开口，所述开口的宽度自沿半导体衬底上表面至下表面方向逐渐增大后逐渐减小。
8.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述湿法刻蚀工艺包括：采用酸性溶液进行清洗，所述酸性溶液为含有氢氟酸的溶液；
采用含有四甲基氢氧化铵的溶液进行刻蚀。
9.如权利要求8所述的∑形凹槽的制作方法，其特征在于，所述含有四甲基氢氧化铵溶液中的四甲基氢氧化铵的浓度为5-20％，所述湿法刻蚀工艺温度范围为50-60摄氏度。
10.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述保护层的材质为氮化硅，其厚度范围为100-150埃。
11.如权利要求1所述的∑形凹槽的制作方法，其特征在于，所述∑形凹槽的垂直深度范围为100-200埃，侧墙距离为30-75埃。
CN201310156183.1A 2013-04-28 2013-04-28 ∑形凹槽的制作方法 Active CN103247524B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201310156183.1A CN103247524B (zh) 2013-04-28 2013-04-28 ∑形凹槽的制作方法
US14/086,151 US20140322879A1 (en) 2013-04-28 2013-11-21 Method of forming sigma-shaped trench

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310156183.1A CN103247524B (zh) 2013-04-28 2013-04-28 ∑形凹槽的制作方法

Publications (2)

Publication Number Publication Date
CN103247524A CN103247524A (zh) 2013-08-14
CN103247524B true CN103247524B (zh) 2016-03-30

Family

ID=48926953

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310156183.1A Active CN103247524B (zh) 2013-04-28 2013-04-28 ∑形凹槽的制作方法

Country Status (2)

Country Link
US (1) US20140322879A1 (zh)
CN (1) CN103247524B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721827B2 (en) * 2014-02-27 2017-08-01 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with stress control and method of making
CN105529265A (zh) * 2014-09-30 2016-04-27 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法及mos晶体管
CN105990342B (zh) * 2015-02-13 2019-07-19 上海华力微电子有限公司 具有用于嵌入锗材料的成形腔的半导体器件及其制造工艺
CN104851884A (zh) * 2015-04-14 2015-08-19 上海华力微电子有限公司 用于锗硅填充材料的成形腔
US10400167B2 (en) * 2015-11-25 2019-09-03 Versum Materials Us, Llc Etching compositions and methods for using same
CN107910259B (zh) * 2017-11-08 2021-03-12 上海华力微电子有限公司 一种制备西格玛凹槽的方法
US10957761B2 (en) 2019-03-26 2021-03-23 International Business Machines Corporation Electrical isolation for nanosheet transistor devices
US11348999B2 (en) 2020-03-13 2022-05-31 International Business Machines Corporation Nanosheet semiconductor devices with sigma shaped inner spacer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740373A (zh) * 2008-11-14 2010-06-16 中芯国际集成电路制造(北京)有限公司 浅沟槽形成方法
CN102290374A (zh) * 2010-06-16 2011-12-21 台湾积体电路制造股份有限公司 制造集成电路装置的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3984689B2 (ja) * 1996-11-11 2007-10-03 キヤノン株式会社 インクジェットヘッドの製造方法
US6544838B2 (en) * 2001-03-13 2003-04-08 Infineon Technologies Ag Method of deep trench formation with improved profile control and surface area
US20090032880A1 (en) * 2007-08-03 2009-02-05 Applied Materials, Inc. Method and apparatus for tunable isotropic recess etching of silicon materials
KR101852342B1 (ko) * 2011-03-23 2018-04-27 삼성전자주식회사 반도체 소자 및 그의 제조방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740373A (zh) * 2008-11-14 2010-06-16 中芯国际集成电路制造(北京)有限公司 浅沟槽形成方法
CN102290374A (zh) * 2010-06-16 2011-12-21 台湾积体电路制造股份有限公司 制造集成电路装置的方法

Also Published As

Publication number Publication date
CN103247524A (zh) 2013-08-14
US20140322879A1 (en) 2014-10-30

Similar Documents

Publication Publication Date Title
CN103247524B (zh) ∑形凹槽的制作方法
US7303999B1 (en) Multi-step method for etching strain gate recesses
KR100853485B1 (ko) 리세스 게이트를 갖는 반도체 소자의 제조 방법
US9502244B2 (en) Manufacturing method for forming semiconductor structure
US20140306286A1 (en) Tapered fin field effect transistor
CN103280407B (zh) ∑形凹槽的制作方法
CN103794490A (zh) 自对准双图形的形成方法
CN102969232A (zh) 后栅工艺中假栅的制造方法
CN105374680A (zh) 半导体结构的形成方法
CN103594342B (zh) 形成鳍部的方法和形成鳍式场效应晶体管的方法
CN105244263A (zh) 一种提高SiGe源/漏区质量的制造方法
CN105336616A (zh) 半导体结构的形成方法
CN104752352A (zh) 半导体器件及其制作方法
CN102709167A (zh) 侧墙结构的制作方法
CN105632926B (zh) 鳍式场效应晶体管的形成方法
US20170133460A1 (en) Semiconductor structure and manufacturing method thereof
CN103377938B (zh) 半导体器件的形成方法
CN104979204A (zh) 鳍式场效应晶体管的形成方法
CN103928339A (zh) SiGe PMOS半导体器件的制作方法
CN103187285B (zh) 半导体结构及其形成方法
CN105655398A (zh) 半导体结构及其形成方法
TWI515775B (zh) 半導體結構之製作方法
CN109585358B (zh) 一种形成浅沟槽隔离的方法
US20210305054A1 (en) Semiconductor structure etching solution and method for fabricating a semiconductor structure using the same etching solution
CN103377904A (zh) 一种多晶硅沟槽回刻蚀方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant