JP2012504327A - チャネル領域への減少させられたオフセットを有する埋め込みSi/Ge材質を伴うトランジスタ - Google Patents
チャネル領域への減少させられたオフセットを有する埋め込みSi/Ge材質を伴うトランジスタ Download PDFInfo
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Abstract
非長方形形状を有していてよいキャビティに基いて歪誘起半導体合金を形成することができ、二酸化シリコン材質のような適切な保護層を設けることによって、非長方形形状は対応する高温処理の間にも維持され得る。その結果、歪誘起半導体材質の横方向のオフセットを小さくすることができる一方、キャビティエッチングプロセスの間に対応するオフセットスペーサの十分な厚みをもたらすことができるので、ゲート電極完全性を維持することができる。例えば、pチャネルトランジスタは六角形形状を伴うシリコン/ゲルマニウム合金を有することができ、それにより全体的な歪転移効率を顕著に高めることができる。
【選択図】図2g
Description
Claims (22)
- 半導体デバイスのトランジスタのゲート電極構造であってその側壁上に形成されるオフセットスペーサを備えているゲート電極構造に隣接するシリコン含有結晶性半導体領域内にキャビティを形成することと、
前記キャビティの露出させられた表面上に保護層を形成することと、
昇温された第1の温度でのプロセス環境内に前記半導体デバイスを導入することと、
前記プロセス環境がより低い第2の温度を有するように調節することと、
前記プロセス環境内で前記保護層を除去することと、
前記第2の温度にある前記プロセス環境内で前記キャビティ内に半導体合金を形成することとを備えた方法。 - 前記キャビティは前記オフセットスペーサの下に延びるアンダーエッチングされた領域を有するように形成される、請求項1の方法。
- 前記キャビティを形成することは、プラズマ環境に基いて第1のエッチングプロセスを実行することと、ウエットエッチング薬品に基いて第2のエッチングプロセスを実行することとを備えている、請求項2の方法。
- 前記ウエットエッチング薬品は結晶学的に異方性の除去速度を有している、請求項3の方法。
- 前記ウエットエッチング薬品はテトラメチルアンモニウムヒドロキシド(TMAH)を備えている、請求項4の方法。
- 前記保護層を形成することは前記キャビティの前記露出させられた表面上に酸化物層を形成することを備えている、請求項1の方法。
- 前記酸化物層は概ね750℃未満の温度の酸化性ガス雰囲気内で形成される、請求項6の方法。
- 前記酸化物層はウエット化学的酸化プロセスを実行することによって形成される、請求項6の方法。
- 前記半導体合金内に少なくとも部分的にドレイン及びソース領域を形成することを更に備えた、請求項1の方法。
- 前記半導体合金は前記トランジスタのチャネル領域内に圧縮歪を誘起するように形成される、請求項1の方法。
- 前記半導体合金はシリコン及びゲルマニウムから構成される、請求項10の方法。
- 前記昇温された第1の温度は概ね800℃以上である、請求項1の方法。
- プラズマ環境に基く第1のエッチングプロセス及びウエットエッチング薬品に基く第2のエッチングプロセスを実行することによってトランジスタのゲート電極構造に対して横方向にオフセットされるキャビティを結晶性半導体領域内に形成することと、
前記キャビティ内に歪誘起半導体合金を形成することと、
前記半導体領域内にドレイン及びソース領域を形成することとを備えた方法。 - 前記歪誘起半導体合金を形成するために用いられるプロセス環境内に前記トランジスタを導入するのに先立ち前記キャビティの露出させられた表面上に保護層を形成することを更に備えた、請求項13の方法。
- 前記保護層を除去するのに先立ち前記プロセス環境内の堆積温度を確立することを更に備えた、請求項14の方法。
- 前記堆積温度は概ね750℃以下である、請求項15の方法。
- 前記保護層は二酸化シリコン材質として形成される、請求項14の方法。
- 前記第2のエッチングプロセスの前記ウエットエッチング薬品は結晶学的に異方性のエッチング挙動を有している、請求項13の方法。
- 前記半導体合金はゲルマニウム及び錫の少なくとも一方を備えている、請求項13の方法。
- 基板の上方に形成されるトランジスタを備えた半導体デバイスであって、
前記トランジスタは、
結晶性半導体領域の上方に形成されるゲート電極構造と、
ドレイン側及びソース側で前記結晶性半導体領域内に形成される歪誘起半導体合金と、
前記結晶性半導体領域内に及び少なくとも部分的に前記半導体合金内に形成されるドレイン及びソース領域とを備えており、
前記歪誘起半導体合金は前記ドレイン側及びソース側の各々に前記結晶性半導体領域との第1の傾斜界面及び第2の傾斜界面を形成し、前記第1及び第2の傾斜界面はエッジで合流する半導体デバイス。 - 前記歪誘起半導体合金は前記トランジスタのチャネル領域内に圧縮歪を誘起する、請求項20の半導体デバイス。
- 前記トランジスタのゲート長は概ね50ナノメートル以下である、請求項20の半導体デバイス。
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DE102008049733A DE102008049733B3 (de) | 2008-09-30 | 2008-09-30 | Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand zum Kanalgebiet und Verfahren zur Herstellung des Transistors |
US12/552,642 US8071442B2 (en) | 2008-09-30 | 2009-09-02 | Transistor with embedded Si/Ge material having reduced offset to the channel region |
US12/552,642 | 2009-09-02 | ||
PCT/EP2009/007002 WO2010037523A1 (en) | 2008-09-30 | 2009-09-29 | A transistor with embedded si/ge material having reduced offset to the channel region |
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Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5355692B2 (ja) * | 2009-07-08 | 2013-11-27 | 株式会社東芝 | 半導体装置及びその製造方法 |
US8299564B1 (en) * | 2009-09-14 | 2012-10-30 | Xilinx, Inc. | Diffusion regions having different depths |
US8405160B2 (en) * | 2010-05-26 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-strained source/drain structures |
DE102010029532B4 (de) * | 2010-05-31 | 2012-01-26 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Transistor mit eingebettetem verformungsinduzierenden Material, das in diamantförmigen Aussparungen auf der Grundlage einer Voramorphisierung hergestellt ist |
US8492234B2 (en) | 2010-06-29 | 2013-07-23 | International Business Machines Corporation | Field effect transistor device |
DE102010063292B4 (de) | 2010-12-16 | 2016-08-04 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung gering diffundierter Drain- und Sourcegebiete in CMOS-Transistoren für Anwendungen mit hoher Leistungsfähigkeit und geringer Leistung |
KR20120073727A (ko) * | 2010-12-27 | 2012-07-05 | 삼성전자주식회사 | 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템 |
DE102010064284B4 (de) * | 2010-12-28 | 2016-03-31 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Herstellung eines Transistors mit einer eingebetteten Sigma-förmigen Halbleiterlegierung mit erhöhter Gleichmäßigkeit |
US8946064B2 (en) * | 2011-06-16 | 2015-02-03 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
US8476169B2 (en) | 2011-10-17 | 2013-07-02 | United Microelectronics Corp. | Method of making strained silicon channel semiconductor structure |
US8524563B2 (en) | 2012-01-06 | 2013-09-03 | GlobalFoundries, Inc. | Semiconductor device with strain-inducing regions and method thereof |
US8866230B2 (en) * | 2012-04-26 | 2014-10-21 | United Microelectronics Corp. | Semiconductor devices |
US8674447B2 (en) | 2012-04-27 | 2014-03-18 | International Business Machines Corporation | Transistor with improved sigma-shaped embedded stressor and method of formation |
KR101986534B1 (ko) | 2012-06-04 | 2019-06-07 | 삼성전자주식회사 | 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법 |
KR101909204B1 (ko) | 2012-06-25 | 2018-10-17 | 삼성전자 주식회사 | 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법 |
CN103594370B (zh) * | 2012-08-16 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
US8541281B1 (en) | 2012-08-17 | 2013-09-24 | Globalfoundries Inc. | Replacement gate process flow for highly scaled semiconductor devices |
US8969190B2 (en) | 2012-08-24 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a layer of silicon on a layer of silicon/germanium |
KR20140039544A (ko) | 2012-09-24 | 2014-04-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9029919B2 (en) | 2013-02-01 | 2015-05-12 | Globalfoundries Inc. | Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer |
US9040394B2 (en) | 2013-03-12 | 2015-05-26 | Samsung Electronics Co., Ltd. | Method for fabricating a semiconductor device |
DE102013105705B4 (de) * | 2013-03-13 | 2020-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung und dessen Herstellung |
US8951877B2 (en) * | 2013-03-13 | 2015-02-10 | Globalfoundries Inc. | Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment |
US20150048422A1 (en) * | 2013-08-16 | 2015-02-19 | International Business Machines Corporation | A method for forming a crystalline compound iii-v material on a single element substrate |
US9054217B2 (en) | 2013-09-17 | 2015-06-09 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device having an embedded source/drain |
CN104517901B (zh) * | 2013-09-29 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的形成方法 |
US9691898B2 (en) * | 2013-12-19 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Germanium profile for channel strain |
US9831341B2 (en) * | 2014-06-16 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for integrated circuit |
US10084063B2 (en) | 2014-06-23 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
US10026837B2 (en) * | 2015-09-03 | 2018-07-17 | Texas Instruments Incorporated | Embedded SiGe process for multi-threshold PMOS transistors |
US20170141228A1 (en) * | 2015-11-16 | 2017-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor and manufacturing method thereof |
US10141426B2 (en) * | 2016-02-08 | 2018-11-27 | International Business Macahines Corporation | Vertical transistor device |
CN113611736B (zh) * | 2020-05-29 | 2022-11-22 | 联芯集成电路制造(厦门)有限公司 | 半导体元件及其制作方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0964016A (ja) * | 1995-08-28 | 1997-03-07 | Nec Corp | 半導体装置の製造方法 |
JP2002124474A (ja) * | 2000-10-13 | 2002-04-26 | Denso Corp | 半導体基板の製造方法および半導体基板 |
US20050148147A1 (en) * | 2003-12-30 | 2005-07-07 | Steven Keating | Amorphous etch stop for the anisotropic etching of substrates |
JP2006108243A (ja) * | 2004-10-01 | 2006-04-20 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2006186240A (ja) * | 2004-12-28 | 2006-07-13 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2006196910A (ja) * | 2005-01-14 | 2006-07-27 | Samsung Electronics Co Ltd | 半導体基板のインサイチュ洗浄方法及びこれを採用する半導体素子の製造方法 |
WO2007049510A1 (ja) * | 2005-10-27 | 2007-05-03 | Tokyo Electron Limited | 処理方法及び記録媒体 |
JP2007250837A (ja) * | 2006-03-16 | 2007-09-27 | Sony Corp | 半導体装置の製造方法 |
JP2007305730A (ja) * | 2006-05-10 | 2007-11-22 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
US20080003783A1 (en) * | 2006-06-30 | 2008-01-03 | Andy Wei | Method of reducing a roughness of a semiconductor surface |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0135147B1 (ko) * | 1994-07-21 | 1998-04-22 | 문정환 | 트랜지스터 제조방법 |
US6071783A (en) * | 1998-08-13 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Pseudo silicon on insulator MOSFET device |
US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
CN1303672C (zh) * | 2003-11-11 | 2007-03-07 | 旺宏电子股份有限公司 | 氮化物只读存储器的制造方法 |
US20060115949A1 (en) | 2004-12-01 | 2006-06-01 | Freescale Semiconductor, Inc. | Semiconductor fabrication process including source/drain recessing and filling |
US7078285B1 (en) | 2005-01-21 | 2006-07-18 | Sony Corporation | SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material |
JP5055771B2 (ja) | 2005-02-28 | 2012-10-24 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
US7544576B2 (en) * | 2005-07-29 | 2009-06-09 | Freescale Semiconductor, Inc. | Diffusion barrier for nickel silicides in a semiconductor fabrication process |
US7422950B2 (en) | 2005-12-14 | 2008-09-09 | Intel Corporation | Strained silicon MOS device with box layer between the source and drain regions |
US7525160B2 (en) * | 2005-12-27 | 2009-04-28 | Intel Corporation | Multigate device with recessed strain regions |
JP4410195B2 (ja) * | 2006-01-06 | 2010-02-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7528072B2 (en) | 2006-04-20 | 2009-05-05 | Texas Instruments Incorporated | Crystallographic preferential etch to define a recessed-region for epitaxial growth |
US20080220579A1 (en) * | 2007-03-07 | 2008-09-11 | Advanced Micro Devices, Inc. | Stress enhanced mos transistor and methods for its fabrication |
US7691752B2 (en) | 2007-03-30 | 2010-04-06 | Intel Corporation | Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby |
DE102007063229B4 (de) * | 2007-12-31 | 2013-01-24 | Advanced Micro Devices, Inc. | Verfahren und Teststruktur zur Überwachung von Prozesseigenschaften für die Herstellung eingebetteter Halbleiterlegierungen in Drain/Source-Gebieten |
KR100971414B1 (ko) * | 2008-04-18 | 2010-07-21 | 주식회사 하이닉스반도체 | 스트레인드 채널을 갖는 반도체 소자 및 그 제조방법 |
US7838372B2 (en) * | 2008-05-22 | 2010-11-23 | Infineon Technologies Ag | Methods of manufacturing semiconductor devices and structures thereof |
-
2008
- 2008-09-30 DE DE102008049733A patent/DE102008049733B3/de active Active
-
2009
- 2009-09-02 US US12/552,642 patent/US8071442B2/en active Active
- 2009-09-29 CN CN200980147114.6A patent/CN102282668B/zh active Active
- 2009-09-29 KR KR1020117009991A patent/KR101608908B1/ko active IP Right Grant
- 2009-09-29 WO PCT/EP2009/007002 patent/WO2010037523A1/en active Application Filing
- 2009-09-29 JP JP2011528256A patent/JP5795735B2/ja active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0964016A (ja) * | 1995-08-28 | 1997-03-07 | Nec Corp | 半導体装置の製造方法 |
JP2002124474A (ja) * | 2000-10-13 | 2002-04-26 | Denso Corp | 半導体基板の製造方法および半導体基板 |
US20050148147A1 (en) * | 2003-12-30 | 2005-07-07 | Steven Keating | Amorphous etch stop for the anisotropic etching of substrates |
JP2006108243A (ja) * | 2004-10-01 | 2006-04-20 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2006186240A (ja) * | 2004-12-28 | 2006-07-13 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2006196910A (ja) * | 2005-01-14 | 2006-07-27 | Samsung Electronics Co Ltd | 半導体基板のインサイチュ洗浄方法及びこれを採用する半導体素子の製造方法 |
WO2007049510A1 (ja) * | 2005-10-27 | 2007-05-03 | Tokyo Electron Limited | 処理方法及び記録媒体 |
JP2007250837A (ja) * | 2006-03-16 | 2007-09-27 | Sony Corp | 半導体装置の製造方法 |
JP2007305730A (ja) * | 2006-05-10 | 2007-11-22 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
US20080003783A1 (en) * | 2006-06-30 | 2008-01-03 | Andy Wei | Method of reducing a roughness of a semiconductor surface |
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CN102282668B (zh) | 2014-09-24 |
JP5795735B2 (ja) | 2015-10-14 |
DE102008049733B3 (de) | 2010-06-17 |
WO2010037523A1 (en) | 2010-04-08 |
US8071442B2 (en) | 2011-12-06 |
CN102282668A (zh) | 2011-12-14 |
KR20110082028A (ko) | 2011-07-15 |
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US20100078689A1 (en) | 2010-04-01 |
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