JP5795260B2 - 段階的な形状の構造を有する埋め込み歪誘起材質を伴うトランジスタ - Google Patents
段階的な形状の構造を有する埋め込み歪誘起材質を伴うトランジスタ Download PDFInfo
- Publication number
- JP5795260B2 JP5795260B2 JP2011542724A JP2011542724A JP5795260B2 JP 5795260 B2 JP5795260 B2 JP 5795260B2 JP 2011542724 A JP2011542724 A JP 2011542724A JP 2011542724 A JP2011542724 A JP 2011542724A JP 5795260 B2 JP5795260 B2 JP 5795260B2
- Authority
- JP
- Japan
- Prior art keywords
- spacer
- recesses
- forming
- transistor
- strain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000463 material Substances 0.000 title claims description 57
- 230000001939 inductive effect Effects 0.000 title claims description 35
- 125000006850 spacer group Chemical group 0.000 claims description 135
- 238000000034 method Methods 0.000 claims description 128
- 239000004065 semiconductor Substances 0.000 claims description 127
- 230000008569 process Effects 0.000 claims description 99
- 229910045601 alloy Inorganic materials 0.000 claims description 41
- 239000000956 alloy Substances 0.000 claims description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 238000011065 in-situ storage Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 76
- 238000005530 etching Methods 0.000 description 64
- 238000004519 manufacturing process Methods 0.000 description 47
- 239000010703 silicon Substances 0.000 description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 27
- 239000002019 doping agent Substances 0.000 description 21
- 230000001965 increasing effect Effects 0.000 description 16
- 229910000676 Si alloy Inorganic materials 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 14
- 229910000927 Ge alloy Inorganic materials 0.000 description 13
- 239000007772 electrode material Substances 0.000 description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 12
- 230000008021 deposition Effects 0.000 description 11
- 229910052732 germanium Inorganic materials 0.000 description 11
- 238000002513 implantation Methods 0.000 description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910001339 C alloy Inorganic materials 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000006259 organic additive Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (9)
- 第1のゲート電極構造の側壁上に形成された第1の側壁スペーサによって前記第1のゲート電極構造からオフセットされ、第1の深さまで延びる第1の複数の凹部を第1の結晶性半導体領域内に形成することであって、前記第1のゲート電極構造の上方および第2の結晶性半導体領域上に形成された第2のゲート電極構造の上方に第1のスペーサ層を形成し、前記第2のゲート電極構造及び前記第2の結晶性半導体領域の上方に形成された前記第1のスペーサ層を覆うために第1のマスクを形成し、前記第1のスペーサ層から前記第1の側壁スペーサを形成し、前記第1の側壁スペーサ及び前記第1のマスクの存在下で前記第1の結晶性半導体領域から材質を除去することを含む、ことと、
前記第1の側壁スペーサ上に形成された第2の側壁スペーサによって前記第1のゲート電極構造からオフセットされ、前記第1の深さよりも深い第2の深さまで延びる第2の複数の凹部を第1の結晶性半導体領域内に形成することであって、前記第1のマスクを除去し、第2のスペーサ層を堆積させ、前記第2のゲート電極構造の上方及び前記第2の結晶性半導体領域の上方に第2のマスクを形成し、前記第2のマスクの存在下で前記第2のスペーサ層から前記第2の側壁スペーサを形成することを含む、ことと、
を備えた方法。 - 選択的なエピタキシャル成長処理を実行することによって、前記第1の凹部及び前記第2の凹部に歪誘起半導体合金を形成することを含む請求項1の方法。
- 前記歪誘起半導体合金を形成することは、前記第1の側壁スペーサの存在下で前記第1の複数の凹部を前記歪誘起半導体合金の第1の部分で充填し、且つ、前記第1の側壁スペーサ及び前記第2の側壁スペーサの存在下で前記第2の複数の凹部の一部を前記歪誘起半導体合金の第2の部分で充填するように、第1のエピタキシャル成長プロセスを実行することを含む、請求項2の方法。
- 前記歪誘起半導体合金の前記第1の部分と前記第2の部分とは、少なくともインサイツドーピングの程度が異なる、請求項3の方法。
- 前記歪誘起半導体合金は錫を含む、請求項2の方法。
- 前記第1の複数の凹部及び前記第2の複数の凹部を形成することは、前記第2の複数の凹部の第1の部分を形成することと、前記第2の側壁スペーサの少なくとも一部を除去することと、前記第2の複数の凹部の第2の部分と前記第1の複数の凹部とを共通して形成することと、を含む、請求項1の方法。
- 前記第1の側壁スペーサは二酸化シリコンから構成されており、前記第2の側壁スペーサはシリコン窒化物から構成されている、請求項1の方法。
- 前記第1の深さ及び前記第2の深さよりも浅い第3の深さを有する第3の複数の凹部であって、前記第1の複数の凹部又は前記第2の複数の凹部のオフセットよりも小さなオフセットによって前記ゲート電極構造からオフセットされている第3の複数の凹部を形成することを備えた請求項1の方法。
- 前記第1の複数の凹部、前記第2の複数の凹部及び前記第3の複数の凹部を半導体合金で充填することを備えた請求項8の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008063427.1 | 2008-12-31 | ||
DE102008063427A DE102008063427B4 (de) | 2008-12-31 | 2008-12-31 | Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung |
US12/640,765 | 2009-12-17 | ||
US12/640,765 US8202777B2 (en) | 2008-12-31 | 2009-12-17 | Transistor with an embedded strain-inducing material having a gradually shaped configuration |
PCT/EP2009/009306 WO2010076017A1 (en) | 2008-12-31 | 2009-12-29 | A transistor with an embedded strain inducing material having a gradually shaped configuration |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012514317A JP2012514317A (ja) | 2012-06-21 |
JP2012514317A5 JP2012514317A5 (ja) | 2013-02-07 |
JP5795260B2 true JP5795260B2 (ja) | 2015-10-14 |
Family
ID=42234622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011542724A Active JP5795260B2 (ja) | 2008-12-31 | 2009-12-29 | 段階的な形状の構造を有する埋め込み歪誘起材質を伴うトランジスタ |
Country Status (6)
Country | Link |
---|---|
US (2) | US8202777B2 (ja) |
JP (1) | JP5795260B2 (ja) |
KR (1) | KR101537079B1 (ja) |
CN (1) | CN102362344B (ja) |
DE (1) | DE102008063427B4 (ja) |
WO (1) | WO2010076017A1 (ja) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
DE102009046241B4 (de) * | 2009-10-30 | 2012-12-06 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verformungsverstärkung in Transistoren, die eine eingebettete verformungsinduzierende Halbleiterlegierung besitzen, durch Kantenverrundung an der Oberseite der Gateelektrode |
US8338259B2 (en) * | 2010-03-30 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with a buried stressor |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
DE102011004320B4 (de) * | 2011-02-17 | 2016-02-04 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Herstellung komplementärer Transistoren mit Metallgateelektrodenstrukturen mit großem ε und epitaktisch hergestellten Halbleitermaterialien in den Drain- und Sourcebereichen |
US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
US8592270B2 (en) * | 2011-05-25 | 2013-11-26 | International Business Machines Corporation | Non-relaxed embedded stressors with solid source extension regions in CMOS devices |
DE102011076695B4 (de) * | 2011-05-30 | 2013-05-08 | Globalfoundries Inc. | Transistoren mit eingebettetem verformungsinduzierenden Material, das in durch einen Oxidationsätzprozess erzeugten Aussparungen ausgebildet ist |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
US9076817B2 (en) | 2011-08-04 | 2015-07-07 | International Business Machines Corporation | Epitaxial extension CMOS transistor |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US20130214358A1 (en) * | 2012-02-17 | 2013-08-22 | International Business Machines Corporation | Low external resistance etsoi transistors |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
CN103545257A (zh) * | 2012-07-12 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的制作方法 |
US8541281B1 (en) | 2012-08-17 | 2013-09-24 | Globalfoundries Inc. | Replacement gate process flow for highly scaled semiconductor devices |
US8969190B2 (en) | 2012-08-24 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a layer of silicon on a layer of silicon/germanium |
US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
CN104854698A (zh) | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | 具有低变化晶体管外围电路的dram型器件以及相关方法 |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
CN103871879B (zh) * | 2012-12-07 | 2016-09-07 | 中芯国际集成电路制造(上海)有限公司 | 晶体管结构及其形成方法 |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9029919B2 (en) | 2013-02-01 | 2015-05-12 | Globalfoundries Inc. | Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
CN104064521B (zh) * | 2014-07-03 | 2017-02-15 | 上海华力微电子有限公司 | 半导体工艺方法以及半导体结构 |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
US9419138B2 (en) * | 2014-09-29 | 2016-08-16 | International Business Machines Corporation | Embedded carbon-doped germanium as stressor for germanium nFET devices |
CN104409351B (zh) * | 2014-11-25 | 2018-04-06 | 上海集成电路研发中心有限公司 | Pmos晶体管的形成方法 |
US9899514B2 (en) * | 2015-05-21 | 2018-02-20 | Globalfoundries Singapore Pte. Ltd. | Extended drain metal-oxide-semiconductor transistor |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196585A (ja) * | 1992-12-21 | 2001-07-19 | Sharp Corp | ゲート絶縁型電界効果トランジスタ及びその製造方法 |
US5863824A (en) * | 1997-12-18 | 1999-01-26 | Advanced Micro Devices | Method of forming semiconductor devices using gate electrode length and spacer width for controlling drivecurrent strength |
US6921982B2 (en) * | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
US7335959B2 (en) * | 2005-01-06 | 2008-02-26 | Intel Corporation | Device with stepped source/drain region profile |
US7429775B1 (en) * | 2005-03-31 | 2008-09-30 | Xilinx, Inc. | Method of fabricating strain-silicon CMOS |
US7226820B2 (en) * | 2005-04-07 | 2007-06-05 | Freescale Semiconductor, Inc. | Transistor fabrication using double etch/refill process |
US7696537B2 (en) * | 2005-04-18 | 2010-04-13 | Toshiba America Electronic Components, Inc. | Step-embedded SiGe structure for PFET mobility enhancement |
JP4630728B2 (ja) * | 2005-05-26 | 2011-02-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7442618B2 (en) * | 2005-07-16 | 2008-10-28 | Chartered Semiconductor Manufacturing, Ltd | Method to engineer etch profiles in Si substrate for advanced semiconductor devices |
DE102005051994B4 (de) * | 2005-10-31 | 2011-12-01 | Globalfoundries Inc. | Verformungsverfahrenstechnik in Transistoren auf Siliziumbasis unter Anwendung eingebetteter Halbleiterschichten mit Atomen mit einem großen kovalenten Radius |
US7696019B2 (en) * | 2006-03-09 | 2010-04-13 | Infineon Technologies Ag | Semiconductor devices and methods of manufacturing thereof |
DE102006015075A1 (de) * | 2006-03-31 | 2007-10-11 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Bereitstellung von Verspannungsquellen in MOS-Transistoren in unmittelbarer Nähe zu einem Kanalgebiet |
JP2007281038A (ja) * | 2006-04-03 | 2007-10-25 | Toshiba Corp | 半導体装置 |
US8207523B2 (en) * | 2006-04-26 | 2012-06-26 | United Microelectronics Corp. | Metal oxide semiconductor field effect transistor with strained source/drain extension layer |
US7554110B2 (en) * | 2006-09-15 | 2009-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with partial stressor channel |
US7504301B2 (en) * | 2006-09-28 | 2009-03-17 | Advanced Micro Devices, Inc. | Stressed field effect transistor and methods for its fabrication |
US7534689B2 (en) * | 2006-11-21 | 2009-05-19 | Advanced Micro Devices, Inc. | Stress enhanced MOS transistor and methods for its fabrication |
US7750338B2 (en) * | 2006-12-05 | 2010-07-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual-SiGe epitaxy for MOS devices |
US7989901B2 (en) * | 2007-04-27 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with improved source/drain regions with SiGe |
JP5211647B2 (ja) * | 2007-11-01 | 2013-06-12 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US7875520B2 (en) * | 2008-03-27 | 2011-01-25 | United Microelectronics Corp. | Method of forming CMOS transistor |
-
2008
- 2008-12-31 DE DE102008063427A patent/DE102008063427B4/de active Active
-
2009
- 2009-12-17 US US12/640,765 patent/US8202777B2/en active Active
- 2009-12-29 WO PCT/EP2009/009306 patent/WO2010076017A1/en active Application Filing
- 2009-12-29 JP JP2011542724A patent/JP5795260B2/ja active Active
- 2009-12-29 KR KR1020117017916A patent/KR101537079B1/ko active IP Right Grant
- 2009-12-29 CN CN200980157544.6A patent/CN102362344B/zh active Active
-
2012
- 2012-05-14 US US13/470,441 patent/US8466520B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2010076017A1 (en) | 2010-07-08 |
US8466520B2 (en) | 2013-06-18 |
DE102008063427B4 (de) | 2013-02-28 |
US20100164020A1 (en) | 2010-07-01 |
DE102008063427A1 (de) | 2010-07-08 |
US8202777B2 (en) | 2012-06-19 |
KR20120030033A (ko) | 2012-03-27 |
KR101537079B1 (ko) | 2015-07-16 |
JP2012514317A (ja) | 2012-06-21 |
CN102362344B (zh) | 2014-03-19 |
CN102362344A (zh) | 2012-02-22 |
US20120223363A1 (en) | 2012-09-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5795260B2 (ja) | 段階的な形状の構造を有する埋め込み歪誘起材質を伴うトランジスタ | |
JP4937263B2 (ja) | Nmosトランジスタおよびpmosトランジスタに凹んだ歪みのあるドレイン/ソース領域を形成する技術 | |
JP5795735B2 (ja) | チャネル領域への減少させられたオフセットを有する埋め込みSi/Ge材質を伴うトランジスタ | |
JP4937253B2 (ja) | コンタクト絶縁層および異なる特性を有するシリサイド領域を形成するための技法 | |
JP5204645B2 (ja) | 強化した応力伝送効率でコンタクト絶縁層を形成する技術 | |
JP5571693B2 (ja) | 歪誘起合金及び段階的なドーパントプロファイルを含むその場で形成されるドレイン及びソース領域 | |
KR101148138B1 (ko) | 리세스된 드레인 및 소스 영역을 갖는 nmos 트랜지스터와 드레인 및 소스 영역에 실리콘/게르마늄 물질을 갖는 pmos 트랜지스터를 포함하는 cmos 디바이스 | |
US8772878B2 (en) | Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material | |
TWI387009B (zh) | 藉由偏斜式預非晶形化而減少受應變之電晶體中之晶體缺陷之技術 | |
KR101811796B1 (ko) | 급경사 접합 프로파일을 갖는 소스/드레인 영역들을 구비하는 반도체 소자 및 그 제조방법 | |
US8735237B2 (en) | Method for increasing penetration depth of drain and source implantation species for a given gate height | |
US7569437B2 (en) | Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern | |
JP2010532572A (ja) | トランジスタのゲート電極のプレアモルファス化のブロッキング | |
JP5614184B2 (ja) | 半導体装置の製造方法 | |
US20100163939A1 (en) | Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration | |
JP5798923B2 (ja) | 基板全域にわたって高められた均一性を有する埋め込みSi/Ge材質を伴うトランジスタ | |
US8999803B2 (en) | Methods for fabricating integrated circuits with the implantation of fluorine | |
US7951662B2 (en) | Method of fabricating strained silicon transistor | |
JP2008066548A (ja) | 半導体装置および半導体装置の製造方法 | |
TW201431007A (zh) | 半導體裝置結構及形成互補式金屬氧化物半導體積體電路結構之方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121212 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20121212 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140307 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140326 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140626 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140703 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140724 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150120 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150420 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150518 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150721 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150812 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5795260 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |