JP2010267996A - 小型電子機器、その形成方法、およびシステム - Google Patents
小型電子機器、その形成方法、およびシステム Download PDFInfo
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- JP2010267996A JP2010267996A JP2010172138A JP2010172138A JP2010267996A JP 2010267996 A JP2010267996 A JP 2010267996A JP 2010172138 A JP2010172138 A JP 2010172138A JP 2010172138 A JP2010172138 A JP 2010172138A JP 2010267996 A JP2010267996 A JP 2010267996A
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- layer
- diffusion barrier
- forming
- bump
- metal
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Abstract
【解決手段】ダイパッケージ220の相互接続構造は、半導体基板205と、半導体基板205と接する第1の導電層はベース層金属230とを含む。ベース層金属230はCuを含む。実施例では、相互接続構造は、第1の導電層と接する拡散バリア225と、拡散バリア225上のウェッティング層とを有する。ウェッティング層上には、バンプ層215が設置され、バンプ層215は、Snを含み電気メッキで設置されても良い。拡散バリア225は、無電解メッキ層であっても良く、CuおよびSnが拡散バリア225を通って拡散することを防止するように適合されている。さらに、拡散バリア225は、バンプ層215内でのウィスカーの形成を抑制するように適合されている。
【選択図】図2
Description
Claims (9)
- 導電性バンプ層を含む小型電子機器であって、
半導体基板と、
該半導体基板と接する第1の導電層であって、Cuを含むベース層金属を含む第1の導電層と、
該第1の導電層と接する拡散バリアであって、ホウ素およびリンを含む金属合金を有する拡散バリアと、
該拡散バリア上のウェッティング層であって、CoBおよびNiPの一つを有するウェッティング層と、
該ウェッティング層と接し、Snを含むバンプ層であって、前記拡散バリアは、CuおよびSnが前記拡散バリアを介して拡散することを抑制し、当該機器にCuSn金属間化合物が形成されることを抑制するように構成される、バンプ層と、
を有する機器。 - 前記拡散バリアは、無電解拡散バリアを有することを特徴とする請求項1に記載の機器。
- さらに、
ダイパッケージ、および
前記バンプ層とダイパッケージの間に設置されたハンダ層
を有し、
前記ハンダ層は、Snを含むことを特徴とする請求項1または2に記載の機器。 - 導電性バンプ層を含む小型電子機器であって、
半導体基板上の、Cuを含むベース層金属と、
該ベース層金属上の、Cuを含むバンプと、
該バンプ上の拡散バリアと、
該拡散バリア上の、CoBおよびNiPの一つを有するウェッティング層と、
該ウェッティング層と接し、Snを含むハンダ層と、
を有し、
前記ベース層金属は、さらに、前記拡散バリアと接し、前記バンプは、前記ハンダ層から物理的に分離され、
前記拡散バリアは、CuおよびSnが前記拡散バリアを介して拡散することを抑制し、当該機器にCuSn金属間化合物が形成されることを抑制するように構成されることを特徴とする機器。 - 小型電子機器を形成する方法であって、
SiNおよびポリイミドで、半導体基板をパッシベーションさせるステップと、
次に、Cuを含むベース層金属を成膜するステップと、
次に、フォトレジスト層を成膜するステップと、
次に、拡散バリアを形成するステップであって、前記拡散バリアは、異なる層間でのCuおよびSnの相互混合を抑制するように適合されるステップと、
次に、前記拡散バリアの上部に、CoBおよびNiPの一つを有するウェッティング層を形成するステップと、
次に、前記ウェッティング層と接するバンプ層を形成するステップと、
次に、前記フォトレジスト層を除去するステップと、
次に、前記ベース層金属をエッチングするステップと、
を有する方法。 - 小型電子機器を形成する方法であって、
SiNおよびポリイミドで、半導体基板をパッシベーションさせるステップと、
次に、ベース層金属を成膜するステップであって、前記ベース層金属は、接着層、シード層、および前記接着層と前記シード層の間に設置されたAlを含む金属層を有する、ステップと、
次に、フォトレジスト層を成膜するステップと、
次に、電気メッキによりCu層を形成するステップと、
次に、無電解拡散バリアを形成するステップであって、前記無電解拡散バリアは、
前記Cu層およびSn層の間に設置される、ステップと、
次に、前記無電解拡散バリア上に、CoBおよびNiPの一つを有するウェッティング層を形成するステップと、
次に、前記フォトレジスト層を除去するステップと、
次に、前記ベース層金属をエッチングするステップと、
を有する方法。 - 小型電子機器を形成する方法であって、
SiNおよびポリイミドで、半導体基板をパッシベーションさせるステップと、
次に、Cuを含むベース層金属を成膜するステップと、
次に、フォトレジスト層を成膜するステップと、
次に、Cuを含むバンプ層を電気メッキするステップと、
次に、前記フォトレジスト層を除去するステップと、
次に、前記ベース層金属をエッチングするステップと、
次に、拡散バリア層を形成するステップであって、前記拡散バリア層は、前記Cuバンプ層とSn層の間に、前記ベース層金属と接するように設置される、ステップと、
次に、前記拡散バリア層上に、CoBおよびNiPの一つを有するウェッティング層を形成するステップと、
を有する方法。 - 前記バンプ層は、外表面を有し、前記バンプ層の外表面は、Snを含む層から物理的に離れていることを特徴とする請求項7に記載の方法。
- 回路基板を有するシステムであって、
回路を有する1または2以上の部品、および
回路基板上の1または2以上の層であって、前記回路基板上の部品間に、少なくとも一つの信号を伝送する層、
を有し、
前記回路基板上の少なくとも一つの部品は、ダイパッケージ相互接続部を有し、該相互接続部は、
半導体基板と、
該半導体基板と接する第1の導電層であって、Cuを含むベース層金属を有する第1の導電層と、
該第1の導電層と接する拡散バリアであって、ホウ素およびリンを含む金属合金を有する拡散バリアと、
該拡散バリア上の、CoBおよびNiPの一つを有するウェッティング層と、
該ウェッティング層と接し、Snを含むバンプ層であって、電気メッキで形成されたバンプ層と、
を有し、
前記拡散バリアは、CuおよびSnが前記拡散バリアを介して拡散することを抑制し、当該システムにCuSn金属間化合物が形成されることを抑制するように構成されるシステム。
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Also Published As
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JP2015167257A (ja) | 2015-09-24 |
US7276801B2 (en) | 2007-10-02 |
US8580679B2 (en) | 2013-11-12 |
US20110084387A1 (en) | 2011-04-14 |
US20190198472A1 (en) | 2019-06-27 |
TWI251921B (en) | 2006-03-21 |
JP2007506284A (ja) | 2007-03-15 |
US10249588B2 (en) | 2019-04-02 |
WO2005031848A1 (en) | 2005-04-07 |
HK1093380A1 (en) | 2007-03-02 |
TW200520192A (en) | 2005-06-16 |
JP2013138260A (ja) | 2013-07-11 |
US20220059484A1 (en) | 2022-02-24 |
US20170084564A1 (en) | 2017-03-23 |
JP4629042B2 (ja) | 2011-02-09 |
US20050062169A1 (en) | 2005-03-24 |
JP5284314B2 (ja) | 2013-09-11 |
US11201129B2 (en) | 2021-12-14 |
CN100492607C (zh) | 2009-05-27 |
US20080213996A1 (en) | 2008-09-04 |
US9543261B2 (en) | 2017-01-10 |
JP6078585B2 (ja) | 2017-02-08 |
CN1853263A (zh) | 2006-10-25 |
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