CN1853263A - 导电凸起的设计和方法 - Google Patents

导电凸起的设计和方法 Download PDF

Info

Publication number
CN1853263A
CN1853263A CNA2004800271614A CN200480027161A CN1853263A CN 1853263 A CN1853263 A CN 1853263A CN A2004800271614 A CNA2004800271614 A CN A2004800271614A CN 200480027161 A CN200480027161 A CN 200480027161A CN 1853263 A CN1853263 A CN 1853263A
Authority
CN
China
Prior art keywords
layer
diffusion barrier
convexity
metal
electroless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004800271614A
Other languages
English (en)
Other versions
CN100492607C (zh
Inventor
M·玻尔
S·巴拉克利施南
V·杜宾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1853263A publication Critical patent/CN1853263A/zh
Application granted granted Critical
Publication of CN100492607C publication Critical patent/CN100492607C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H01L2224/11614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1312—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

涉及管芯封装的方法、技术和结构。在一个典型实现中，管芯封装互连结构包括半导体衬底以及与所述半导体衬底接触的第一导电层。该第一导电层可包括基极层金属(230)。所述基极层金属可包括Cu。该典型实现还包括与所述第一导电层接触的扩散阻挡物(225)以及在所述扩散阻挡物之上的润湿层。凸起层(215)可位于所述润湿层之上，其中所述凸起层包括Sn并且Sn可被电镀。此外，所述扩散阻挡物还适于抑制凸起层中类晶须的形成。

Description

导电凸起的设计和方法
技术领域
本说明书涉及半导体工艺制造，尤其涉及制造在管芯封装内的集成电路凸起。
背景技术
在管芯封装工艺中，在管芯衬底和周围封装之间可放置多层导电层。管芯封装可以使用导电层来焊接并且焊接层可以与低层的导电层相接触。可以在所述低层导电层上形成图案使其具有一个或多个导电凸起，并可被称为“凸起”层。凸起可以接触直接或间接连接至所述衬底的基极层金属。所述凸起和基极层金属具有可能会导致一个或多个电迁移问题或层老化的一种或多种性质。
附图说明
图1A到图1D示出了典型的缺陷凸起示意图。
图2示出了制造结构的典型实施例。
图3是图2中示出的制造的典型实现的典型流程图。
图4示出了制造结构的典型实施例。
图5是图4中示出的制造的典型实现的典型流程图。
图6示出了制造结构的典型实施例。
图7是图6中示出的制造的典型实现的典型流程图。
图8示出了在电气/计算机系统中管芯封装结构的典型实现。
具体实施方式
本发明的一个或多个典型实施例的技术、方法和结构涉及集成电路和管芯封装。一个或多个典型实现尤其涉及在衬底上制造凸起以避免Cu和Sn的混合。本发明中的一个或多个典型实现可以减少与CuSn金属间形成有关的电迁移问题，并且可以减少一层或多层中晶须的形成。
将在附图和以下的描述中阐明一个或多个典型实现的细节。在一个典型实现中，一种装置包括半导体衬底以及与所述半导体衬底接触的第一导电层。第一导电层可包括基极层金属，诸如Cu。所述装置还包括与所述第一导电层接触的扩散阻挡物、在所述扩散阻挡物之上的润湿层以及在所述润湿层之上的凸起层。所述凸起层包括Sn。并且所述Sn凸起层可以是电镀的。扩散阻挡物可以防止Cu和Sn扩散通过所述扩散阻挡物。所述扩散阻挡物还能够抑制所述凸起层内类晶须的形成。一个或多个典型实现的其他性质和优点从所述说明和附图以及权利要求中显而易见。
在半导体晶片处理中，在衬底上形成器件和互连并电气连接至管芯封装。可以通过所述管芯封装和晶片上低层导电互连层之间的导电焊接层来实现与管芯封装的电气连接。所述焊接层有时包括Sn或Sn合金。所述导电互连层或相邻的导电层有时包括Cu。在某些实例中，导电互连层可以是最低层的金属层或者是最接近于所述衬底的金属层。这一金属层可被称为是基极层金属(BLM)。在某些实例中，所述基极层金属可用作扩散阻挡物以避免焊料迁移入该管芯的低层焊盘。该管芯的焊盘可以包括一层或多层金属层，诸如Al层。在本发明的一个或多个典型实现中，可以在基极层金属上形成一层用作在所述基极层金属中的Cu和在扩散阻挡物之上的Sn之间的扩散阻挡物。
在一层内使用Sn并在邻近层内使用Cu的管芯封装互连结构会导致该管芯互连的一个或多个有害问题。这些有害问题中的某一些会劣化该管芯封装互连的电学和机械性质，降低形成该互连的成品率，甚至会形成不规则的、不需要的区域，诸如晶须和分层。分层可包括一层或多层的劣化或物理分离。这些有害问题的一部分在图1A到图1D列举并且将在以下描述。
图1A和图1B示出了带有电学凸起分层的管芯封装互连的示意图。在图1A中的凸起110是包括了Sn合金和PbSn的焊料区。如标记区115所示，凸起110具有下层互连或基极层金属125相符合的形状。凸起110可以接触并覆盖下层互连或基极层金属的边缘和侧壁。
图1B示出了其中包括基极层金属125、PbSn凸起110和管芯衬底区130的区域115的示意图。在此示意图中，在衬底130和凸起110之间的层125和110出现了分层。这一分层是由所述基极层金属125的一种或多种性质导致的。所述基极层金属125可能会以其在烘烤或热处理期间的劣化的方式而被构造。劣化和分层会减少层125和110之间的导电表面区域并会产生电迁移相关的缺陷。
管芯封装互连中的某些缺陷可以是电迁移相关的缺陷，并且可由层材料和层分界面的性质引起其他缺陷。某些电迁移相关的缺陷是由层125和110的冶金学性质、增加的热问题以及层125和110之间一个或多个空隙120的生长所引起的。区域115内的电迁移会产生更高的电流密度并会增加电磁应力。如下将在一个或多个典型实现中描述，示出的方法、结构和技术能够减少电迁移相关的管芯封装互连的缺陷。
一层或多层管芯封装互连的某些冶金学性质会导致管芯封装互连的缺陷。这些冶金学性质的实例包括不兼容的表面、不同温度下材料的相变以及不同层元素的扩散和混合。例如，Sn是用于一层或多层管芯封装互连层的常用金属。然而Sn在不同的温度下存在两种同素异形体。在约13.2℃以上的温度下，坚硬、有光泽并导电的αSn(四方形结构、α相的Sn)处于稳定相。而当温度低于13.2℃时，βSn(金刚石立方结构、β相的Sn)则是热活泼的。α相是层结构中的首选相。由于两相的密度不同，所以α到β相的转化伴随着26％的体积膨胀。相变中的体积改变会使得Sn和其他层之间的分界面变形。而且βSn是粉末状的并且不具有可用于互连的机械强度。因此当Sn处于β相时，会使Sn层的机械强度和互连劣化。至少由于上述理由，Sn层或互连在低温下会从α相变成β相并导致互连缺陷。以下将在一个或多个典型实现中详述，示出的方法、技术和结构可以防止低温下Sn的相变。
虽然示出凸起110作为100中的焊料凸起，但是所述凸起可以不是焊料层而是与焊料层相邻层的凸起或凸起层。此外，凸起110不是直接接触所述管芯封装105。如在所述附图中描述，凸起或凸起层可以包括诸如Cu的其他材料并且可以直接连接至所述基极层金属或其他层互连。
图1C和图1D示出了不同层的Cu和Sn的非期望混合的实例。例如，图1C示出了在互连层内带有空隙155的管芯封装互连150。来自不同层的Cu和Sn的扩散或混合会形成CuSn金属间化合并且可以帮助产生空隙155。互连150中的电抗会因为所述焊料中的空隙而增加并且导致电迁移问题。其他诸如晶须的非期望的形成也可由于Cu和Sn的混合而形成。晶须会导致在Sn凸起中建立的压缩应力并且会导致管芯封装互连的缺陷。
图1D示出了带有扩散的或混合的Cu和Sn的管芯封装互连的各层的另一个典型图表160。图1D示出了Cu和Sn形成的实例。例如在图160中，Cu3Sn的区域165和Cu6Sn5的区域170已在Cu层172和178以及Sn层176之间形成。
某些传统的技术企图避免来自不同管芯封装互连层的Cu和Sn的混合和扩散。例如，Pb5Sn凸起的使用就可用于防止晶须的形成。然而对Pb5Sn的使用会导致由如上所述低温下Sn相变所引起的电迁移问题。此外，Pb会产生环境和健康问题。在另一个传统实例中，溅射的Ni可用于防止Cu扩散入Sn。然而，溅射Ni的扩散阻挡物性质很差并且不足以阻止Cu和Sn的扩散或混合。如下在一个或多个典型实现中所述，示出的方法、技术和结构能够防止不同管芯封装互连层之间的Cu和Sn的混合和扩散。
在本发明中的一个或多个典型实现也示出了在所述基极层金属蚀刻期间防止Sn凸起劣化的方法、技术和结构。一般而言，在蚀刻包括Ti、Al或NiV的基极层金属时是能够避免Sn凸起的侵蚀和氧化的。
图2示出了管芯封装互连的一个典型实现。基极层金属230在硅衬底205之上形成并且所述基极层金属230可以包括Cu。基极层金属230也图案化在绝缘体、树脂或介电层235(诸如聚酰亚胺层)之上。基极层金属230可以包括粘附层232和籽晶层234。粘附层232可以在例如衬底205或介电层235之上形成。粘附层232有助于连接或粘附两个不同的表面，诸如有助于基极层金属粘附住底层表面。籽晶层234有助于在粘附层232上建立基极层金属结构。所述籽晶层可以作为底层的平坦表面并且可以促进所述基极层金属的正确生长和形成。粘附层232可包括Ti、TiN和TiSiN并且籽晶层234也可包括Ni、NiV和Co。可以在粘附层232和籽晶层234之间形成诸如Al层233的附加金属层以改善所述基极层金属的一种或多种性质。带有附加金属层的所述基极层金属性质的改善包括抑制所述晶须的形成以及防止热处理期间的分层和劣化以及电磁应力。
扩散阻挡物层225可选择性地设置在基极层金属230之上。选择性的沉积意味着某些表面可以具有仅在该表面部分上沉积的另一层。无电镀的扩散阻挡物可以阻止Cu和Sn扩散通过所述扩散阻挡物。所述扩散阻挡物层225可以是无电镀的并且可以位于某个位置上以阻止来自所述基极层金属230的Cu与来自所述凸起层215或焊料层210的Sn的混合。扩散阻挡物层225可以防止CuSn金属间化合的形成以及晶须的形成。扩散阻挡物层225可以避免凸起的分层并且能够改善生产管芯封装互连的成品率工艺。所述扩散阻挡物层225可以包括但不限于CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP中的任何一种。
当在不规则形状的物体、图形和凹进部分上沉积时，无电镀沉积具有一种或多种优势。在无电镀层中，电子是由化学还原剂提供的。一般来说，无电镀层指的是包含还原剂的溶液中金属离子的还原。所述还原剂可以通过接触反应表面的氧化来提供电子。无电镀沉积可以具有较高的均匀性并且在电镀时基本没有压缩应力。无电镀沉积倾向于在整个底层结构形状上的厚度均匀，因此就提供了更为均匀的电流密度并减少了某些电迁移问题。无电镀阻挡物还具有低成本、选择性和无定形的优点。
扩散阻挡物具有避免或抑制Sn通过扩散阻挡物扩散至Cu的其他材料。例如可以使用具有较慢反应或扩散Cu和Sn的可电镀材料，诸如来自族VIII的金属(例如Co、Ni、Fe、Ru、Rh、Ir和Os)与来自族VI(例如W、Mo和Cr)和非金属(例如B、P和N)的合金。
润湿层(未示出)可位于扩散阻挡物层225之上。润湿层也可选择性地沉积在部分扩散阻挡物层225上。润湿层可以包括CoB、NiB和NiP的任何一种。
把凸起层215放置于润湿层之上并把焊料层210放置在凸起层之上。管芯封装220位于焊料层210之上并与其电气连接。与所述管芯封装220的电气连接允许电流可在管芯封装和器件以及接近或在所述衬底之上的互连之间流动。凸起层215、焊料层510或这两层210和215都可含有Sn。
在本发明一个或多个典型实现中，可以电镀Sn以抑制晶须的形成以及相关的电迁移缺陷。Sn的电镀也可以防止低温下(例如约13.2℃)Sn的相变并且避免涉及βSn的机械和电迁移缺陷。Sn的电镀包括Sn和Sn合金，诸如0.7Cu、Bi、Sb以及3.5Ag。可以在包含锡盐(例如硫酸锡、氯化锡)、酸(例如硫酸、磺酸)和其他添加剂(例如类似聚醚二醇的抑制剂或者晶粒细化剂和抗氧化剂)的溶液中以恒定的电流(例如约为10-100mA/em2)或电压进行锡的电镀。
图3是图2中示出的制造典型实现的典型流程图。在310处，可在晶片上形成一个或多个器件或Cu互连。随后在312处可使用SiN和聚酰亚胺钝化所述管芯封装互连200。通过使用光刻和蚀刻操作，可以为Cu的金属喷镀打开一个接触焊盘(未示出)。可以使用等离子汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)或电镀来沉积基极层金属230。所述基极层金属230可以包括粘附层(例如Ti、TiN或TiSiN)和籽晶层(例如Ni、NiV或Co)。可以在粘附层和籽晶层之间形成诸如Al的附加金属层以改善所述基极层金属230的阻挡物性质。
随后可在316处沉积并图案化光刻胶层。可在318处形成扩散阻挡物层225。扩散阻挡物层225可以是无电镀的并且可以包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP。随后在320处可以在所述扩散阻挡物层225上沉积润湿层。所述润湿层可以包括CoB、NiB、CoP以及NiP的任何一种。在322处可以执行Sn或Sn合金的电镀。Sn的某些合金可以包括0.7Cu、Bi、Sb和3.5Ag的任何一种。随后就在324处移除光刻胶并且在326处蚀刻所述基极层金属230。
用扩散阻挡物层225形成所述管芯封装互连200需要使用蚀刻来形成基极层金属230的图案。对基极层金属230的蚀刻会减轻Sn凸起和聚酰亚胺的劣化(例如腐蚀或氧化)。
图4示出了管芯封装互连的另一个典型实现400。凸起层415由Cu形成并且直接位于基极层金属430之上。基极层金属430也可以是Cu。扩散阻挡物层425可以是无电镀的并且可放置于(Cu)凸起层415之上和Sn或Sn合金层之下。扩散阻挡物层425可以提供类似于图2中互连200的扩散阻挡物层425的类似优点。例如，扩散阻挡物层425可以阻止(Cu)凸起层415和Sn层415之间通过所述扩散阻挡物层的Cu和Sn扩散或混合。扩散阻挡物层425能够避免在凸起层415中晶须的形成。虽然在图中示出了若干层415、425和435的典型厚度，但是层的厚度可以发生变化。
可以在Sn层435上形成焊料层410并且封装层420可以连接至所述焊料层410。封装层420可以在互连400中与其他所有的导电层410、435、425、415和430相连，从而允许电流在管芯和器件之间以及在衬底附近或之上的互连间流动。
图5示出了制造图4中示出的典型实现的典型流程图。用于互连400的在310、312、314和316处的流程能够以与图2到图3中用于互连200的流程类似的方式和次序出现。在518处，形成并电镀Cu凸起层415。Cu凸起层415的电镀可以提供均匀的厚度，抑制晶须的形成并且具有优于图2中电镀Sn凸起层215的低至零的压缩应力。在520处，扩散阻挡物层425可以是无电镀的并且在凸起层415上形成而在522处，就可在凸起层415上形成润湿层(图4中未示出)。无电镀扩散阻挡物层425包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP的任何一种而所述润湿层可包括CoB、NiB、CoP以及NiP的任何一种。
在524处，可以在所述润湿层上形成并电镀Sn层435。电镀Sn层435可以提供与上述在互连200中电镀Sn类似的优点。这些类似的优点包括抑制晶须的形成以及避免低温下Sn的相变。在526处移除光刻胶并且在528处蚀刻所述基极层金属430。可以在Sn层435上形成焊料层410并且封装层420可以连接至焊料层410。焊料层410可以包括Sn并还可被电镀。
图6示出了管芯封装互连的另一个典型实现600。凸起层615由Cu形成并且直接位于基极层金属630之上。基极层金属630可由Cu形成。扩散阻挡物层625可以是无电镀的并且可放置于Cu凸起层415之上和Sn或Sn合金层之下。扩散阻挡物层625可以包围凸起层615，而基极层金属630则接触凸起层615的底面。凸起层615的所有非基极层金属630的表面(包括顶面和侧面)可由无电镀扩散阻挡物层625覆盖。这样，凸起层615的外表面就能够与直接物理接触的包括Sn的层物理绝缘。无电镀扩散阻挡物层625可以提供类似于图4中互连400的扩散阻挡物层的类似优点。例如，扩散阻挡物层625可以阻止Cu凸起层615和Sn层415之间的Cu和Sn扩散或混合，并且防止凸起层615内晶须的形成。
可以在无电镀扩散阻挡物层625上形成焊料层610并且封装层620可以连接至焊料层610。焊料层610可以包括Sn并可被电镀。
图7示出了制造图6中示出的典型实现的典型流程图。用于互连600的在310、312、314、316和518处的流程能够以与图4到图5中用于互连400的流程类似的方式和次序出现。在720处，移除光刻胶并且在722处蚀刻所述基极层金属630。在724处，扩散阻挡物层625可以是无电镀的并且在凸起层615上形成而在726处，可在凸起层615上形成润湿层(图6中未示出)。无电镀扩散阻挡物层625包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP的任何一种而所述润湿层可包括CoB、NiB、CoP以及NiP的任何一种。诸如焊料层610的其他导电层可在无电镀扩散阻挡物层625上并且润湿层可以连接至封装层620。
图8示出了电子计算系统中管芯封装结构的一个典型实现。如上参考图3、5和7所述，在衬底上形成用于管芯封装的一个或多个互连和层。当被放置在电路板850上时，管芯封装810可以将管芯封装内部的电路与管芯封装外部且在电路板850上的电路相连接。电路板850可以是其他的芯片或组件，诸如存储器843、中央处理单元(CPU)825以及控制器或其他的逻辑单元833。电路板850可采用多层制成，以便于在组件之间的信号连接，并且可在计算机和/或电子系统860中使用。
已经讨论了本发明的多个实现。然而应该认识到可以做出多种修改而不背离本发明的精神和范围。例如，处理过程可以与图3、5和7中示出的处理次序不同。例如在图7中，在互连600的518处形成并电镀了Cu层之后，才在724处沉积无电镀的扩散阻挡物层625。在726处在无电镀的扩散阻挡物层625上形成润湿层后，才在720处移除光刻胶并在722处蚀刻所述基极层金属630。在另一个实例中，可使用无电镀阻挡物来防止除了Cu和Sn之外的其他金属的混合，诸如防止Au和Al的混合。

Claims (33)

1.一种装置，包括：
半导体衬底；
与所述半导体衬底接触的第一导电层，所述第一导电层包括基极层金属，所述基极层金属包括Cu；
与所述第一导电层接触的扩散阻挡物；
在所述扩散阻挡物之上的润湿层；以及
在所述润湿层之上的凸起层，所述凸起层包括Sn，所述Sn凸起层被电镀，所述扩散阻挡物适于防止Cu和Sn扩散通过所述扩散阻挡物。
2.如权利要求1所述的装置，其特征在于，所述扩散阻挡物是无电镀扩散阻挡物。
3.如权利要求1所述的装置，其特征在于，还包括位于所述凸起层和管芯封装之间的焊料层，其中所述焊料层包括Sn。
4.如权利要求1所述的装置，其特征在于，所述基极层金属包括粘附层和籽晶层，其中所述粘附层包括Ti、TiN和TiSiN中的一种并且籽晶层包括Ni、NiV和Co中的一种。
5.如权利要求4所述的装置，其特征在于，所述基极层金属还包括位于所述粘附层和所述籽晶层之间的金属层，其中所述金属层包括Al。
6.如权利要求1所述的装置，其特征在于，所述扩散阻挡物层包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP中的一种，并且所述凸起层还包括Sn合金，所述Sn合金包括0.7Cu、Bi、Sb和3.5Ag中的一种，其中被电镀的Sn凸起层还适于防止Sn从αSn到βSn的低温相变。
7.如权利要求1所述的装置，其特征在于，所述湿润层还包括CoB、NiB和NiP中的一种，其中所述扩散阻挡物还适于减少凸起层的分层。
8.如权利要求1所述的装置，其特征在于，所述装置还包括被溅射的基极层金属，其中所述扩散阻挡物还适于减少与CuSn金属间化合形成相关的电迁移。
9.一种装置，包括：
在半导体衬底上的基极层金属，所述基极层金属包括Cu；
在所述基极层金属之上的凸起层，所述凸起层包括被电镀的Cu层；
与所述凸起层相接触的扩散阻挡物；
在所述扩散阻挡物之上的润湿层；以及
与所述凸起层相接触的焊料层，所述焊料层包括Sn，所述扩散阻挡物还适于防止Cu和Sn通过所述扩散阻挡物的扩散。
10.如权利要求9所述的装置，其特征在于，所述扩散阻挡物包括无电镀扩散层。
11.如权利要求9所述的装置，其特征在于，所述基极层金属包括粘附层和籽晶层，其中所述粘附层包括Ti、TiN和TiSiN中的一种并且籽晶层包括Ni、NiV和Co中的一种。
12.如权利要求10所述的装置，其特征在于，所述基极层金属还包括位于所述粘附层和所述籽晶层之间的金属层，其中所述金属层包括Al，其中所述扩散阻挡物适于抑制所述凸起层中类晶须的形成。
13.如权利要求12所述的装置，其特征在于，所述基极层金属还与所述扩散阻挡物相接触以便于使所述凸起层的所有表面与所述焊料层物理绝缘。
14.如权利要求9所述的装置，其特征在于，所述扩散阻挡物层包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP中的一种，其中并且所述湿润层包括CoB、NiB和NiP中的一种。
15.一种方法，包括：
使用SiN和聚酰亚胺进行钝化；
沉积基极层金属；
沉积光刻胶层；
形成扩散阻挡物，所述扩散阻挡物适于防止不同层之间的Cu和Sn混合；
在所述扩散阻挡物之上形成润湿层；
形成凸起层；
移除所述光刻胶层；以及
蚀刻所述基极层金属。
16.如权利要求15所述的方法，其特征在于，沉积所述基极层金属包括等离子汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)中的一种，其中所述扩散阻挡物包括无电镀扩散阻挡物。
17.如权利要求16所述的方法，其特征在于，所述基极层金属包括粘附层和籽晶层，其中所述粘附层包括Ti、TiN或TiSiN中的一种而所述籽晶层包括Ni、NiV或Co中的一种，其中所述无电镀扩散阻挡物还适于减轻凸起层分层。
18.如权利要求17所述的方法，其特征在于，沉积所述基极层金属包括在所述粘附层和所述籽晶层之间沉积金属层，所述基极层金属还包括一个或多个电气互连。
19.如权利要求18所述的方法，其特征在于，所述金属层包括Al，其中所述光刻胶层适于图案化，而且所述无电镀扩散阻挡物还适于减少与CuSn金属间化合形成相关的电迁移。
20.如权利要求16所述的方法，其特征在于，所述无电镀扩散阻挡物层包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP中的一种。
21.如权利要求16所述的方法，其特征在于，所述凸起层包括Sn，所述Sn被电镀以防止Sn从αSn到βSn的低温相变，其中所述被电镀的Sn还适于抑制晶须的形成。
22.如权利要求16所述的方法，其特征在于，所述凸起层还包括Sn合金，所述Sn合金包括0.7Cu、Bi、Sb和3.5Ag中的一种，其中Sn合金被电镀以防止Sn从αSn到βSn的低温相变。
23.如权利要求16所述的方法，其特征在于，还包括：
让焊料层形成所述凸起层，所述焊料层包括Sn；以及
连接管芯封装至所述焊料层。
24.一种方法，包括：
使用SiN和聚酰亚胺进行钝化；
沉积基极层金属；
沉积光刻胶层；
形成Cu层，所述Cu层被电镀；
形成无电镀扩散阻挡物，所述无电镀扩散阻挡物位于所述Cu层和Sn层之间，所述无电镀扩散阻挡物适于防止Cu和Sn通过所述无电镀扩散阻挡物扩散；
在所述无电镀扩散阻挡物之上形成润湿层；
移除所述光刻胶层；以及
蚀刻所述基极层金属。
25.如权利要求24所述的方法，其特征在于，还包括在所述润湿层和所述无电镀扩散阻挡物之上形成焊料区，其中所述焊料区与管芯封装相接触，其中所述焊料区包括Sn。
26.如权利要求24所述的方法，其特征在于，所述Sn层包括在所述无电镀扩散阻挡物之上的焊料区，所述焊料区与管芯封装相接触。
27.如权利要求24所述的方法，其特征在于，所述无电镀扩散阻挡物层包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP中的一种。
28.一种方法，包括：
使用SiN和聚酰亚胺进行钝化；
沉积基极层金属；
沉积光刻胶层；
形成凸起层，所述凸起层包括Cu，所述Cu凸起层被电镀；
移除所述光刻胶层；
蚀刻所述基极层金属；
形成无电镀扩散阻挡物层，所述无电镀扩散阻挡物层被设置在所述Cu凸起层和Sn层之间，所述无电镀扩散阻挡物层适于防止通过所述不同层之间的Cu和Sn混合；以及
在所述无电镀扩散阻挡物层之上形成润湿层。
29.如权利要求28所述的方法，其特征在于，所述无电镀扩散阻挡物层包括CoBP、CoWP、CoWB、CoWBP、NiBP、NiWP、NiWB以及NiWBP中的一种，其中所述基极层金属包括粘附层和籽晶层，其中所述粘附层包括Ti、TiN和TiSiN中的一种并且所述籽晶层包括Ni、NiV和Co中的一种。
30.如权利要求28所述的方法，其特征在于，所述基极层金属还物理接触所述无电镀扩散阻挡物层，其中所述凸起层包括外表面，其中所述凸起层的所述外表面与接触包括Sn的层物理绝缘的。
31.如权利要求28所述的方法，其特征在于，所述Cu凸起层还适于防止晶须的形成，其中所述无电镀扩散阻挡物层还适于减轻与CuSn金属间化合形成相关的电迁移。
32.一种具有电路板的系统，包括：
含有电路的一个或多个组件；以及
用于在所述电路板上各组件之间路由至少一个信号的所述电路板上的一层或多层，其中在所述电路板上的至少一个所述组件包括管芯封装互连，所述管芯封装互连包括：
半导体衬底；
与所述半导体衬底接触的第一导电层，所述第一导电层包括基极层金属，所述基极层金属包括Cu；
与所述第一导电层接触的扩散阻挡物；
在所述扩散阻挡物之上的润湿层；以及
在所述润湿层之上的凸起层，所述凸起层包括Sn，所述Sn凸起层被电镀，所述扩散阻挡物适于防止Cu和Sn扩散通过所述扩散阻挡物。
33.如权利要求32所述的系统，其特征在于，所述一个或多个组件包括中央处理单元、存储器和逻辑单元中的任何一种。
CNB2004800271614A 2003-09-22 2004-09-17 包括导电凸起的微电子器件及其制备方法 Expired - Lifetime CN100492607C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/668,986 US7276801B2 (en) 2003-09-22 2003-09-22 Designs and methods for conductive bumps
US10/668,986 2003-09-22

Publications (2)

Publication Number Publication Date
CN1853263A true CN1853263A (zh) 2006-10-25
CN100492607C CN100492607C (zh) 2009-05-27

Family

ID=34313628

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800271614A Expired - Lifetime CN100492607C (zh) 2003-09-22 2004-09-17 包括导电凸起的微电子器件及其制备方法

Country Status (6)

Country Link
US (6) US7276801B2 (zh)
JP (4) JP4629042B2 (zh)
CN (1) CN100492607C (zh)
HK (1) HK1093380A1 (zh)
TW (1) TWI251921B (zh)
WO (1) WO2005031848A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102496606A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 一种高可靠圆片级柱状凸点封装结构
CN102496605A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 一种圆片级封装结构
CN102971840A (zh) * 2010-07-07 2013-03-13 朗姆研究公司 用于金属化的方法、器件和材料
CN105097743A (zh) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 键合结构及其形成方法
CN108886003A (zh) * 2016-03-31 2018-11-23 株式会社荏原制作所 基板的制造方法及基板
CN110066984A (zh) * 2013-09-27 2019-07-30 应用材料公司 实现无缝钴间隙填充的方法
CN114639767A (zh) * 2020-12-15 2022-06-17 乐金显示有限公司 光源单元和包括该光源单元的显示装置

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7276801B2 (en) 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
US6933171B2 (en) * 2003-10-21 2005-08-23 Intel Corporation Large bumps for optical flip chips
US7273803B2 (en) * 2003-12-01 2007-09-25 International Business Machines Corporation Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
WO2007008171A2 (en) * 2005-07-09 2007-01-18 Gautham Viswanadam Integrated circuit device and method of manufacturing thereof
US7541681B2 (en) * 2006-05-04 2009-06-02 Infineon Technologies Ag Interconnection structure, electronic component and method of manufacturing the same
JP2007305667A (ja) * 2006-05-09 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
US7569422B2 (en) 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
US8168537B2 (en) * 2006-08-17 2012-05-01 Nxp B.V. Semiconductor component and assumbly with projecting electrode
DE102006047761A1 (de) * 2006-10-06 2008-04-10 Infineon Technologies Ag Halbleiterbauteil und Verfahren zu dessen Herstellung
US20100200991A1 (en) * 2007-03-15 2010-08-12 Rohan Akolkar Dopant Enhanced Interconnect
US9214442B2 (en) * 2007-03-19 2015-12-15 Infineon Technologies Ag Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip
US7919859B2 (en) * 2007-03-23 2011-04-05 Intel Corporation Copper die bumps with electromigration cap and plated solder
US7615865B2 (en) * 2007-05-21 2009-11-10 Stats Chippac, Ltd. Standoff height improvement for bumping technology using solder resist
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
US8293587B2 (en) 2007-10-11 2012-10-23 International Business Machines Corporation Multilayer pillar for reduced stress interconnect and method of making same
DE102008016427B4 (de) 2008-03-31 2018-01-25 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Drahtbonden auf reaktiven Metalloberflächen einer Metallisierung eines Halbleiterbauelements durch Vorsehen einer Schutzschicht
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
JP5572979B2 (ja) * 2009-03-30 2014-08-20 ソニー株式会社 半導体装置の製造方法
US8592995B2 (en) 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US8445375B2 (en) * 2009-09-29 2013-05-21 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
KR101187977B1 (ko) 2009-12-08 2012-10-05 삼성전기주식회사 패키지 기판 및 그의 제조방법
JP5387695B2 (ja) 2009-12-28 2014-01-15 富士通株式会社 配線構造の形成方法
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US20110226613A1 (en) 2010-03-19 2011-09-22 Robert Rash Electrolyte loop with pressure regulation for separated anode chamber of electroplating system
US8492891B2 (en) 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8426236B2 (en) 2010-05-07 2013-04-23 International Business Machines Corporation Method and structure of photovoltaic grid stacks by solution based processes
US8993431B2 (en) * 2010-05-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure
US9620469B2 (en) * 2013-11-18 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming post-passivation interconnect structure
US9916763B2 (en) 2010-06-30 2018-03-13 Primal Space Systems, Inc. Visibility event navigation method and system
US8232193B2 (en) 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US9048135B2 (en) 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
US8587116B2 (en) 2010-09-30 2013-11-19 Infineon Technologies Ag Semiconductor module comprising an insert
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US9404194B2 (en) * 2010-12-01 2016-08-02 Novellus Systems, Inc. Electroplating apparatus and process for wafer level packaging
US8610285B2 (en) * 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
JP6035714B2 (ja) * 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
CN102437066A (zh) * 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 一种高可靠圆片级柱状凸点封装方法
CN102496580B (zh) * 2011-12-19 2016-02-03 南通富士通微电子股份有限公司 一种焊料凸点的形成方法
CN102446780A (zh) * 2011-12-19 2012-05-09 南通富士通微电子股份有限公司 一种圆片级封装方法
US9475145B2 (en) 2012-02-27 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump joint in a device including lamellar structures
US9842817B2 (en) 2012-02-27 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump stretching method and device for performing the same
KR101932727B1 (ko) 2012-05-07 2018-12-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 이의 제조 방법
US8803333B2 (en) 2012-05-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
US9534308B2 (en) 2012-06-05 2017-01-03 Novellus Systems, Inc. Protecting anodes from passivation in alloy plating systems
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8659153B2 (en) 2012-07-16 2014-02-25 Micron Technology, Inc. Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
WO2014037996A1 (ja) * 2012-09-04 2014-03-13 三菱電機株式会社 半導体装置、半導体装置の製造方法
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
TWI466253B (zh) 2012-10-08 2014-12-21 Ind Tech Res Inst 雙相介金屬接點結構及其製作方法
KR20140114252A (ko) 2013-03-14 2014-09-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 장치에서 땜납 범프 조인트를 형성하기 위한 땜납 범프 연신 방법
CN104347534B (zh) * 2013-08-05 2017-05-24 中芯国际集成电路制造(上海)有限公司 倒装芯片的封装方法和封装基板
JP6046010B2 (ja) * 2013-09-09 2016-12-14 株式会社東芝 半導体装置及びその製造方法
US9152751B2 (en) * 2013-09-30 2015-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Metal lines for preventing AC electromigration
KR102245825B1 (ko) 2014-09-04 2021-04-30 삼성전자주식회사 반도체 패키지
US10006136B2 (en) 2015-08-06 2018-06-26 Dow Global Technologies Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole compounds, bisepoxides and halobenzyl compounds
US9932684B2 (en) 2015-08-06 2018-04-03 Rohm And Haas Electronic Materials Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of alpha amino acids and bisepoxides
US10100421B2 (en) 2015-08-06 2018-10-16 Dow Global Technologies Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole and bisepoxide compounds
TWI608132B (zh) 2015-08-06 2017-12-11 羅門哈斯電子材料有限公司 自含有吡啶基烷基胺及雙環氧化物之反應產物的銅電鍍覆浴液電鍍覆光阻劑限定之特徵的方法
US9754911B2 (en) 2015-10-05 2017-09-05 Globalfoundries Inc. IC structure with angled interconnect elements
US10522485B2 (en) * 2015-12-21 2019-12-31 Intel IP Corporation Electrical device and a method for forming an electrical device
US11100589B1 (en) 2016-09-02 2021-08-24 State Farm Mutual Automobile Insurance Company Systems and methods for analyzing unmanned aerial missions
US10076034B2 (en) * 2016-10-26 2018-09-11 Nanya Technology Corporation Electronic structure
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
CN111630211B (zh) 2017-11-01 2024-05-24 朗姆研究公司 控制在电化学镀敷设备上的镀敷电解液浓度
US11011483B2 (en) * 2018-02-21 2021-05-18 Texas Instruments Incorporated Nickel alloy for semiconductor packaging
US10790251B2 (en) * 2018-06-20 2020-09-29 Micron Technology, Inc. Methods for enhancing adhesion of three-dimensional structures to substrates
JP2020047775A (ja) * 2018-09-19 2020-03-26 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法および半導体装置

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068712A (en) * 1988-09-20 1991-11-26 Hitachi, Ltd. Semiconductor device
US4880708A (en) * 1988-07-05 1989-11-14 Motorola, Inc. Metallization scheme providing adhesion and barrier properties
JPH0492432A (ja) * 1990-08-08 1992-03-25 Seiko Epson Corp 半導体装置
JPH05175275A (ja) * 1991-12-25 1993-07-13 Nec Corp 半導体チップの実装方法および実装構造
JP2796919B2 (ja) * 1992-05-11 1998-09-10 インターナショナル・ビジネス・マシーンズ・コーポレーション メタライゼーション複合体および半導体デバイス
JPH06140406A (ja) 1992-10-23 1994-05-20 Toshiba Corp バンプを備える半導体素子
JP2784122B2 (ja) * 1992-10-29 1998-08-06 ローム株式会社 半導体装置の製法
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
US5346118A (en) * 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US5384283A (en) * 1993-12-10 1995-01-24 International Business Machines Corporation Resist protection of ball limiting metal during etch process
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
DE19524739A1 (de) * 1994-11-17 1996-05-23 Fraunhofer Ges Forschung Kernmetall-Lothöcker für die Flip-Chip-Technik
US5775569A (en) * 1996-10-31 1998-07-07 Ibm Corporation Method for building interconnect structures by injection molded solder and structures built
JP3654485B2 (ja) * 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6181012B1 (en) 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6607613B2 (en) * 1998-07-10 2003-08-19 International Business Machines Corporation Solder ball with chemically and mechanically enhanced surface properties
JP2000101014A (ja) 1998-09-22 2000-04-07 Hitachi Ltd 半導体装置
JP3813367B2 (ja) 1998-12-22 2006-08-23 三洋電機株式会社 半導体装置およびその製造方法
JP2000252313A (ja) * 1999-02-25 2000-09-14 Sony Corp メッキ被膜の形成方法および半導体装置の製造方法
US6285083B1 (en) * 1999-03-24 2001-09-04 Shinko Electric Industries Co., Ltd. Semiconductor device and mounting structure of a semiconductor device
JP2000353703A (ja) 1999-06-11 2000-12-19 Sony Corp 半導体装置の製造方法
US20020017789A1 (en) 1999-06-16 2002-02-14 Holmes William W. Gland pipe fitting
JP2001085390A (ja) 1999-09-09 2001-03-30 Sony Corp 半導体装置の製造方法
JP3859403B2 (ja) * 1999-09-22 2006-12-20 株式会社東芝 半導体装置及びその製造方法
US6372622B1 (en) 1999-10-26 2002-04-16 Motorola, Inc. Fine pitch bumping with improved device standoff and bump volume
SG99331A1 (en) * 2000-01-13 2003-10-27 Hitachi Ltd Method of producing electronic part with bumps and method of producing elctronic part
US6335104B1 (en) * 2000-02-22 2002-01-01 International Business Machines Corporation Method for preparing a conductive pad for electrical connection and conductive pad formed
US6517602B2 (en) * 2000-03-14 2003-02-11 Hitachi Metals, Ltd Solder ball and method for producing same
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
JP3701542B2 (ja) 2000-05-10 2005-09-28 シャープ株式会社 半導体装置およびその製造方法
JP2002057252A (ja) * 2000-08-07 2002-02-22 Hitachi Ltd 半導体装置及びその製造方法
JP2002076046A (ja) 2000-09-04 2002-03-15 Citizen Watch Co Ltd 半導体装置の製造方法
JP4174174B2 (ja) * 2000-09-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置およびその製造方法並びに半導体装置実装構造体
JP3640876B2 (ja) * 2000-09-19 2005-04-20 株式会社ルネサステクノロジ 半導体装置及び半導体装置の実装構造体
US6716330B2 (en) * 2000-10-26 2004-04-06 Ebara Corporation Electroless plating apparatus and method
JP3433732B2 (ja) * 2000-11-22 2003-08-04 住友電気工業株式会社 光半導体気密封止容器及び光半導体モジュール並びに光ファイバー増幅器
JP3683179B2 (ja) * 2000-12-26 2005-08-17 松下電器産業株式会社 半導体装置及びその製造方法
JP3910363B2 (ja) * 2000-12-28 2007-04-25 富士通株式会社 外部接続端子
US6433427B1 (en) * 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
JP4638614B2 (ja) 2001-02-05 2011-02-23 大日本印刷株式会社 半導体装置の作製方法
TW531873B (en) 2001-06-12 2003-05-11 Advanced Interconnect Tech Ltd Barrier cap for under bump metal
US6689680B2 (en) * 2001-07-14 2004-02-10 Motorola, Inc. Semiconductor device and method of formation
JP2003031576A (ja) * 2001-07-17 2003-01-31 Nec Corp 半導体素子及びその製造方法
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
JP2003124216A (ja) 2001-10-16 2003-04-25 Sony Corp 配線用シード膜および半導体装置の配線方法
JP3787295B2 (ja) * 2001-10-23 2006-06-21 ローム株式会社 半導体装置
JP3615206B2 (ja) * 2001-11-15 2005-02-02 富士通株式会社 半導体装置の製造方法
TW529143B (en) * 2001-12-03 2003-04-21 Advanced Semiconductor Eng Method for producing under-bump metallurgy layer (UBM)
JP3860028B2 (ja) 2001-12-25 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP3897596B2 (ja) 2002-01-07 2007-03-28 日本テキサス・インスツルメンツ株式会社 半導体装置と配線基板との実装体
US6541366B1 (en) * 2002-01-08 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving a solder bump adhesion bond to a UBM contact layer
US6732908B2 (en) 2002-01-18 2004-05-11 International Business Machines Corporation High density raised stud microjoining system and methods of fabricating the same
JP2005525694A (ja) * 2002-01-24 2005-08-25 ハネウェル・インターナショナル・インコーポレーテッド 薄膜、薄膜を有する構造、及び薄膜を形成する方法
US7535078B2 (en) * 2002-02-14 2009-05-19 Freescale Semiconductor, Inc. Semiconductor device having a fuse and method of forming thereof
TWI284376B (en) * 2002-02-21 2007-07-21 Advanced Semiconductor Eng Bump manufacturing method
US6528409B1 (en) * 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US6596621B1 (en) * 2002-05-17 2003-07-22 International Business Machines Corporation Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US6700207B2 (en) * 2002-08-05 2004-03-02 Lsi Logic Corporation Flip-chip ball grid array package for electromigration testing
US6797312B2 (en) * 2003-01-21 2004-09-28 Mattson Technology, Inc. Electroless plating solution and process
US6893799B2 (en) * 2003-03-06 2005-05-17 International Business Machines Corporation Dual-solder flip-chip solder bump
US6883889B2 (en) 2003-04-30 2005-04-26 Hewlett-Packard Development Company, L.P. Fluid ejection device
US7276801B2 (en) 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
JP2005175275A (ja) 2003-12-12 2005-06-30 Matsushita Electric Works Ltd Ｉｉｉ族金属窒化物結晶を用いた半導体発光素子およびこのｉｉｉ族金属窒化物結晶の製法
JP4495572B2 (ja) 2004-11-15 2010-07-07 シャープ株式会社 ステイン膜除去方法
KR101486587B1 (ko) * 2005-11-18 2015-01-26 레플리서러스 그룹 에스에이에스 마스터 전극 및 마스터 전극 형성 방법
JP2008203020A (ja) 2007-02-19 2008-09-04 Toppan Printing Co Ltd マイクロ分光分析方法
JP5638396B2 (ja) 2008-01-22 2014-12-10 アプライド マテリアルズ イスラエル リミテッド 微細要素の物質分析のためのシステムおよび方法
JP2011219946A (ja) 2010-04-07 2011-11-04 Ihi Transport Machinery Co Ltd 機械式駐車装置
AT521173B1 (de) 2018-06-27 2019-11-15 Trumpf Maschinen Austria Gmbh & Co Kg Biegewerkzeug mit Distanzelement

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102971840A (zh) * 2010-07-07 2013-03-13 朗姆研究公司 用于金属化的方法、器件和材料
US9006893B2 (en) 2010-07-07 2015-04-14 Lam Research Corporation Devices for metallization
CN102971840B (zh) * 2010-07-07 2016-11-09 朗姆研究公司 用于金属化的方法、器件和材料
CN102496606A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 一种高可靠圆片级柱状凸点封装结构
CN102496605A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 一种圆片级封装结构
CN110066984A (zh) * 2013-09-27 2019-07-30 应用材料公司 实现无缝钴间隙填充的方法
CN110066984B (zh) * 2013-09-27 2021-06-08 应用材料公司 实现无缝钴间隙填充的方法
CN105097743A (zh) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 键合结构及其形成方法
CN108886003A (zh) * 2016-03-31 2018-11-23 株式会社荏原制作所 基板的制造方法及基板
CN108886003B (zh) * 2016-03-31 2022-09-20 株式会社荏原制作所 基板的制造方法
CN114639767A (zh) * 2020-12-15 2022-06-17 乐金显示有限公司 光源单元和包括该光源单元的显示装置

Also Published As

Publication number Publication date
JP2015167257A (ja) 2015-09-24
JP2013138260A (ja) 2013-07-11
JP4629042B2 (ja) 2011-02-09
US20170084564A1 (en) 2017-03-23
US20080213996A1 (en) 2008-09-04
JP2010267996A (ja) 2010-11-25
US10249588B2 (en) 2019-04-02
US20190198472A1 (en) 2019-06-27
JP6078585B2 (ja) 2017-02-08
CN100492607C (zh) 2009-05-27
US8580679B2 (en) 2013-11-12
WO2005031848A1 (en) 2005-04-07
US9543261B2 (en) 2017-01-10
JP5284314B2 (ja) 2013-09-11
JP2007506284A (ja) 2007-03-15
US20220059484A1 (en) 2022-02-24
HK1093380A1 (en) 2007-03-02
US20050062169A1 (en) 2005-03-24
US7276801B2 (en) 2007-10-02
US11201129B2 (en) 2021-12-14
US20110084387A1 (en) 2011-04-14
TW200520192A (en) 2005-06-16
TWI251921B (en) 2006-03-21

Similar Documents

Publication Publication Date Title
CN100492607C (zh) 包括导电凸起的微电子器件及其制备方法
KR100213152B1 (ko) 솔더 터미널 및 그 제조방법
CN100578746C (zh) 允许使用高含锡量焊块的凸块下金属化层
US20030025173A1 (en) Semiconductor device and manufacturing method thereof
CN102347298A (zh) 基板上的凸块结构与其形成方法
US20070228567A1 (en) Semiconductor Chip Comprising A Metal Coating Structure And Associated Production Method
JPH02341A (ja) 半導体装置及びその製造方法
US8053894B2 (en) Surface treatment of metal interconnect lines
CN100508147C (zh) 电镀方法和接触凸起装置
CN1316581C (zh) 用于改良晶片可靠性的密封针脚结构
KR20000047626A (ko) 반도체 장치의 제조 방법
US20040051117A1 (en) Method of using materials based on Ruthenium and Iridium and their oxides, as a Cu diffusion barrier, and integrated circuits incorporating same
CN1913141A (zh) 半导体装置及其制造方法
CN1879208A (zh) 用于探针测试和布线接合的i/o位置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1093380

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1093380

Country of ref document: HK

CX01 Expiry of patent term

Granted publication date: 20090527

CX01 Expiry of patent term