CN100508147C - 电镀方法和接触凸起装置 - Google Patents

电镀方法和接触凸起装置 Download PDF

Info

Publication number
CN100508147C
CN100508147C CNB2004800352077A CN200480035207A CN100508147C CN 100508147 C CN100508147 C CN 100508147C CN B2004800352077 A CNB2004800352077 A CN B2004800352077A CN 200480035207 A CN200480035207 A CN 200480035207A CN 100508147 C CN100508147 C CN 100508147C
Authority
CN
China
Prior art keywords
layer
basic
titanium
contact projection
basalis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800352077A
Other languages
English (en)
Other versions
CN1886828A (zh
Inventor
J·赫尔内德
H·托尔维斯滕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1886828A publication Critical patent/CN1886828A/zh
Application granted granted Critical
Publication of CN100508147C publication Critical patent/CN100508147C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明尤其涉及用于电镀的方法，包括例如借助抗蚀剂(26)构造铜层(24)。置于所述铜层(24)下面的阻挡层(22)用于向没有铜层的区域提供电镀电流。本发明方法使形成高质量的焊接凸点成为可能。

Description

电镀方法和接触凸起装置
技术领域
本发明涉及一种用于电镀的方法以及一种接触凸起装置。
背景技术
所述衬底是例如具有一个金属化层或具有多个金属化层的半导体衬底。通常使用硅半导体衬底。所述金属化包含例如大于80个原子百分比的铝或大于80个原子百分比的铜。
导电基本层是例如用于增加机械粘附的粘附促进层和/或用于防止扩散的扩散阻挡层。作为实例，氮化钛层用作铜阻挡层。与接触凸起有关地，基本层和辅助层在术语中也被称为“凸点下金属化”(UBM)。
铜是非常价廉的、具有高电导率的材料。从而，铜层很适于在电镀期间提供电流。因此，铜是通常用作辅助层材料的材料。
掩模层是例如抗蚀剂层，其借助光刻法来构图。例如，由可焊接的材料制成的接触凸起被电镀在掩模开口中，该接触凸起在术语中也被称为“焊接凸点”。锡合金，例如尤其是锡铅合金或可与环境更兼容的锡银合金被用作焊接材料。
基本层、辅助层和掩模层优选施加到整个区域上方。基本层和辅助层通过例如溅射来施加。
在电镀期间，将要被涂敷的衬底浸入电解槽中并被连接作为阴极。由于由电压引起的电化学过程的原因，材料即所谓的阳离子从电解液淀积到衬底上。电解槽中可选的添加剂使得能够有针对性地影响淀积层的具体特性。
发明内容
本发明的目的是给出用于电镀的改进方法，其可尤其用于形成具有良好的机械特性和电特性的接触凸起。此外，本发明将给出具有良好的机械特性和电特性的接触凸起。
在根据本发明的方法的情况下，除了引言中提到的方法步骤之外，还执行以下步骤：
-使用掩模或抗蚀剂掩模构图辅助层，根据抗蚀剂掩模基本层没有被构图或没有被完全构图，
-在构图辅助层之后在抗蚀剂开口中电镀一层。
本发明基于以下考虑：一方面辅助层是快速电镀以及均匀层生长所需的。另一方面，淀积层下面的辅助层的残余物例如相对于侵蚀或相对于特定界面的形成来说通常是干扰性的。因此，在根据本发明的方法的情况下辅助层借助抗蚀剂开口下面的掩模来去除，所述掩模是限定电镀区无论如何都需要的。然而，在这种情况下，在抗蚀剂开口下面没有同时除去基本层。基本层同样是导电的，由此适于电镀期间的电流输送。
由于辅助层存在直到掩模开口为止并用于电流输送，因此基本层的较低载流能力并不是非常重要的。在与衬底表面相比比较小的电镀区中，载流能力随着淀积层厚度的增加而提高。作为实例，电镀区具有小于衬底表面的40％或小于衬底表面的20％的面积。
由于借助辅助层避免了限制，因此新的层顺序可以通过根据本发明的方法来电镀。由此可能特别形成具有良好的电特性，尤其是具有高电迁???移阻力，和具有高机械粘附的接触凸起。接触凸起尤其适于倒装芯片技术或适于芯片高速装配技术，其中使用导电粘合剂或使用导电漆通过焊接、微型焊接或者通过接合来同时形成多个连接。
在一个改进方案中，执行以下步骤：
-在初始阶段利用一种电流密度来电镀，
-在初始阶段之后的主阶段，利用与初始阶段期间的电流密度相比更高的电流密度来电镀。
该过程考虑了基本层的较低的载流能力，因为在初始阶段在比较低的电流密度的情况下，具有比基本层更大的电导率的层淀积在穿过辅助层的开口的底部。只有当该层具有例如对应于辅助层的厚度(例如更大的层厚度)的电导率时，也就是说利用另一材料再次“修理”了辅助层，电流密度才增加到高值以实现快速电镀。
在一个改进方案中，初始阶段的电流密度小于主阶段电流密度的50％。初始阶段长于5秒并短于5分钟。在一个改进方案中，随着时间的过去从初始阶段向主阶段的转变在电流均匀增加的情况下进行。在另一个改进方案中，电流密度按照阶梯顺序倍增，其间使用保持不变的电流密度。还进行这些电流密度函数与电流脉冲的叠加。
在一个改进方案中，主阶段的电流密度大于0.2安培每平方分米并小于10安培每平方分米(ASD)，例如0.5A/dm-2。所提到的电流密度值与晶片表面上被敞开的抗蚀剂面积有关。在另一个改进方案中，执行以下步骤：
-在施加基本层之前施加绝缘层，
-在施加基本层之前构图绝缘层并形成接触开口。
就接触凸起来说，绝缘层是例如钝化层，其包含例如氧化硅层和/或氮化硅层。接触开口位于掩模开口下面以便电镀。如果掩模开口被选择为比接触开口宽一点，则由于绝缘层用作腐蚀停止层，因此便于除去已预构图的辅助层和位于将要形成的装置外面的部分基本层的剩余物。
在下一个改进方案中，基本层是抵抗铜扩散的阻挡层。辅助层包含铜或者包括铜，由此特别适于馈送电镀电流。然而，在存在湿气的情况下铜也是特别侵蚀性的材料，因为混合氧化物特别容易产生，其也被称为碱性醋酸铜。所述混合氧化物显著降低了将要形成的装置中的各层的粘附。在集成电路装置的操作期间电流电导率也将由此显著降低。由于辅助层被完全除去了，尤其是在电淀积该层的区域中或在电淀积这些层的区域中，因此这些缺点没有显露出来，尤其是如果该装置也不含铜时。特别地，也不需要任何附加措施来封装含铜层并由此保护它们免受湿气。
在另一个改进方案中，执行以下步骤：
-电镀基底层，
-在电镀基底层之后电镀覆盖层，该基底层包括与该覆盖层不同的材料。
因此，在随后的回流过程或将要形成的装置的机械特性的改善期间淀积层堆叠，其允许将要获得的组合效应，例如特定化合物的形成。
在一个改进方案中，基底层的材料具有大于500摄氏度的熔点，由此对焊接有抵抗力。覆盖层的材料具有小于400摄氏度的熔点，由此是可焊接的。
本发明还涉及接触凸起装置，其也被称为焊接凸点。随着离集成电路的衬底的距离的增加，该焊接凸点按以下次序包含有：
-用于横向电流输送的导电互连或连接板，其也被称为连接衬垫并用作垂直电流输送，也就是说在与衬底主区域的法线的方向完全相反的方向上，
-导电基本层，尤其是粘附促进和阻挡层，
-邻近基本层的由具有大于500摄氏度的熔点的材料制成的无铜基底层，
-优选邻近基底层的具有小于400摄氏度的熔点的导电焊接材料层。
根据本发明的接触凸起装置可以通过根据本发明的方法或其改进方案之一来特别良好地形成。特别地，无铜接触凸起装置可以在电镀期间使用铜辅助层来形成。
在一个改进方案中，基底层包含至少60个原子百分比的镍。作为实例，基底层包括镍、镍磷或镍铬。镍与焊接材料例如边界层中的锡银一起形成三元化合物，边界层的厚度受到三元化合物形成期间的自调节的限制。因此用于限定边界层的厚度的附加措施不是必需的。边界层形成抵抗电迁移的有效阻挡，且另一方面使电阻仅增加到仍可接受的程度。例如作为金属间相的三元化合物形成一个复杂的空间点阵。
在一个改进方案中，互连或连接板包括至少80个原子百分比的铝。然而，作为替换，铜用作一种构成，并且其比例超过50个原子百分比。
在一个改进方案中，基本层形成铜的扩散阻挡，以便辅助层的铜不渗入互连中。在一个改进方案中，基本层由钛钨组成或包含钛钨，钛的比例优选小于20个原子百分比。该层的阻挡和粘附特性特别好。然而，其它材料也是适合的，例如钛、钽、氮化钛或氮化钽，并且这些材料的层组合也是可以的，例如由钛层、钛钨层和钛层构成的层序列。
如果基本层邻近互连，则没有其它层位于基本层和互连之间，因此接触凸起装置具有简单的结构。特别地，没有必须被保护以抵抗侵蚀的含铜层位于互连和基本层之间。
附图说明
下面参考附图来解释本发明，其中：
图1A～1C示出焊接凸点形成期间的形成阶段，以及
图2示出在淀积镍基底之后以及在淀积焊接材料之前焊接凸点的平面图。
具体实施方式
图1A～1C示出焊接凸点10形成期间的形成阶段。该方法从衬底12开始进行，该衬底12包含例如多个金属化层(未示出)和由硅制成的主体。这些金属化层在所有情况下都包含多个互连和通过金属化层内的层内电介质和通过相邻金属化层之间的层间电介质被绝缘的通孔。多个半导体部件例如存储电路或处理器的场效应晶体管形成在由硅制成的主体上。
如图1A所示，上铝层14施加到衬底12上并使用光刻法来构图，其中形成连接衬垫16。铝层14以及连接衬垫16具有例如在从500纳米到2微米的范围内的厚度，在示例性实施例中是500纳米。连接衬底16具有例如矩形或正方形的基本区域。在示例性实施例中，该基本区域是八边形的，六边形的两个对边之间的距离是大约80微米。铝层14仅包含少量小于5个原子百分比、例如0.5个原子百分比的硅添加物，并且如果适当的话是铜添加物，特别地是1个原子百分比。
在构图铝层14之后，淀积钝化层18。钝化层18具有例如在从500纳米到1微米的范围内的层厚度，在示例性实施例中是500纳米。钝化层18包含例如氧化物层和叠加的氮化物层。借助光刻法，在钝化层18中引入多个切口以用于焊接凸点，其中一个切口20在图1A中示出。切口20同样是例如八边形，但具有比连接衬垫16小的直径。在示例性实施例中，切口20的直径是大约60微米。
在形成切口20之后，钛钨阻挡层22施加到整个区域上方，所述阻挡层的层厚度处于例如从100纳米到200纳米的范围内。在示例性实施例中，阻挡层22具有100纳米的层厚度。阻挡层22包含例如大于80个原子百分比的钨。在示例性实施例中，钨的比例是90个原子百分比以及钛的比例是10个原子百分比。阻挡层22通过例如溅射来施加。
在施加阻挡层22之后，由纯铜制成的、例如具有大于98个原子百分比的铜比例的铜层24施加到整个区域上方。铜层24的厚度处于例如从80纳米到150纳米的范围内。在示例性实施例中，铜层24具有100纳米的厚度。作为实例，铜层24通过溅射来施加。
如图1A进一步所示，例如具有100微米的层厚度的抗蚀剂层26随后施加到铜层24上。曝光并显影抗蚀剂层26，在切口20上形成切口28。切口28同样是八边形的，但是具有比切口20大一点的直径。在示例性实施例中，切口28的直径是80微米。切口20和28保持彼此共中心。
如图1A中的虚线30进一步所示，在显影抗蚀剂层26之后，通过根据由抗蚀剂层26形成的掩模构图铜层24来除去切口28底部的铜。作为实例，实行湿法化学腐蚀，铜层32的钻蚀(undercut)32是非临界的，这将在下面更详细地解释。在另一个示例性实施例中，由于刻蚀优化的原因，切口保持很小并且总计小于2微米。
如图1B所示，随后电淀积镍基底50，铜层24决定性地用于运送切口28外面的电流。只有在切口28的底部处阻挡层20才决定性地用于馈送电流，尤其是在电镀开始时。作为实例，根据上述电镀方法，首先仅利用低电流密度比较慢地实行电镀。一旦镍基底50具有类似铜层24的层厚度，在示例性实施例中即100纳米的层厚度，那么就逐渐或逐步转换到更高的电流密度以便更快地电镀。镍基底50被淀积成例如具有2微米～5微米的层厚度。在示例性实施例中，镍基底的层厚度是3微米。
在淀积镍基底50期间，钻蚀32或这些空腔并没有引起干扰，因为该区域中的可能的淀积没有不利地影响接触凸起的功能性。
如图1B进一步示出的，随后电淀积焊接材料52，在开始时直接使用高电流密度。在示例性实施例中，焊接材料是被淀积成具有在50～120微米的范围内的层厚度的锡银焊料。在示例性实施例中，焊接材料52具有90微米的层厚度。
镍基底50和焊接材料52的电淀积是共形的。切口20的边缘54映射为镍基底50上的边缘56和焊接材料52上的边缘58。
图1C示出在淀积焊接材料52之后，再次除去抗蚀剂层26，以便暴露焊接凸点10。随后通过湿法化学或干法化学方法从阻挡层22除去铜层24的残余物。然后，如果适当的话借助相同的刻蚀方法，除去未被镍基底50覆盖的区域中的阻挡层22。在镍基底50和连接衬垫16之间产生了阻挡层区域22a。阻挡层区域22a伸出切口20之外并靠在切口22a附近、例如小于15微米附近的钝化层18上。相反，在进一步远离切口20的地方，阻挡层22被除去。
关于铜层24和阻挡层22的去除，对于铜层24和阻挡层22将最小可能的层厚度选择到极其大的程度，但是分别不损害它们实际的电流馈送功能和阻挡功能。
随后在回流步骤中将焊接凸点10瞬间加热到400摄氏度的温度，例如，焊接材料52重新成形为球形形式。尤其包含三元合金锡镍银的薄边界层形成在镍基底和焊接材料之间的边界70处。
图2示出在淀积镍基底50之后以及在淀积焊接材料52之前焊接凸点10的平面图。该平面图是最初摄影的，之前已经除去了抗蚀剂层26。邻近例如重新布线平面的互连80的八边形连接衬垫16可易于辨别。在钻蚀32的区域中钛钨阻挡层22是暴露的，其沿圆周方向具有高达10微米的宽度B1。
镍基底50被切口28定界，并具有80微米的直径D。镍基底50的边缘56也可易于辨别。
总之适用的是，特别借助于湿法化学或电镀回蚀(etching-back)(其也被称为除去镀层)在接触窗口中选择性地除去辅助层、尤其是铜层。在电镀回蚀期间，衬底被连接作为从其除去材料的阳极。随后通过电化学淀积例如镍淀积再次形成再处理的(worked-back)区域。因此，特别地无铜界面存在于焊接凸点下面。导致下列技术效应：
-严重干扰例如铜和锡的金属相形成不再发生，
-在抗蚀剂去除之后，由此可能在某种情况下，在单个刻蚀步骤中除去UBM(凸点下金属化)。该刻蚀被优化用于除去阻挡，例如钛或钛钨。辅助层和阻挡层优选在相同的刻蚀腔室中尤其借助于相同的腐蚀化学或腐蚀化学成分来去除。
-焊接凸点的钻蚀被最小化。
-为了利用接触窗口除去辅助层，还可以使用与掩模开口内的淀积情况相同的电镀装置，并且同时不从该装置拿掉衬底，
-直接在阻挡层上的电镀，例如镍电镀变得可能。
优选的应用领域是射频电路和具有超过100个连接的外壳，其根据倒装芯片技术来安装。在电化学淀积焊球或焊接凸点之前，例如钛层或钛钨层的金属阻挡以及例如铜层的辅助层被施加作为晶片上的整个区域电极。这两层可被认为是UBM(凸点下金属化)并例如通过磁控管溅射或电子束蒸发来施加。
阻挡层防止焊接材料的金属相互扩散进入晶片上的互连中。辅助层用作用于电镀工艺的载流接触形成层。
在光刻之后，已打开的抗蚀剂接触窗口准备用于填满凸点金属化。电镀工艺开始于变湿或预变湿步骤以便利用电解液均匀地弄湿接触。打算生长的第一金属层是镍，例如具有2～5微米的厚度或具有在5微米到100微米的范围内的厚度、尤其是具有大于40微米的厚度的所谓的接线柱(stud)。随后淀积厚度高达50微米或高达150微米的焊料金属化。
在抗蚀剂去除之后，必须再次除去阻挡层和辅助层。这里采用湿法化学法。在湿法腐蚀的过程中，不会产生由于上述过程而引起的不希望有的钻蚀和侵蚀，因此焊球仍很好地粘附在晶片表面。
特别地，在由铜制成的辅助层的情况下，避免了铜以及锡的严重金属间相的形成和相关的铜在锡银焊料中的完全溶解以及细孔在阻挡界面处的形成。有效防止了凸点脱落和系统失效。

Claims (20)

1.一种用于电镀的方法，具有以下步骤：
将导电基本层(22)施加到衬底(12)，
在施加基本层(22)之后施加与该基本层(22)相比具有更好的电导率的辅助层(24)，
在施加辅助层(24)之后施加掩模层(26)，
由掩模层(26)形成具有至少一个掩模开口(28)的掩模，
使用该掩模构图辅助层(24)，基本层(22)由于该掩模而没有被构图或没有被完全构图，
在构图辅助层(24)之后在掩模开口(28)中对层(50、52)进行电镀，
即：
电镀基底层(50)，
在电镀基底层(50)之后电镀覆盖层(52)，该基底层(50)包含的材料具有高于覆盖层(52)材料的熔点，
所述基本层(22)由钛、钽、氮化钛、氮化钽、钛钨、氮化钛钨组成或是这些材料的层组合，
所述辅助层(24)包含铜，
所述基底层(50)与基本层(22)相邻。
2.如权利要求1所述的方法，其特征在于以下步骤：
在利用低电流密度缓慢实行电镀的初始阶段利用一种电流密度来电镀，
在初始阶段之后的主阶段，利用与初始阶段期间的电流密度相比更高的电流密度来电镀。
3.如权利要求2所述的方法，其特征在于初始阶段的电流密度具有小于主阶段电流密度的50％的值。
4.如权利要求2所述的方法，其特征在于初始阶段长于5秒和/或短于5分钟。
5.如权利要求2所述的方法，其特征在于主阶段的电流密度大于0.2安培每平方分米和/或小于10安培每平方分米。
6.如权利要求1或2所述的方法，其特征在于以下步骤：
在施加基本层(22)之前施加绝缘层(18)，
在施加基本层(22)之前构图绝缘层(18)并形成接触开口(20)，
并且在接触开口(20)中施加部分基本层(22)。
7.如权利要求1或2所述的方法，其特征在于基本层(22)是抵抗铜扩散的阻挡层。
8.如权利要求7所述的方法，其特征在于基底层(50)的材料具有大于500摄氏度的熔点，
以及覆盖层(52)的材料具有小于400摄氏度的熔点。
9.如权利要求1或2所述的方法，其特征在于构图辅助层通过电镀法在与在掩模开口(28)中电镀所述基底层和覆盖层(50、52)相同的装置中进行。
10.一种接触凸起装置(10)，其随着离集成电路的衬底(12)的距离的增加而按以下次序包含：
导电互连(16)或连接板，
导电基本层(22)，
邻近基本层(22)的由具有大于500摄氏度的熔点的材料制成的无铜基底层(50)，
具有小于400摄氏度的熔点的导电焊接材料层(52)，
基底层(50)由镍或镍磷组成，或包含至少60个原子百分比的镍，
基本层(22)形成铜的扩散阻挡层，
所述基本层(22)由钛、钽、氮化钛、氮化钽、钛钨、氮化钛钨组成或者是这些材料的层组合，
以及基本层(22)邻近互连(16)或连接板。
11.如权利要求10所述的接触凸起装置(10)，其特征在于由多相化合物制成的边界层存在于基底层(50)和焊接材料层(52)之间的边界处。
12.如权利要求11所述的接触凸起装置(10)，其特征在于，所述多相化合物是由二元化合物或三元化合物制成的。
13.如权利要求10-12中的一个所述的接触凸起装置(10)，其特征在于互连(16)或连接板包含至少80个原子百分比的铝。
14.如权利要求10-12中的一个所述的接触凸起装置(10)，其特征在于互连(16)或连接板包含大于50个原子百分比的铜。
15.如权利要求10-12中的一个所述的接触凸起装置(10)，其特征在于焊接材料层(52)包括锡合金。
16.如权利要求15所述的接触凸起装置(10)，其特征在于，所述锡合金是锡银合金或锡铅合金或锡银铜合金或锡银铋合金。
17.如权利要求10-12中的一个所述的接触凸起装置(10)，其特征在于基本层包括由多个部件层构成的层堆叠，该层堆叠包括下述层中的至少一层：钛层、钽层、氮化钛层、氮化钽层、钨层、钛钨层或氮化钛钨层。
18.如权利要求10或11所述的接触凸起装置(10)，其特征在于当基本层(22)包括钛钨或由钛钨组成时，钛的比例小于20个原子百分比。
19.如权利要求10或11所述的接触凸起装置(10)，其特征在于基底层(50)邻近焊接材料层(52)。
20.如权利要求10或11所述的接触凸起装置(10)，其特征在于在互连(16)或连接板与导电的基本层(22)之间包含具有切口(20)的电绝缘层(18)，在该切口中设置了至少一部分基本层(22)和一部分基底层(50)。
CNB2004800352077A 2003-11-29 2004-11-17 电镀方法和接触凸起装置 Expired - Fee Related CN100508147C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10355953.1 2003-11-29
DE10355953A DE10355953B4 (de) 2003-11-29 2003-11-29 Verfahren zum Galvanisieren und Kontaktvorsprungsanordnung

Publications (2)

Publication Number Publication Date
CN1886828A CN1886828A (zh) 2006-12-27
CN100508147C true CN100508147C (zh) 2009-07-01

Family

ID=34625424

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800352077A Expired - Fee Related CN100508147C (zh) 2003-11-29 2004-11-17 电镀方法和接触凸起装置

Country Status (5)

Country Link
US (1) US20070246133A1 (zh)
EP (1) EP1687846A1 (zh)
CN (1) CN100508147C (zh)
DE (1) DE10355953B4 (zh)
WO (1) WO2005053012A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4718305B2 (ja) * 2005-11-09 2011-07-06 新光電気工業株式会社 配線基板の製造方法および半導体装置の製造方法
US7456090B2 (en) * 2006-12-29 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce UBM undercut
DE102007031958A1 (de) * 2007-07-10 2009-01-15 Deutsche Cell Gmbh Kontakt-Struktur für ein Halbleiter-Bauelement sowie Verfahren zur Herstellung desselben
JP5627835B2 (ja) * 2007-11-16 2014-11-19 ローム株式会社 半導体装置および半導体装置の製造方法
DE102008014577B3 (de) * 2008-03-14 2009-07-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer Lotmetallisierung
US8080973B2 (en) 2008-10-22 2011-12-20 General Electric Company Apparatus for energy transfer using converter and method of manufacturing same
US8476760B2 (en) * 2010-11-03 2013-07-02 Texas Instruments Incorporated Electroplated posts with reduced topography and stress
US9553040B2 (en) * 2012-03-27 2017-01-24 Mediatek Inc. Semiconductor package
DE102016103585B4 (de) 2016-02-29 2022-01-13 Infineon Technologies Ag Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
CN110444479B (zh) * 2019-07-22 2022-02-01 厦门通富微电子有限公司 一种金属凸点的制造方法和芯片

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105653A (en) * 1980-01-28 1981-08-22 Seiko Instr & Electronics Ltd Gold bump forming method of semiconductor device
GB2095904B (en) * 1981-03-23 1985-11-27 Gen Electric Semiconductor device with built-up low resistance contact and laterally conducting second contact
JPH02224336A (ja) * 1989-02-27 1990-09-06 Nec Corp 半導体装置の製造方法
US5160409A (en) * 1991-08-05 1992-11-03 Motorola, Inc. Solder plate reflow method for forming a solder bump on a circuit trace intersection
US5264107A (en) * 1991-12-17 1993-11-23 At&T Bell Laboratories Pseudo-electroless, followed by electroless, metallization of nickel on metallic wires, as for semiconductor chip-to-chip interconnections
KR100319813B1 (ko) * 2000-01-03 2002-01-09 윤종용 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6316831B1 (en) * 2000-05-05 2001-11-13 Aptos Corporation Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties
TW517334B (en) * 2000-12-08 2003-01-11 Nec Corp Method of forming barrier layers for solder bumps
JP4000796B2 (ja) * 2001-08-08 2007-10-31 株式会社豊田自動織機 ビアホールの銅メッキ方法
US20050000821A1 (en) * 2001-11-16 2005-01-06 White Tamara L Anodes for electroplating operations, and methods of forming materials over semiconductor substrates
US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ｕｂｍ의형성방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device

Also Published As

Publication number Publication date
EP1687846A1 (de) 2006-08-09
DE10355953A1 (de) 2005-07-07
CN1886828A (zh) 2006-12-27
US20070246133A1 (en) 2007-10-25
WO2005053012A1 (de) 2005-06-09
DE10355953B4 (de) 2005-10-20

Similar Documents

Publication Publication Date Title
US7456501B1 (en) Semiconductor structure having recess with conductive metal
USRE40983E1 (en) Method to plate C4 to copper stud
CN100492607C (zh) 包括导电凸起的微电子器件及其制备方法
US9324669B2 (en) Use of electrolytic plating to control solder wetting
US7382051B2 (en) Semiconductor device with reduced contact resistance
CN100508147C (zh) 电镀方法和接触凸起装置
US11581279B2 (en) Semiconductor device
CN1315158C (zh) 选择性电镀半导体器件的输入/输出焊盘的方法
US20080017987A1 (en) Semiconductor device with reduced contact resistance
US6362100B1 (en) Methods and apparatus for forming a copper interconnect
US6589816B2 (en) Method of forming metal connection elements in integrated circuits
US5264107A (en) Pseudo-electroless, followed by electroless, metallization of nickel on metallic wires, as for semiconductor chip-to-chip interconnections
JP2000031145A (ja) 半導体装置の製造方法
KR100702805B1 (ko) 반도체 소자의 금속 배선 형성 방법
CN114496909A (zh) 重布线结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090701

Termination date: 20181117