Classifications

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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
  • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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  • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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  • H01L2924/04941—TiN
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  • H01L2924/1904—Component type
  • H01L2924/19043—Component type being a resistor

Definitions

• the invention relates to a method for electroplating, in which the following steps are carried out:
• auxiliary layer e.g. a resist layer
• the substrate is, for example, a semiconductor substrate with one metallization layer or with several metallization layers. Silicon semiconductor substrates are often used.
• the metallization contains, for example, more than eighty atomic percent aluminum or more than eighty atomic percent copper.
• the electrically conductive base layer is, for example, an adhesion- promoting layer to increase mechanical adhesion and / or a diffusion barrier layer to prevent diffusion.
• an adhesion- promoting layer to increase mechanical adhesion and / or a diffusion barrier layer to prevent diffusion.
• titanium nitride layers are used as copper barrier layers.
• the base layer and auxiliary layer are also referred to in technical terms as "Under Bump Metallization" (UBM).
• Copper is a very inexpensive material with a high electrical conductivity. A copper layer is therefore well suited for bringing up the current during electroplating. That is why copper is a material that is often used as a material for the auxiliary layer.
• the mask layer is, for example, a resist layer that is structured using a photolithographic process.
• a contact projection made of a solderable material is galvanically deposited, which is also referred to in technical terms as a "solder bump".
• solder bump tin alloys are used as the soldering material, in particular tin-lead alloys or more environmentally friendly tin-silver alloys.
• the base layer, the auxiliary layer and the mask layer are preferably applied over the entire surface.
• the base layer and the auxiliary layer are sputtered on, for example.
• the substrate to be coated is immersed in an electrolyte bath and switched as a cathode. Due to the electrochemical processes caused by the voltage, material - the so-called cations - is deposited on the substrate from the electrolyte. Optional additives in the electrolyte bath enable specific properties of the deposited layer to be influenced.
• a contact projection should be specified that has good mechanical and electrical properties.
• the invention is based on the consideration that the auxiliary layer is required on the one hand for rapid electroplating with homogeneous layer growth.
• residues of the auxiliary layer under the deposited layer are often troublesome, for example with regard to corrosion or with regard to the formation of certain interfaces.
• the auxiliary layer is therefore removed with a mask, which is anyway necessary for defining the galvanization area, below a resist opening.
• the base layer below the resist opening is not removed.
• the base layer is also electrically conductive and is therefore suitable for transporting electricity during electroplating.
• the lower current carrying capacity of the base layer is not so important, since the auxiliary layer is available right up to the mask opening and is used to transport electricity.
• the current carrying capacity increases with increasing thickness of the deposited layer.
• the electroplating area has an area of less than 40 percent or less than 20 percent of the substrate surface.
• new layers can be galvanically deposited, because restrictions are avoided by the auxiliary layer.
• contact protrusions with good electrical properties, in particular with high resistance to electrical migration and with high mechanical adhesion, can be produced in this way. len.
• the contact projections are particularly suitable for the flip-chip technology or for the quick-mounting wafer technology, in which a large number of connections are produced simultaneously by soldering, by micro-welding or by gluing with conductive adhesive or with conductive lacquer.
• the lower Stromtragfä- is ability of the base layer into account, because in the on ⁇ initial phase with a relatively low power density, a layer having a higher electrical conductivity than the base layer at the bottom of the auxiliary layer penetrating openings is deposited. Only when this layer has, for example, a conductivity corresponding to the thickness of the auxiliary layer (for example greater layer thickness), ie the auxiliary layer has been "repaired" with another material, is the current density increased to the high value in order to galvanize quickly.
• the current density in the initial phase is less than 50 percent of the current density in the main phase.
• the initial phase is longer than five seconds and less than five minutes. The transition from the initial phase to the main phase takes place in the case of a configuration with a uniform current increase over time.
• the current density is increased several times in accordance with a step sequence, current densities which remain the same in the meantime being used. These current density functions are also overlaid with current pulses.
• the current density in the main phase is greater than 0.2 amperes per square decimeter and less than 10 amperes per square decimeter (ASD ampere per square decimeter), for example at 0.5 A / crrf 2 .
• the current density values mentioned relate to the open resist area on the wafer surface.
• the insulating layer is, for example, a passivation layer which contains, for example, a silicon oxide layer and / or a silicon nitride layer.
• the contact opening is below the mask opening for electroplating. If the mask opening is chosen to be somewhat wider than the contact opening, the removal of the residues of the already pre-structured auxiliary layer and of the parts of the base layer lying outside the arrangement to be produced is facilitated, since the insulating layer is used as an etching stop layer.
• the base layer is a barrier layer against copper diffusion.
• the auxiliary layer contains copper or consists of copper and is therefore particularly well suited for supplying the galvanizing current.
• copper is also a material that is particularly corrosive when exposed to moisture, since mixed oxides, which are also referred to as verdigris, are particularly easy to form. These mixed oxides considerably reduce the adhesion of the layers in the arrangement to be produced. Also, the current conductivity during loading ⁇ drive the integrated circuit arrangement would thus be substantially reduced. Since the auxiliary layer is completely removed, in particular in the area in which the layer is electrodeposited or in which the layers are electrodeposited, these disadvantages do not come into play, in particular if the arrangement is also in the The rest is copper free. In particular, no additional measures are required to encapsulate copper-containing layers and thus protect them from moisture.
• a layer stack is thus deposited which allows combination effects to be achieved, for example the formation of certain connections in a subsequent reflow process or the improvement of mechanical properties of the arrangement to be produced.
• the material of the base layer has a melting point greater than 500 degrees Celsius and is therefore resistant to soldering.
• the material of the cover layer has a melting point of less than 400 degrees Celsius and is therefore solderable.
• the invention also relates to a contact projection arrangement which is also referred to as a solder bump.
• the solder bump contains in the following order with increasing distance from a substrate of an integrated circuit: an electrically conductive interconnect for lateral current transport or a connection plate, which is also referred to as a connection pad and is used for vertical current transport, i.e. in a direction exactly opposite to a normal direction of a main substrate surface, an electrically conductive base layer, in particular an adhesion-promoting and barrier layer,
• a copper-free base layer made of a material with a melting temperature greater than 500 degrees Celsius, - preferably adjacent to the base layer, an electrically conductive solder material layer with a melting point less than 400 degrees Celsius.
• the contact projection arrangement according to the invention can be produced particularly well using the method according to the invention or one of its developments.
• a copper-free contact protrusion arrangement can be produced using a copper auxiliary layer during the electroplating.
• the base layer contains at least 60 atomic percent nickel.
• the base layer consists of nickel, nickel phosphorus or nickel chrome.
• Nickel forms with the solder material, e.g. the tin-silver in a boundary layer has a ternary or triple connection, the thickness of the boundary layer being limited by self-regulation when the ternary connections are formed. Additional measures to determine the thickness of the boundary layer are therefore not necessary.
• the boundary layer forms an effective barrier against electromigration and, on the other hand, only increases the electrical resistance to an acceptable level.
• the ternary connections for example, build up a complicated space lattice as intermetallic phases.
• the interconnect or the connecting plate consists of at least 80 atomic percent aluminum.
• copper is used as a component, the proportion of which is more than 50 atomic percent.
• the base layer forms a diffusion barrier for copper, so that the copper of the auxiliary layer does not penetrate the interconnect.
• the base layer consists of titanium tungsten or contains titanium tungsten, the titanium content preferably being less than 20 atomic percent. The barrier and adhesive properties of this layer are particularly good.
• other materials are also suitable, such as titanium, tantalum, titanium nitride or tantalum nitride, and layer combinations of these materials are also possible, for example a layer sequence composed of a titanium layer, a titanium tungsten layer and a titanium layer. If the base layer borders on the interconnect, there are no further layers between the base layer and the interconnect, so that the contact projection arrangement has a simple structure. In particular, there is no copper-containing layer between the interconnect and the base layer, which should be protected against corrosion.
• Figures 1A to 1B manufacturing stages in the manufacture of a solder bump
• Figure 2 is a plan view of the solder bump after the deposition of a nickel base and before the deposition of solder material.
• Figures 1A to 1B show manufacturing stages in the manufacture of a solder bump 10.
• the process starts from a substrate 12, e.g. contains several metallization layers, not shown, and a main body made of silicon.
• the metallization layers each contain a multiplicity of interconnects and vias, which are insulated within an metallization layer by an intralayer dielectric and between adjacent metallization layers by an inter-layer dielectric.
• a variety of semiconductor devices are formed on the silicon main body, e.g. Field effect transistors of a memory circuit or a processor.
• an upper aluminum layer 14 is applied to the substrate 12 and structured using a photolithographic method, a connection pad 16 being produced.
• the aluminum layer 14 and also the connection pad 16 have, for example, a thickness in the range from 500 nanometers to two micrometers, in the exemplary embodiment of 500 nanometers.
• the connection pad 16 has, for example, a rectangular or square base area. In the exemplary embodiment, the base area is octagonal, with the distance between two opposite sides of the hexagon is about 80 microns.
• the aluminum layer 14 contains only minor additions smaller than 5 atom percent, for example 0.5 atom percent silicon, and possibly a copper addition, for example 1 atom percent.
• a passivation layer 18 is deposited.
• the passivation layer 18 has, for example, a layer thickness in the range from 500 nanometers to one micrometer, in the exemplary embodiment of 500 nanometers.
• the passivation layer 18 contains, for example, an oxide layer and an overlying nitride layer.
• a large number of recesses are made in the passivation layer 18 for solder bumps, a recess 20 of which is shown in FIG. 1A.
• the recess 20 is, for example, also octagonal, but has a smaller diameter than the connection pad 16. In the exemplary embodiment, the diameter of the recess 20 is approximately 60 micrometers.
• a titanium-tungsten barrier layer 22 is applied over the entire surface, the layer is thick ⁇ for example. In the range of 100 nanometers to 200 nanometers. In the exemplary embodiment, the barrier layer 22 has a layer thickness of 100 nanometers.
• the barrier layer 22 contains, for example, more than 80 atomic percent tungsten. In the exemplary embodiment, the proportion of tungsten is 90 atomic percent and the proportion of titanium is 10 atomic percent.
• the barrier layer 22 is sputtered on, for example.
• a copper layer 24 made of pure copper is applied over the entire surface, for example with a copper content greater than 98 atomic percent.
• the thickness of the copper layer 24 is, for example, in the range from 80 nanometers to 150 nanometers. In the exemplary embodiment, the copper layer 24 has a thickness of 100 nanometers.
• the copper layer 24 is sputtered on.
• a resist layer 26 is subsequently applied to the copper layer 24, for example with a layer thickness of 100 micrometers.
• the resist layer 26 is exposed and developed, wherein above the Ausspa ⁇ tion 20 a recess 28 is formed.
• the recess 28 is also octagonal, but has a slightly larger diameter than the recess 20.
• the diameter of the recess 28 is 80 micrometers in the exemplary embodiment.
• the recesses 20 and 28 are concentric with one another.
• the copper on the bottom of the recess 28 is removed by structuring the copper layer 24 in accordance with the mask formed by the resist layer 26. For example, it is etched using wet chemistry, with undercuts 32 of the copper layer 32 being uncritical, as will be explained in more detail below. In another embodiment, the undercuts are kept low due to an optimization of the etching and are less than 2 micrometers.
• a nickel base 50 is then electrodeposited, with the copper layer 24 serving primarily for current carrying outside the recess 28. Only at the bottom of the recess 28 is the barrier layer 20 primarily used for power supply, in particular at the beginning of the galvanizing. For example. According to the above-mentioned electroplating process, electroplating is initially carried out comparatively slowly with a low current density. If the nickel base 50 then has a layer thickness like the copper layer 24, that is to say in the exemplary embodiment a layer thickness of 100 nanometers, then a switch is made gradually or stepwise to a higher current density for faster electroplating. The nickel base 50 is deposited, for example, with a layer thickness of two micrometers to five micrometers. In the execution The layer thickness of the nickel base is three micrometers.
• the undercuts 32 or these cavities do not interfere, because any deposits in this area have no negative effects on the functionality of the contact projection.
• solder material 52 is subsequently electrodeposited, a high current density being used right at the start.
• the solder material is a tin-silver alloy, which is deposited with a layer thickness in the range from 50 to 120 micrometers.
• the solder material 52 has a layer thickness of 90 micrometers.
• the galvanic deposits of the nickel base 50 and the solder material 52 are compliant.
• An edge 54 of the recess 20 is shown as an edge 56 on the nickel base 50 and as an edge 58 on the solder material 52.
• FIG. IC shows that after the solder material 52 has been deposited, the resist layer 26 is removed again, so that the solder bump 10 is exposed.
• the residues of the copper layer 24 are then removed from the barrier layer 22 by wet chemical or dry chemical means.
• the barrier layer 22 in areas is removed, which are not covered by the nickel base 50th
• a barrier layer region 22a is formed between the nickel base 50 and the connection pad 16.
• the barrier layer region 22a projects beyond the cutout 20 and lies on the passivation layer 18 in the vicinity of the cutout 22a, for example in a neighborhood smaller than 15 micrometers.
• the barrier layer 22 was removed further away from the cutout 20.
• the smallest possible layer thicknesses are chosen for the copper layer 24 and for the barrier layer 22, without, however, impairing their actual power supply function or barrier function too much.
• solder bump 10 is then briefly heated to a temperature of, for example, 400 degrees Celsius in a reflow step, the solder material 52 forming a spherical shape.
• a thin boundary layer forms, which contains the ternary alloy tin-nickel-silver.
• FIG. 2 shows a top view of the solder bump 10 after the deposition of the nickel base 50 and before the deposition of the solder material 52.
• the top view was originally photographed, the resist layer 26 having been removed beforehand.
• the titanium tungsten barrier layer 22 is exposed in the area of the undercuts 32, which for example have a width B1 of up to 10 micrometers in the circumferential direction.
• the nickel base 50 is delimited by the recess 28 and has a diameter D of 80 micrometers.
• the edge 56 of the nickel base 50 is also clearly visible.
• the auxiliary layer in particular the copper layer, is selectively removed in the contact windows, in particular by wet chemical or galvanic etching back, which is also referred to as deplating.
• galvanic etching back the substrate is switched as an anode, from which material is removed.
• the reworked area is then rebuilt by an electrochemical deposition, for example a nickel deposition.
• electrochemical deposition for example a nickel deposition.
• This etching is optimized for removing the barrier, for example titanium or titanium tungsten.
• the auxiliary layer and the barrier layer are preferably removed in the same etching chamber, in particular with the same etching chemical or etching chemical composition. - The undercut of the solder bump is minimized.
• the same electroplating system can also be used as for the deposition within the mask opening without the substrate being removed from the system in the meantime, - a plating, for example a nickel plating, is possible directly on the barrier layer,
• a preferred field of application is high-frequency circuits and housings with more than 100 connections, which are mounted according to the flip-chip technology.
• a metal barrier e.g. a titanium layer or a titanium tungsten layer
• an auxiliary layer e.g. a copper layer.
• UBM Under Bump Metallization
• the barrier layer prevents metallic interdiffusion from the solder material into the interconnects on the wafer.
• the auxiliary layer serves as a current-carrying contact layer for the electroplating process.
• the electroplating process begins with a wetting or prewetting step to evenly wet the contacts with the Electrolyte.
• Nickel for example, should grow as the first metal layer, for example a so-called stud with a thickness of 2 to 5 micrometers or with a thickness in the range from 5 micrometers to 100 micrometers, in particular with a thickness greater than 40 micrometers.
• the solder metallization is then deposited with thicknesses of up to 50 micrometers or up to 150 micrometers.
• the barrier layer and the auxiliary layer must be removed again.
• wet chemical processes are used. With wet etching, the described procedure does not result in any undesirable undercuts or corrosion, so that the solder ball continues to adhere well to the wafer surface.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Electroplating Methods And Accessories (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Manufacturing Of Printed Wiring (AREA)

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• 2003
  • 2003-11-29 DE DE10355953A patent/DE10355953B4/de not_active Expired - Fee Related
• 2004
  • 2004-11-17 EP EP04819243A patent/EP1687846A1/de not_active Withdrawn
  • 2004-11-17 CN CNB2004800352077A patent/CN100508147C/zh not_active Expired - Fee Related
  • 2004-11-17 US US10/580,740 patent/US20070246133A1/en not_active Abandoned
  • 2004-11-17 WO PCT/EP2004/052999 patent/WO2005053012A1/de active Application Filing

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