US20070246133A1 - Method for Electroplating and Contact Projection Arrangement - Google Patents

Method for Electroplating and Contact Projection Arrangement Download PDF

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US20070246133A1
US20070246133A1 US10/580,740 US58074004A US2007246133A1 US 20070246133 A1 US20070246133 A1 US 20070246133A1 US 58074004 A US58074004 A US 58074004A US 2007246133 A1 US2007246133 A1 US 2007246133A1
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layer
base layer
current density
mask
applying
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Johann Helneder
Holger Torwesten
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • the invention relates to a method of electroplating.
  • the invention relates to a method of electroplating for a contact projection.
  • Copper is a very inexpensive material having a high electrical conductivity. Consequently, a copper layer is well suited to supplying the current during electroplating. Therefore, copper is a material that is often used as a material for the auxiliary layer.
  • the mask layer is e.g. a resist layer which is patterned by means of a photolithographic method.
  • a contact projection made of a solderable material which is also referred to in the jargon as “soldering bump”, is electrodeposited in the mask opening.
  • Tin alloys for example, in particular tin-lead alloys or more environmentally compatible tin-silver alloys, are used as soldering material.
  • the basic layer, the auxiliary layer and the mask layer are preferably applied over the whole area.
  • the basic layer and the auxiliary layer are applied by sputtering, for example.
  • the substrate to be coated is dipped into an electrolyte bath and connected as cathode.
  • material the so-called cations—deposits from the electrolyte on the substrate.
  • Optional additives in the electrolyte bath enable specific properties of the deposited layer to be influenced in a targeted manner.
  • the invention relates to a method for electroplating in which the following steps are performed:
  • auxiliary layer e.g. a resist layer
  • the substrate is for example a semiconductor substrate with one metallization layer or with a plurality of metallization layers. Silicon semiconductor substrates are often used.
  • the metallization contains for example more than eighty atomic percent of aluminum or more than eighty atomic percent of copper.
  • the electrically conductive basic layer is e.g. an adhesion promoting layer for increasing the mechanical adhesion and/or a diffusion barrier layer for preventing diffusion.
  • an adhesion promoting layer for increasing the mechanical adhesion and/or a diffusion barrier layer for preventing diffusion.
  • titanium nitride layers are used as copper barrier layers.
  • the basic layer and auxiliary layer are also referred to in the jargon as “under bump metallization” (UBM).
  • the invention is based on the consideration that the auxiliary layer is on the one hand required for rapid electroplating with homogeneous layer growth.
  • residues of the auxiliary layer below the deposited layer are often disturbing, for example with regard to corrosion or with regard to the formation of specific interfaces. Therefore, the auxiliary layer is removed in the case of the method according to the invention by means of a mask beneath a resist opening, said mask being required anyway for the definition of the electroplating zone.
  • the basic layer is not concomitantly removed beneath the resist opening.
  • the basic layer is likewise electrically conductive and thus suitable for current transport during electroplating.
  • the lower current-carrying capacity of the basic layer is not of very great consequence since the auxiliary layer is present as far as the mask opening and is used for current transport.
  • the current-carrying capacity is increased as the thickness of the deposited layer increases.
  • the electroplating zone has an area of less than 40 percent or less than 20 percent of the substrate surface.
  • New layer sequences can be electrodeposited by the method according to the invention because restrictions are circumvented by the auxiliary layer. It is thus possible to produce in particular contact projections having good electrical properties, in particular having high resistance to electromigration, and having a high mechanical adhesion.
  • the contact projections are suitable in particular for the flip-chip technique or for the chip high-speed mounting technique, in which a multiplicity of connections are produced simultaneously by soldering, by microwelding or by bonding using conductive adhesive or using conductive varnish.
  • This procedure takes account of the lower current-carrying capacity of the basic layer because in the initial phase with a comparatively low current density a layer having a greater electrical conductivity than the basic layer is deposited at the bottom of the openings penetrating through the auxiliary layer. Only when this layer has for example a conductivity corresponding to the thickness of the auxiliary layer (e.g. greater layer thickness), that is to say the auxiliary layer has been “repaired” again with another material, is the current density increased to the high value in order to effect electroplating rapidly.
  • a conductivity corresponding to the thickness of the auxiliary layer e.g. greater layer thickness
  • the current density in the initial phase is less than 50 percent of the current density in the main phase.
  • the initial phase is longer than 5 seconds and shorter than 5 minutes.
  • the transition from the initial phase to the main phase takes place with a uniform rise in current over time.
  • the current density is increased multiply in accordance with a stepped sequence, current densities that remain the same in the meantime being used. A superposition of these current density functions with current pulses is also carried out.
  • the current density in the main phase is greater than 0.2 ampere per square decimeter and less than 10 ampere per square decimeter (ASD), e.g. 0.5 A/cm-2.
  • the current density values mentioned relate to the opened resist area on the wafer surface.
  • the insulating layer is for example a passivation layer which contains for example a silicon oxide layer and/or a silicon nitride layer.
  • the contact opening lies below the mask opening for the electroplating. If the mask opening is chosen to be somewhat wider than the contact opening, then the removal of the residues of the already prepatterned auxiliary layer and of the parts of the basic layer which lie outside the arrangement to be produced is facilitated since the insulating layer is used as an etching stop layer.
  • the basic layer is a barrier layer against copper diffusion.
  • the auxiliary layer contains copper or comprises copper and is thus particularly well suited to feeding the electroplating current.
  • copper is also a material which is particularly corrosive in the presence of moisture, since mixed oxides arise particularly readily, which are also referred to as verdigris. Said mixed oxides considerably reduce the adhesion of the layers in the arrangement to be produced. The current conductivity during operation of the integrated circuit arrangement would thus also be considerably reduced. Since the auxiliary layer is completely removed, in particular in the region in which the layer is electrodeposited or in which the layers are electrodeposited, these disadvantages are not manifested, particularly if the arrangement is also moreover free of copper. In particular, there is also no need for any additional measures for encapsulating copper-containing layers and thus protecting them from moisture.
  • the electroplating of a covering layer after the electroplating of the base layer, the base layer comprising a different material than the covering layer.
  • a layer stack is deposited which permits combination effects to be obtained, for example the formation of specific compounds during a subsequent reflow process or the improvement of mechanical properties of the arrangement to be produced.
  • the material of the base layer has a melting point of greater than 500 degrees Celsius and is thus resistant to soldering.
  • the material of the covering layer has a melting point of less than 400 degrees Celsius and is thus solderable.
  • the invention additionally relates to a contact projection arrangement, which is also referred to as a soldering bump.
  • the soldering bump contains in the following order with increasing distance from a substrate of an integrated circuit:
  • connection pad an electrically conductive interconnect for lateral current transport or a connection plate, which is also referred to as a connection pad and serves for vertical current transport, that is to say in a direction exactly opposite to a direction of the normal to a substrate main area
  • an electrically conductive basic layer in particular an adhesion promoting and barrier layer
  • a copper-free base layer made of a material having a melting point of greater than 500 degrees Celsius
  • an electrically conductive solder material layer having a melting point of less than 400 degrees Celsius.
  • the contact projection arrangement according to the invention can be produced particularly well by means of the method according to the invention or one of its developments.
  • a copper-free contact projection arrangement can be produced using a copper auxiliary layer during electroplating.
  • the base layer contains at least 60 atomic percent of nickel.
  • the base layer comprises nickel, nickel-phosphorus or nickel-chromium.
  • Nickel forms a ternary compound with the solder material, e.g. the tin-silver in a boundary layer, the thickness of the boundary layer being limited by self-regulation during the formation of the ternary compounds. Additional measures for defining the thickness of the boundary layer are therefore not necessary.
  • the boundary layer forms an effective barrier against electromigration and, on the other hand, increases the electrical resistance only to a still acceptable extent.
  • the ternary compounds for example as intermetallic phases, build up a complicated space lattice.
  • the interconnect or the connection plate comprises at least 80 atomic percent of aluminum.
  • copper is used as a constituent, with its proportion being more than 50 atomic percent.
  • the basic layer forms a diffusion barrier for copper, so that the copper of the auxiliary layer does not penetrate into the interconnect.
  • the basic layer comprises titanium-tungsten or contains titanium-tungsten, the proportion of titanium preferably being less than 20 atomic percent. The barrier and adhesion properties of this layer are particularly good.
  • other materials are also suitable, such as titanium, tantalum, titanium nitride or tantalum nitride, and layer combinations of these materials are furthermore also possible, e.g. a layer sequence made of a titanium layer, a titanium-tungsten layer and a titanium layer.
  • the contact projection arrangement has a simple construction.
  • no copper-containing layer that would have to be protected against corrosion is situated between the interconnect and the basic layer.
  • FIGS. 1A to 1 B show production stages during the production of a soldering bump.
  • FIG. 2 shows a plan view of the soldering bump after the deposition of a nickel base and prior to the deposition of solder material.
  • FIGS. 1A to 1 B show production stages during the production of a soldering bump 10 .
  • the method begins proceeding from a substrate 12 , which contains for example a plurality of metallization layers (not illustrated) and a main body made of silicon.
  • the metallization layers in each case contain a multiplicity of interconnects and vias which are insulated by an intralayer dielectric within a metallization layer and by an interlayer dielectric between adjacent metallization layers.
  • a multiplicity of semiconductor components e.g. field effect transistors of a memory circuit or of a processor, are formed on the main body made of silicon.
  • an upper aluminum layer 14 is applied to the substrate 12 and patterned using a photolithographic method, a connection pad 16 being produced.
  • the aluminum layer 14 and also the connection pad 16 have for example a thickness in the range from 500 nanometers to 2 micrometers, 500 nanometers in the exemplary embodiment.
  • the connection pad 16 has for example a rectangular or square basic area. In the exemplary embodiment, the basic area is octagonal, the distance between two mutually opposite sides of the hexagon being approximately 80 micrometers.
  • the aluminum layer 14 contains only small additions of less than 5 atomic percent, for example 0.5 atomic percent, of silicon, and if appropriate a copper addition, in particular 1 atomic percent.
  • a passivation layer 18 is deposited.
  • the passivation layer 18 has for example a layer thickness in the range from 500 nanometers to 1 micrometer, 500 nanometers in the exemplary embodiment.
  • the passivation layer 18 contains for example an oxide layer and an overlying nitride layer.
  • a multiplicity of cutouts are introduced into the passivation layer 18 for soldering bumps, one cutout 20 of which is illustrated in FIG. 1A .
  • the cutout 20 is for example likewise octagonal, but has a smaller diameter than the connection pad 16 . In the exemplary embodiment, the diameter of the cutout 20 is approximately 60 micrometers.
  • a titanium-tungsten barrier layer 22 is applied over the whole area, the layer thickness of said barrier layer lying e.g. in the range from 100 nanometers to 200 nanometers.
  • the barrier layer 22 has a layer thickness of 100 nanometers.
  • the barrier layer 22 contains for example more than 80 atomic percent of tungsten. In the exemplary embodiment, the proportion of tungsten is 90 atomic percent and the proportion of titanium is 10 atomic percent.
  • the barrier layer 22 is applied by sputtering, for example.
  • the thickness of the copper layer 24 lies for example in the range from 80 nanometers to 150 nanometers. In the exemplary embodiment, the copper layer 24 has a thickness of 100 nanometers.
  • the copper layer 24 is applied by sputtering.
  • a resist layer 26 e.g. with a layer thickness of 100 micrometers, is subsequently applied to the copper layer 24 .
  • the resist layer 26 is exposed and developed, a cutout 28 arising above the cutout 20 .
  • the cutout 28 is likewise octagonal, but has a somewhat larger diameter than the cutout 20 .
  • the diameter of the cutout 28 is 80 micrometers in the exemplary embodiment.
  • the cutouts 20 and 28 lie concentrically with respect to one another.
  • the copper is removed at the bottom of the cutout 28 by patterning of the copper layer 24 according to the mask formed by the resist layer 26 .
  • wet-chemical etching is effected, undercuts 32 of the copper layer 32 being noncritical, as will be explained in greater detail below.
  • the cutouts are kept small on account of an optimization of the etching and amount to less than 2 micrometers.
  • a nickel base 50 is subsequently electrodeposited, the copper layer 24 critically serving for carrying current outside the cutout 28 . Only at the bottom of the cutout 28 does the barrier layer 20 critically serve for feeding current, in particular at the start of electroplating.
  • firstly electroplating is effected only comparatively slowly with a low current density.
  • the nickel base 50 has a layer thickness like the copper layer 24 , that is to say a layer thickness of 100 nanometers in the exemplary embodiment, a changeover is made gradually or in steps to a higher current density for faster electroplating.
  • the nickel base 50 is deposited for example with a layer thickness of 2 micrometers to 5 micrometers. In the exemplary embodiment, the layer thickness of the nickel base is 3 micrometers.
  • the undercuts 32 or these cavities do not cause a disturbance because possible depositions in this region do not adversely affect the functionality of the contact projection.
  • solder material 52 is subsequently electrodeposited, a high current density being used directly at the beginning.
  • the solder material is a tin-silver solder deposited with a layer thickness in the range of 50 to 120 micrometers.
  • the solder material 52 has a layer thickness of 90 micrometers.
  • the electrodepositions of the nickel base 50 and of the soldering material 52 are conformal.
  • An edge 54 of the cutout 20 is mapped as edge 56 on the nickel base 50 and as edge 58 on the solder material 52 .
  • FIG. 1C shows that after the deposition of the solder material 52 , the resist layer 26 is removed again, so that the soldering bump 10 is uncovered.
  • the residues of the copper layer 24 are subsequently removed from the barrier layer 22 by wet-chemical or dry-chemical means.
  • the barrier layer 22 is removed in regions which are not covered by the nickel base 50 .
  • a barrier layer region 22 a arises between the nickel base 50 and the connection pad 16 .
  • the barrier layer region 22 a projects beyond the cutout 20 and bears on the passivation layer 18 in the vicinity of the cutout 22 a , for example in a vicinity of less than 15 micrometers. Further away from the cutout 20 , by contrast, the barrier layer 22 was removed.
  • the smallest possible layer thicknesses are chosen for the copper layer 24 and for the barrier layer 22 but without impairing their actual current feeding function and barrier function, respectively, to an excessively great extent.
  • the soldering bump 10 is subsequently heated in a reflow step momentarily to a temperature of 400 degrees Celsius, for example, the solder material 52 being reshaped in spherical fashion.
  • a thin boundary layer containing, inter alia, the ternary alloy tin-nickel-silver forms at the boundary 70 between nickel base and solder material.
  • FIG. 2 shows a plan view of the soldering bump 10 after the deposition of the nickel base 50 and prior to the deposition of the solder material 52 .
  • the plan view was originally photographed, the resist layer 26 previously having been removed.
  • the octagonal connection pad 16 adjoining for example an interconnect 80 of a rewiring plane is readily discernible.
  • the titanium-tungsten barrier layer 22 is uncovered in the region of the undercuts 32 , which have a width B 1 of up to 10 micrometers in the circumferential direction.
  • the nickel base 50 is delimited by the cutout 28 and has a diameter D of 80 micrometers.
  • the edge 56 of the nickel base 50 is also readily discernible.
  • the auxiliary layer in particular the copper layer
  • galvanic etching-back the substrate is connected as an anode from which material is removed.
  • the worked-back region is subsequently built again by an electrochemical deposition, e.g. a nickel deposition. Consequently, copper-free interfaces, in particular, are present below the soldering bumps.
  • a preferred field of application is radio frequency circuits and housings with more than 100 connections which are mounted in accordance with the flip-chip technique.
  • a metal barrier e.g. a titanium layer or a titanium-tungsten layer
  • an auxiliary layer e.g. a copper layer
  • UBM Under Bump Metallization
  • the barrier layer prevents metallic interdiffusion from the solder material into the interconnects on the wafer.
  • the auxiliary layer serves as a current-carrying contact-making layer for the electroplating process.
  • the electroplating process begins with a wetting or prewetting step for uniformly wetting the contacts with the electrolyte.
  • the first metal layer that is intended to be grown is nickel, for example, e.g. a so-called stud having a thickness of 2 to 5 micrometers or having a thickness in the range of 5 micrometers to 100 micrometers, in particular having a thickness of greater than 40 micrometers.
  • the solder metallization is subsequently deposited with thicknesses of up to 50 micrometers or up to 150 micrometers.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
US10/580,740 2003-11-29 2004-11-17 Method for Electroplating and Contact Projection Arrangement Abandoned US20070246133A1 (en)

Applications Claiming Priority (3)

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DE10355953.1 2003-11-29
DE10355953A DE10355953B4 (de) 2003-11-29 2003-11-29 Verfahren zum Galvanisieren und Kontaktvorsprungsanordnung
PCT/EP2004/052999 WO2005053012A1 (de) 2003-11-29 2004-11-17 Verfahren zum galvanisieren und kontaktvorsprungsanordnung

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DE10355953A1 (de) 2005-07-07
CN1886828A (zh) 2006-12-27
CN100508147C (zh) 2009-07-01
WO2005053012A1 (de) 2005-06-09
DE10355953B4 (de) 2005-10-20

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