CN1315158C - 选择性电镀半导体器件的输入/输出焊盘的方法 - Google Patents

选择性电镀半导体器件的输入/输出焊盘的方法 Download PDF

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CN1315158C
CN1315158C CNB2004100929298A CN200410092929A CN1315158C CN 1315158 C CN1315158 C CN 1315158C CN B2004100929298 A CNB2004100929298 A CN B2004100929298A CN 200410092929 A CN200410092929 A CN 200410092929A CN 1315158 C CN1315158 C CN 1315158C
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layer
pad
tiw
seed layer
metal level
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CN1630039A (zh
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郑天人
戴维·F·埃施塔德
乔纳森·H·格里菲思
萨拉·H·尼克尔伯克尔
罗斯玛丽·A·普莱维蒂－凯利
罗格尔·A·居昂
卡马列什·斯里瓦斯塔瓦
黄洸汉
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International Business Machines Corp
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Abstract

一种选择性电镀半导体输入/输出(I/O)焊盘的方法，包含在半导体基体的钝化层上形成钛-钨(TiW)层，所述TiW层还延伸到成形于所述钝化层上用于露出所述I/O焊盘的开口中，使得TiW层覆盖所述开口的侧壁和所述I/O焊盘的顶面。在所述TiW层上形成种子层。选择性去除所述种子层的一部分，使剩余的种子层材料对应于所述I/O焊盘的所需的互连冶金位置。使用所述TiW层作为导电电镀介质，在所述种子层材料上电镀至少一个金属层。

Description

选择性电镀半导体器件 的输入/输出焊盘的方法
技术领域
本发明涉及半导体器件加工，尤其涉及一种使用钛钨(TiW)种子层选择性电镀半导体器件的输入/输出焊盘的方法。
背景技术
在半导体器件的制造过程中，已经开发了选择性电镀工艺，以便在线圈、通孔、焊盘和其他互连结构上电镀铜、镍、金及其他导电金属。在这种选择电镀工艺中，电流通过难熔金属层(例如，钽/氮化钽(Ta/TaN))传导，而使用铜晶种在线或焊盘上电镀金属。电镀条件特别设计为能仅在预先形成图案的铜焊盘上沉积，而不在Ta/TaN晶种上。因为在电镀工艺中没有使用光致抗蚀剂，所以消除了任何由于光致抗蚀剂分层导致的过电镀和由于光致抗蚀剂浸析造成的镀液污染。而且，通过使用镍/金电镀，所述铜晶种的侧壁完全覆盖了镍/金，从而由于这种“自密封”冶金而具有优良的抗蚀性，且不再需要额外的钝化层。
另外，使用选择性铜电镀可以减少化学-机械抛光(CMP)时间，因为电镀过程中形成较少的“外来”铜。带有镍和金的焊盘可以用于与较厚的金引线结合，或用于无铅焊膏网印，作为有少量金的俘获焊盘。已经证实所述俘获焊盘上的金表现出非常低的接触电阻，这对于C4崩沸(bumping)前的电测是非常理想的。而且，已经证实电镀的镍和金作为终端金属已经在应力测试中显示出期望的结果。具体而言，为减小间距开发了多种方法，在更低的试验力和更好的可靠性性能条件下为低K电介质提供了保护更好的表面。在完成金属电镀后，所述Ta/TaN种子层通过反应离子蚀刻工艺或CMP工艺移除。
然而，普通的选择性电镀工艺并不是没有自身的缺点。首先，存在与使用Ta/TaN种子层有关的厚度均匀性问题。800埃()的Ta/TaN种子层被认为是非常有电阻性的。在镀铜的情况下，所述边缘区域可以镀到厚度约为中心区域的两倍，这在铜的均匀性要求严格的应用中是不可以接受的。其次，在种子层中表面形貌(即，拐角或其他缺陷)的存在会显著增加局部的电镀电流。在特定情况下，这些局部电流会过高，从而开始在Ta/TaN晶种上电镀金属。反过来，过电镀的金属结可能缩短器件的特征图形。因此，施加的电镀电流密度保持相当低，导致更长的电镀时间，且也可能改变膜的显微结构和性能。
常规选择性电镀的另一个缺点来自Ta/TaN移除过程(也就是，反应离子蚀刻)。反应离子蚀刻(RIE)工艺能够从所述表面移除部分金。尽管金的损失可以补偿，在所述制造工具中再沉积金已经成为制造业的关注点。另一方面，所得到的较薄的金层可以导致引线结合的失败。CMP也不是Ta/TaN晶种移除的理想方法，由于所属结构的形貌学特征。第三个可能是湿化学蚀刻移除所述Ta/TaN晶种，然而，从制造的角度，所述蚀刻材料难于操纵。
因此，需要实施能够得到较高的导电性和工具生产能力、且没有上述缺点的选择性电镀工艺。
发明内容
一种选择性电镀半导体输入/输出焊盘的方法克服或缓和了上述讨论的现有技术的缺点和不足。在示例性实施例中，所述方法包含在半导体基体的钝化层上形成钛-钨(TiW)层，所述TiW层还延伸到成形于所述钝化层上用于露出所述I/O焊盘的开口中，使得TiW层覆盖所述开口的侧壁和所述I/O焊盘的顶面。在所述TiW层上形成种子层。选择性去除所述种子层的一部分，使剩余的种子层材料对应于所述I/O焊盘的所需的互连冶金位置。在所述种子层材料上电镀至少一个金属层，其中使用所述TiW层作为导电电镀介质。
另一方面，一种半导体输入/输出(I/O)焊盘结构包括在形成于半导体基体钝化层的开口内形成钛-钨(TiW)层，所述开口用于露出所述I/O焊盘，这样，所述TiW层覆盖所述开口的侧壁和所述I/O焊盘的顶面。形成于部分所述TiW层上的种子层，对应于所述I/O焊盘的所需的互连冶金位置。并且在所述种子层材料上电镀而成的至少一个金属层，其中所述TiW层用作导电电镀介质。
附图说明
参照示例性附图，在此，相同的元件在几幅图中标注为相同的附图标记。
图1至8示出了根据本发明的实施例的使用钛钨种子(TiW)层选择性电镀半导体器件输入/输出焊盘的方法的多个加工步骤。
具体实施方式
在此公开了一种使用钛钨种子层选择性电镀半导体器件输入/输出焊盘的方法和结构。所述TiW层提供了改进的电镀均匀性，与Ta/TaN导电种子层相比，显著提高了导电性。另外，TiW的使用如下所述，强调关注Ta/TaN在聚酰亚胺上的溅射问题，以及在反应离子蚀刻过程中的金损失问题。
最先参照图1，示出了适用于本发明的实施例的示例性终端金属(TD)铝接合焊盘结构100的截面图。所述结构100的特征在于铝接线焊盘102形成于半导体基体104的最上面的金属化层，用于为通过多层之间的互连结构(包括铝填充的通孔106)而成形于基体的所述有源器件(未示出)提供外部连接。铝焊盘102和通孔106周围是交替的电介质层108(例如，SiO2或低K材料)和焊盘氮化物110(例如，Si3N4)，这是本领域的技术人员已经认识到的。另外，钝化层，比如光敏性聚酰亚胺(PSPI)层112形成于焊盘氮化物110的最顶端。
为了向适当的外部连接提供入口，在铝焊盘102的顶面上成形有通孔或开口114。如图2所示，钛-钨(TiW)层116沉积在整个结构(包括通孔114的侧壁和铝焊盘102的顶部)上，接下来是铜/铬-铜(Cu/CrCu)晶种。尽管图2示出的层118是单一层，应当理解，Cu/CrCu晶种也可以是多层的。如前所述，整个Cu/CrCu层118在此前用作种子层，在电镀步骤中，所述通孔区外的所有区域使用光致抗蚀剂进行保护，这样，所述电镀金属仅形成于所述Cu/CrCu的裸露的部分。在本方法中，然而，除了通孔114区外，Cu/CrCu在所有部位都最先被移除，在此，形成了互连冶金。
因此，图3示出了利用光致抗蚀剂120对通孔114区的构图(在此，应保留Cu/CrCu 118层)。此后，未掩蔽的Cu/CrCu 118层部分被电蚀刻掉，停止在如图4所示的TiW层116上。还发现了其他关于电蚀刻工艺和技术的信息，例如，在授予Datta等的美国专利5486282，和授予Dinan等的美国专利5536388中，在此通过引用而包含其全部内容。然后，剩余的光致抗蚀剂120被揭掉(图5)，镍层122和金层124的电镀实施如图6所示。因为Cu/CrCu层118仅出现在通孔114区，它用作电镀的种子层。而且，连续的TiW层116用于提供电镀导电性的电流传输层，但是在其上不形成任何电镀材料(Ni，Au)。这可以通过平衡所使用电位来实现，从而，镍将在Cu/CrCu种子层118上成核，而不是在TiW层116上成核。
从图6中还能够注意到，与常规电镀使用受保护的Cu/CrCu种子层形成鲜明的对比，在通孔114区中剩余的Cu/CrCu材料的侧壁被电镀材料封闭，因为在实际的电镀步骤中没有光致抗蚀剂。导致改善了Cu/CrCu材料的耐蚀性。一旦形成互连冶金，TiW层116未被所述互连冶金覆盖的剩余部分通过湿法蚀刻去除。最后，如图8所示，所述接合焊盘结构100做好进行下一个加工步骤的准备，比如，添加无铅焊膏126，制备C4球形接头等。另外，引线接合接头也使用与所述接合焊盘结构100相连。
与Ta/TaN层相比，使用TiW层作为导电的电镀晶种材料具有几个优点。首先，TiW层的晶种厚度可以到达6000，很好地覆盖了表面形貌还降低了片电阻。例如，据估计TiW的这一厚度的导电性10倍于700形成的Ta衬垫，能够带来更好的电镀均匀性。另外，TiW对镍和金的电镀具有更高的过电位。据此，通过TiW层的电流量可以比通过Ta/TaN层的电流量大3倍，而且不会在所述层上形成节。带来器件产量的改善大约为300％。而且，因为TiW是已知的C4球限冶金(BLM)材料，TiW蚀刻可以使用过氧化氢和末端探测控制非常容易地进行。示例性TiW蚀刻工艺在授予Srivastava等的美国专利6293457中进行了描述，在此通过引用包含其全部内容。而且，所述金层的厚度在TiW蚀刻工艺中没有损失。
虽然参照优选实施例或实施例描述了本发明，本领域的技术人员刻理解，可以进行多种变化，替换多种要素的等价物，而不背离本发明的范围。另外，可以采用特定场景或材料对本发明所教授的内容进行很多改进，而不背离本发明的范围。因此，本发明并不仅限于作为经过考虑的最佳方式在此公开的特定的实施例，本发明将包括落入后附的权利要求书范围中的所有实施例。

Claims (14)

1.一种选择性电镀半导体I/O焊盘的方法，包含
在半导体基体的钝化层上形成钛-钨TiW层，所述TiW层还延伸到成形于所述钝化层上用于露出所述I/O焊盘的开口中，使得TiW层覆盖所述开口的侧壁和所述I/O焊盘的顶面；
在所述TiW层上形成种子层；
选择性去除所述种子层的一部分，使剩余的种子层材料对应于所述I/O焊盘的所需的互连冶金位置，并且
使用所述TiW层作为导电电镀介质，在所述剩余的种子层材料上电镀至少一个金属层。
2.如权利要求1所述的方法，其特征在于所述种子层还包含Cu/CrCu层。
3.如权利要求1所述的方法，其特征在于所述至少一个金属层还包含伴随有金层的镍层。
4.如权利要求1所述的方法，其特征在于进一步包含在电镀后，移除没有被所述至少一个金属层覆盖的所述TiW层的部分。
5.如权利要求1所述的方法，其特征在于所述I/O焊盘还包含铝焊盘。
6.如权利要求1所述的方法，其特征在于所述种子层被光致抗蚀剂构图选择性移除。
7.如权利要求1所述的方法，其特征在于所述钝化层还包含光敏性聚酰亚胺层。
8.一种半导体I/O焊盘结构，包含
在形成于半导体基体上的钝化层的开口内形成的钛-钨TiW层，所述开口用于露出所述I/O焊盘，这样，所述TiW层覆盖所述开口的侧壁和所述I/O焊盘的顶面；
形成于部分所述TiW层上的种子层，对应于所述I/O焊盘的所需的互连冶金位置，并且
在所述种子层材料上电镀而成的至少一个金属层，其中所述TiW层用作导电电镀介质。
9.如权利要求8所述的I/O焊盘结构，其特征在于所述种子层还包含Cu/CrCu层。
10.如权利要求8所述的I/O焊盘结构，其特征在于所述至少一个金属层还包含伴随有金层的镍层。
11.如权利要求8所述的I/O焊盘结构，其特征在于所述I/O焊盘还包含铝焊盘。
12.如权利要求8所述的I/O焊盘结构，其特征在于所述至少一个金属层部分地密封了所述种子层的侧壁。
13.如权利要求12所述的I/O焊盘结构，其特征在于所述至少一个金属层覆盖了所述TiW层未被所述种子层覆盖的剩余部分。
14.如权利要求8所述的I/O焊盘结构，其特征在于所述钝化层还包含光敏性聚酰亚胺层。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050167837A1 (en) * 2004-01-21 2005-08-04 International Business Machines Corporation Device with area array pads for test probing
JP4665531B2 (ja) * 2005-01-27 2011-04-06 日立電線株式会社 配線板の製造方法
JP4468191B2 (ja) * 2005-01-27 2010-05-26 株式会社日立製作所 金属構造体及びその製造方法
KR100871768B1 (ko) * 2007-05-18 2008-12-05 주식회사 동부하이텍 반도체 소자 및 ｂｏａｃ/ｃｏａ 제조 방법
JP2009099589A (ja) * 2007-10-12 2009-05-07 Elpida Memory Inc ウエハまたは回路基板およびその接続構造体
US7727890B2 (en) 2007-12-10 2010-06-01 International Business Machines Corporation High aspect ratio electroplated metal feature and method
US8089154B2 (en) * 2008-03-19 2012-01-03 Nippon Mining & Metals Co., Ltd. Electronic component formed with barrier-seed layer on base material
US8563336B2 (en) 2008-12-23 2013-10-22 International Business Machines Corporation Method for forming thin film resistor and terminal bond pad simultaneously
CN101859748B (zh) * 2009-04-07 2012-04-18 日月光半导体制造股份有限公司 焊垫及应用其的封装结构
US8193089B2 (en) * 2009-07-13 2012-06-05 Seagate Technology Llc Conductive via plug formation
US8394713B2 (en) * 2010-02-12 2013-03-12 Freescale Semiconductor, Inc. Method of improving adhesion of bond pad over pad metallization with a neighboring passivation layer by depositing a palladium layer
CN102194719A (zh) * 2010-03-15 2011-09-21 中芯国际集成电路制造(上海)有限公司 在封装过程中提高焊点特性的方法
EP2398046A1 (en) * 2010-06-18 2011-12-21 Nxp B.V. Integrated circuit package with a copper-tin joining layer and manufacturing method thereof
US8148257B1 (en) * 2010-09-30 2012-04-03 Infineon Technologies Ag Semiconductor structure and method for making same
US8735273B2 (en) * 2011-07-08 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Forming wafer-level chip scale package structures with reduced number of seed layers
US9324669B2 (en) 2014-09-12 2016-04-26 International Business Machines Corporation Use of electrolytic plating to control solder wetting
US10297563B2 (en) * 2016-09-15 2019-05-21 Intel Corporation Copper seed layer and nickel-tin microbump structures
US10037957B2 (en) * 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US20230275050A1 (en) * 2022-02-28 2023-08-31 Texas Instruments Incorporated Silver- and gold-plated conductive members

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1392609A (zh) * 2001-06-15 2003-01-22 东部电子株式会社 半导体封装件及其制造方法
CN1111907C (zh) * 1994-02-18 2003-06-18 艾利森电话股份有限公司 在半导体器件上形成互连的方法和半导体器件上的互连件

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5486282A (en) 1994-11-30 1996-01-23 Ibm Corporation Electroetching process for seed layer removal in electrochemical fabrication of wafers
US5536388A (en) 1995-06-02 1996-07-16 International Business Machines Corporation Vertical electroetch tool nozzle and method
US5620611A (en) 1996-06-06 1997-04-15 International Business Machines Corporation Method to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder pads
US6140234A (en) * 1998-01-20 2000-10-31 International Business Machines Corporation Method to selectively fill recesses with conductive metal
JP3715816B2 (ja) 1999-02-18 2005-11-16 ローム株式会社 半導体チップ
US6451627B1 (en) 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
US6293457B1 (en) 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
US6605534B1 (en) * 2000-06-28 2003-08-12 International Business Machines Corporation Selective deposition of a conductive material
US6534863B2 (en) 2001-02-09 2003-03-18 International Business Machines Corporation Common ball-limiting metallurgy for I/O sites
US6853076B2 (en) 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US6749760B2 (en) 2001-10-26 2004-06-15 Intel Corporation Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead
US7025866B2 (en) * 2002-08-21 2006-04-11 Micron Technology, Inc. Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1111907C (zh) * 1994-02-18 2003-06-18 艾利森电话股份有限公司 在半导体器件上形成互连的方法和半导体器件上的互连件
CN1392609A (zh) * 2001-06-15 2003-01-22 东部电子株式会社 半导体封装件及其制造方法

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