WO2014037996A1 - 半導体装置、半導体装置の製造方法 - Google Patents

半導体装置、半導体装置の製造方法 Download PDF

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Publication number
WO2014037996A1
WO2014037996A1 PCT/JP2012/072476 JP2012072476W WO2014037996A1 WO 2014037996 A1 WO2014037996 A1 WO 2014037996A1 JP 2012072476 W JP2012072476 W JP 2012072476W WO 2014037996 A1 WO2014037996 A1 WO 2014037996A1
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WIPO (PCT)
Prior art keywords
film
solder
semiconductor device
metal film
bonding
Prior art date
Application number
PCT/JP2012/072476
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English (en)
French (fr)
Inventor
洋輔 中田
政良 多留谷
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US14/422,573 priority Critical patent/US9653390B2/en
Priority to DE112012006875.0T priority patent/DE112012006875T5/de
Priority to PCT/JP2012/072476 priority patent/WO2014037996A1/ja
Priority to KR1020167031425A priority patent/KR20160132499A/ko
Priority to CN201280075614.5A priority patent/CN104603921B/zh
Priority to JP2014534065A priority patent/JP6156381B2/ja
Priority to KR1020157005393A priority patent/KR20150038535A/ko
Publication of WO2014037996A1 publication Critical patent/WO2014037996A1/ja
Priority to US15/456,746 priority patent/US9911705B2/en

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Definitions

  • the present invention relates to a semiconductor device used for high current switching and the like and a method of manufacturing the semiconductor device.
  • Patent Document 1 discloses a semiconductor device in which an external electrode that is a copper plate and a semiconductor element electrode are directly joined by solder. The reason why the external electrode and the semiconductor element electrode are directly joined by soldering is to realize wiring connection capable of energizing a large current while reducing the electric resistance.
  • Patent Document 2 discloses forming a metal film (plating electrode) having good bonding properties with solder on a part of a semiconductor element electrode (emitter electrode). This metal film is joined to the heat sink by solder. By controlling the distance and relative position between the metal film and the heat sink, stress is prevented from concentrating on the outer edge of the metal film.
  • Patent Document 2 has a problem of low productivity because it is necessary to precisely control the distance and relative position between the metal film and the heat sink.
  • the present invention has been made to solve the above-described problems, and provides a semiconductor device capable of suppressing the generation of cracks in an electrode due to stress from solder and a method of manufacturing the semiconductor device by a simple method. With the goal.
  • a semiconductor device is formed so as to surround a semiconductor element, a surface electrode formed on the surface of the semiconductor element, a junction on the surface electrode, and the junction while contacting the junction
  • a manufacturing method of a semiconductor device includes a step of forming a surface electrode on a semiconductor element, a step of forming a metal film on the surface electrode, and avoiding an outer peripheral portion of the metal film. And a joining step of forming solder at the center and joining the metal film and the external electrode through the solder.
  • the stress relaxation portion disperses the stress from the solder, it is possible to suppress the cracks from being generated in the electrode.
  • a semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
  • the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
  • the semiconductor device 10 includes a base plate 12 made of metal.
  • a semiconductor element 14 made of a vertical IGBT is disposed above the base plate 12.
  • a gate electrode 14a and an emitter electrode (hereinafter, the emitter electrode is referred to as a surface electrode 14b) are formed.
  • a collector electrode 14 c is formed on the lower surface side of the semiconductor element 14.
  • the gate electrode 14a and the surface electrode 14b are formed of a material containing 95% or more of aluminum.
  • the collector electrode 14c is formed of a laminated metal film for ensuring the bondability with the solder.
  • the laminated metal film of the collector electrode 14c is composed of Ti / Ni / Au, AlSi / Ti / Ni / Au, or the like in order from the semiconductor element 14 side.
  • the collector electrode 14 c is fixed to the base plate 12 with solder 16.
  • a metal film 20 is formed on the surface electrode 14b.
  • the metal film 20 is covered with the coating film 22 so that a part of the upper surface of the metal film 20 is exposed.
  • a solder 30 made of SnAgCu-based Pb-free solder is joined to a portion of the metal film 20 exposed from the coating film 22. The solder 30 joins the external electrode 32 extending to the outside of the semiconductor device 10 and the metal film 20.
  • the external electrode 42 is joined to the base plate 12 with solder 40.
  • a wire 50 is connected to the gate electrode 14a.
  • the wire 50 connects the external electrode 52 extending to the outside and the gate electrode 14a.
  • An insulating sheet 60 is attached to the lower surface side of the base plate 12.
  • Each component described above is covered with a sealing material 70 that exposes the external electrodes 32, 42, 52 and the lower surface side of the insulating sheet 60 to the outside.
  • FIG. 2 is a plan view of the surface electrode, the coating film, and the solder.
  • the solder 30 is surrounded by the coating film 22.
  • FIG. 3 is a plan view of the metal film and the solder.
  • the solder 30 is formed only at the center of the metal film 20. Therefore, the solder 30 is not formed on the outer peripheral portion of the metal film 20.
  • FIG. 4 is an enlarged view of the outer peripheral portion of the metal film and its periphery.
  • the metal film 20 includes a joint portion 20A and a stress relaxation portion 20B formed so as to surround the joint portion 20A while being in contact with the joint portion 20A.
  • the stress relaxation part 20B is an outer peripheral part of the metal film 20 in FIG.
  • the joining portion 20A has a first adhesion film 20a formed of Ti or Mo on the surface electrode 14b.
  • the bonding portion 20A has a first bonding film 20b made of Ni on the first adhesion film 20a.
  • the joining portion 20A has a solder-Ni alloy portion 20c formed on the first joining film 20b.
  • the stress relaxation portion 20B has a second adhesion film 20d formed of Ti or Mo on the surface electrode 14b. Further, the stress relaxation part 20B has a second bonding film 20e formed of Ni on the second adhesion film 20d. Further, the stress relaxation portion 20B has an antioxidant film 20f formed of Au or Ag on the second bonding film 20e.
  • the first bonding film 20b is formed thinner than the second bonding film 20e. The thickness of the first bonding film 20b is preferably 0.5 ⁇ m or more.
  • the stress relaxation part 20B is formed so that the length (length a) from the part in contact with the joint part 20A to the outermost peripheral part is 10 ⁇ m or more.
  • the solder 30 is joined to the upper surface of the joint 20A.
  • An external electrode 32 is bonded to the bonding portion 20A via the solder 30.
  • the solder 30 is bonded to the bonding portion 20A while avoiding the stress relaxation portion 20B.
  • a coating film 22 that covers the stress relaxation portion 20B is formed so that the solder 30 does not contact the stress relaxation portion 20B.
  • the coating film 22 is preferably formed of any polyimide having a thickness of 2 to 20 ⁇ m.
  • FIG. 5 is a cross-sectional view showing that a surface electrode is formed on a semiconductor element.
  • the surface electrode 14b is formed by sputtering, for example, Al, AlSi, or AlCu. Thereafter, the surface electrode 14b is heated at 400 to 470 ° C. in a hydrogen or nitrogen atmosphere. This heat treatment increases the crystal size of the surface electrode 14b and improves the flatness of the surface electrode 14b. Therefore, the coverage of the metal film 20 with respect to the surface electrode 14b can be improved.
  • FIG. 6 is a cross-sectional view showing that a resist is formed on a part of the surface electrode.
  • the resist 100 is formed by lithography or the like so as to cover a region of the surface electrode 14b where the metal film is not desired to be formed.
  • FIG. 7 is a cross-sectional view showing that a metal film is formed.
  • the metal film includes, from the surface electrode 14b side, an adhesion film 20g formed of Ti or Mo, a bonding film 20h formed of Ni on the adhesion film 20g, and an oxidation formed of Au or Ag on the bonding film 20h.
  • a prevention film 20i is provided.
  • the adhesion film 20g, the bonding film 20h, and the antioxidant film 20i are formed by a sputtering method or the like.
  • the thickness of the bonding film 20h that forms an appropriate compound film with solder and functions as a barrier against excessive erosion by the solder is the largest.
  • the bonding film 20h (the first bonding film 20b and the second bonding film 20e of the semiconductor device 10) substantially determines the mechanical strength of the metal film 20.
  • the antioxidant film 20i is formed in order to prevent the bonding film 20h made of Ni from being oxidized and the solder wettability of the bonding film 20h from being lowered.
  • the structure in the portion of the metal film formed on the surface electrode 14b that comes into contact with the resist 100, when viewed microscopically, the structure may be mixed in, or the film thickness may deviate from a desired value. It is a relatively weak part.
  • FIG. 8 is a cross-sectional view showing that the resist has been removed.
  • the resist 100 is immersed in a chemical solution for resist removal, and the resist 100 and the metal film thereon are removed. Thus, a metal film is formed in a desired region on the surface electrode 14b.
  • FIG. 9 is a cross-sectional view showing that the outer peripheral portion of the metal film is covered with a coating film.
  • the coating film 22 is formed by lithography using photosensitive polyimide. Alternatively, a non-photosensitive polyimide and a photosensitive resist may be used in combination. In this case, after processing the photosensitive resist into a desired shape by a lithography method, the non-photosensitive polyimide is processed.
  • the coating film 22 is formed to have a film thickness of about 2 to 20 ⁇ m.
  • FIG. 10 is a cross-sectional view showing that the external electrode is soldered to the joint in the joining process.
  • the joining step for example, molten solder is dropped from a through hole provided in the external electrode 32 to the joint portion 20 ⁇ / b> A, and the external electrode 32 and the joint portion 20 ⁇ / b> A are joined via the solder 30.
  • the coating film 22 is formed on the outer peripheral portion of the metal film 20, the solder is formed at the central portion of the metal film 20 avoiding this outer peripheral portion. That is, the coating film 22 prevents the solder from spreading.
  • the portion where the solder is formed becomes the joint portion 20 ⁇ / b> A, and the portion covered with the coating film 22 and where the solder is not formed becomes the stress relaxation portion 20 ⁇ / b> B.
  • the antioxidant film 20i at the center of the metal film 20 is immediately diffused into the solder. Thereafter, Ni and solder of the bonding film 20h at the center of the metal film 20 are alloyed to form an alloy portion 20c of solder and Ni.
  • the thickness of the bonding film 20h at the center of the metal film 20 is reduced by the amount of the alloy part 20c (for example, about 0.3 ⁇ m).
  • the portion where the film thickness is reduced is the first bonding film 20b.
  • a method of soldering the external electrode 32 and the metal film for example, a method of melting a plate solder in a formic acid atmosphere may be employed in addition to a method of using a molten solder.
  • Fig. 11-13 shows the analysis results of the stress distribution in the metal film when the solder is heated to 125 ° C.
  • the bonding film mainly supports the stress from the solder. Therefore, an analysis model was constructed by forming the metal film 20 ′ only with Ni as the material of the bonding film. Further, the stress relaxation part is covered with the sealing material 70.
  • FIG. 11 is a diagram showing the stress distribution in the metal film when the film thickness of the metal film is 0.5 ⁇ m.
  • FIG. 12 is a diagram showing the stress distribution in the metal film when the thickness of the metal film is 1.0 ⁇ m.
  • FIG. 13 is a diagram showing the stress distribution in the metal film when the thickness of the metal film is 1.5 ⁇ m. From these analysis results, it can be seen that in the metal film, the stress of the joint 20A ′ is mainly increased, but also in the stress relaxation portion 20B ′, a high stress is generated from the end of the solder 30 to the outside by about 10 ⁇ m.
  • stress relaxation portion 20B is formed so that the length (a) from the portion in contact with joint portion 20A to the outermost peripheral portion is 10 ⁇ m or more.
  • the stress generated in the metal film 20 is dispersed in the stress relaxation portion 20B. Therefore, the stress relaxation portion 20B can sufficiently relax the stress of the solder and reduce the stress reaching the surface electrode 14b.
  • the joint 20A ′ bears a larger stress at the joint 20A ′ and the stress relaxation part 20B ′. Therefore, the strength of the metal film needs to be uniform and strong at the joint 20A ′.
  • the outermost peripheral portion of the metal film may be mixed with the structure when viewed microscopically, or the film thickness may deviate from the desired value, and the strength of the metal film is a relatively weak part. ing. Therefore, in the first embodiment of the present invention, stress is mainly borne by the joint portion 20A where the strength of the metal film 20 is strong, and auxiliary stress relaxation is performed by the stress relaxation portion 20B where the strength of the metal film is weak, An excellent stress relaxation effect was obtained. By doing in this way, it can suppress that the metal film 20 deform
  • the length (a) from the portion in contact with the joint 20A of the stress relaxation portion 20B to the outermost periphery is preferably 50 to 500 ⁇ m if possible. By setting it to 50 ⁇ m or more, it is possible to secure a margin for the position and pattern controllability of the coating film 22 and the metal film 20, and to detect a pattern abnormality by simple inspection. Further, by setting the thickness to 500 ⁇ m or less, the adhesion between the antioxidant film 20f and the coating film 22 can be secured, so that the coating film 22 can be prevented from being detached from the metal film 20 in the wafer process including the bonding step. Increasing the length a in this manner is useful for sufficiently relaxing the stress in the stress relaxation portion even when the operating temperature of the semiconductor element increases and the high stress region of the stress relaxation portion expands.
  • FIG. 14 is a graph showing the relationship between the thickness of the metal film and the stress generated in the metal film.
  • the yield stress of the metal film is 490 MPa. Therefore, the stress of the metal film must be less than 490 MPa.
  • FIG. 14 shows that the stress generated in the metal film is less than 490 MPa when the thickness of the metal film is 0.5 ⁇ m or more. Therefore, if the thickness of the metal film is 0.5 ⁇ m or more, the stress generated in the metal film is lower than the yield stress of the metal film, so that the stress from the solder is not deformed by the stress from the solder and can support the stress from the solder. Can do.
  • the thickness of the first bonding film 20b is 0.5 ⁇ m or more, deformation of the metal film 20 can be suppressed.
  • FIG. 14 shows that the stress reduction effect is saturated when the thickness of the metal film exceeds 1 ⁇ m.
  • the coating film 22 prevents the solder from spreading. Then, the solder 30 can be formed “only at the center of the metal film 20”. Moreover, the influence on the process after a joining process can be avoided by using the polyimide which was excellent in heat resistance for the coating film 22.
  • the thickness of the coating film 22 is preferably set to any value of 2 to 20 ⁇ m.
  • the surface electrode 14b according to the first embodiment of the present invention contains 95% or more of aluminum, it can be easily formed and processed as an electrode of a semiconductor element using various semiconductor substrates such as a Si substrate, and when a metal wire is connected. Can be bonded with excellent bonding characteristics. Since Ti or Mo is used for the first adhesion film 20a and the second adhesion film 20d, Ni of the first bonding film 20b and the second bonding film 20e is secured while ensuring the adhesion between the surface electrode 14b and the metal film 20. It is possible to prevent diffusion to the surface electrode 14b side.
  • solder 30 is joined to the metal film 20 because the solder 30 is joined to the metal film 20, good jointability and solder wettability can be ensured between the solder 30 and the metal film 20.
  • the surface electrode 14b is an emitter electrode, but the present invention is not limited to this. If the metal film 20 and the coating film 22 are formed on the surface electrode formed on the surface of the semiconductor element 14, cracking of the surface electrode can be suppressed. Accordingly, the surface electrode is not particularly limited as long as it is an electrode formed on the semiconductor element 14. Moreover, the semiconductor element 14 is not limited to IGBT, For example, MOSFET or a diode may be sufficient.
  • the metal film 20 does not have to have a three-layer structure. For example, Ni—P grown by plating can also be used.
  • FIG. 15 is a cross-sectional view of the outer peripheral portion of the metal film and its periphery in the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the second embodiment of the present invention is characterized in that a modified film 200 is formed on the surface of the stress relaxation portion 20C.
  • the reformed film 200 is formed of a material that is less likely to adhere to the solder than the surface portion of the joint portion 20A so that the solder 30 does not wet and spread in the region immediately above the stress relaxation portion 20C. More specifically, the modified film 200 is formed of a metal oxide film obtained by oxidizing Ni.
  • the length (a) from the portion in contact with the joint 20A to the end is 10 ⁇ m or more.
  • connects the junction part 20A of the stress relaxation part 20C to the outermost periphery part is also 10 micrometers or more. Note that the length indicated by a in FIG. 15 is preferably any one of 100 to 1000 ⁇ m.
  • FIG. 16 is a cross-sectional view showing that a sacrificial protective film is formed on the metal film.
  • the sacrificial protective film 202 is formed only at the central portion of the metal film 20 and is not formed at the outer peripheral portion of the metal film.
  • the sacrificial protective film 202 can be formed using, for example, a photosensitive resist and a lithography method.
  • FIG. 17 is a cross-sectional view showing that the antioxidant film on the outer peripheral portion of the metal film has been removed.
  • the antioxidant film is removed by a dry etching process such as sputter etching using Ar plasma or Ar ion beam milling.
  • FIG. 18 is a cross-sectional view showing that a modified film is formed.
  • the modified film 200 is a metal oxide film in which the bonding film 20h is oxidized by oxygen plasma ashing or the like.
  • the modified film 200 can be easily formed by selectively oxidizing the bonding film 20h.
  • wet etching using an organic solvent or the like is used to remove the sacrificial protective film 202, the modified film 200 can be formed by irradiating the bonding film 20h with UV light or the like after drying.
  • the portion where the modified film 200 is formed can be the stress relaxation portion 20C.
  • the modified film 200 can prevent the solder 30 from spreading and form the stress relaxation portion 20C.
  • the modified film 200 can be easily formed simply by oxidizing the bonding film 20h.
  • the reason why the length (a) of the modified film 200 from the portion in contact with the joining portion 20A to the end portion is set to any one of 100 to 1000 ⁇ m is as follows. By setting the thickness to 100 ⁇ m or more, a sufficient margin can be secured so that the solder does not wet and spread into the modified film 200 having poor wettability. By not exceeding 1000 ⁇ m, it is possible to secure a solder-surface electrode junction with a sufficient area, and to maintain the solder strength and the high-current conducting performance.
  • the modified film 200 is not limited to a metal oxide film obtained by oxidizing Ni, and is not particularly limited as long as it can suppress the spread of solder in the joining process. Further, if a process that does not form an antioxidant film at the stress relaxation portion is employed, the step of removing the antioxidant film can be omitted.
  • the coating film 22 is used, and in the second embodiment of the present invention, the modified film 200 is used to prevent the solder from spreading.
  • the stress relaxation portion can be formed. Therefore, means other than the coating film 22 or the modified film 200 may be used as long as wetting and spreading of the solder can be prevented.

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Abstract

　本願の発明にかかる半導体装置は、半導体素子と、該半導体素子の表面に形成された表面電極と、該表面電極上に、接合部と、該接合部と接しつつ該接合部を囲むように形成された応力緩和部とを有するように形成された金属膜と、該応力緩和部を避けて該接合部に接合されたはんだと、該はんだを介して該接合部に接合された外部電極と、を備えたことを特徴とする。

Description

半導体装置、半導体装置の製造方法
　この発明は、大電流のスイッチングなどに用いられる半導体装置とその半導体装置の製造方法に関する。
　特許文献１には、銅板である外部電極と半導体素子電極をはんだで直接接合した半導体装置が開示されている。外部電極と半導体素子電極をはんだで直接接合するのは、電気抵抗を下げつつ大電流通電が可能な配線接続を実現するためである。
　特許文献２には、半導体素子電極（エミッタ電極）の一部にはんだと接合性のよい金属膜（めっき電極）を形成することが開示されている。この金属膜は、はんだによりヒートシンクと接合されている。そして、金属膜とヒートシンクの距離や相対位置を制御することで、金属膜の外縁部に応力が集中することを防止している。
日本特開２００８－１８２０７４号公報 日本特開２００８－２４４０４５号公報
　半導体素子を有する半導体装置において、半導体素子の電流が流れる部分は温度サイクルによる熱ストレスを受ける。このような熱ストレス環境下において、特許文献１の半導体装置のようにはんだと半導体素子電極が接していると、はんだと半導体素子電極の線膨張係数の差により熱応力が発生し半導体素子電極に亀裂を生じさせる問題があった。　
　また、特許文献２に開示の技術では、金属膜とヒートシンクの距離や相対位置を精密に制御する必要があるため、生産性が低い問題があった。
　本発明は上述の問題を解決するためになされたものであり、簡単な方法で、はんだからからの応力で電極に亀裂が生じることを抑制できる半導体装置とその半導体装置の製造方法を提供することを目的とする。
　本願の発明にかかる半導体装置は、半導体素子と、該半導体素子の表面に形成された表面電極と、該表面電極上に、接合部と、該接合部と接しつつ該接合部を囲むように形成された応力緩和部とを有するように形成された金属膜と、該応力緩和部を避けて該接合部に接合されたはんだと、該はんだを介して該接合部に接合された外部電極と、を備えたことを特徴とする。
　本願の発明にかかる半導体装置の製造方法は、半導体素子に表面電極を形成する工程と、該表面電極の上に金属膜を形成する工程と、該金属膜の外周部分を避けて該金属膜の中央部にはんだを形成し、該はんだを介して該金属膜と外部電極を接合する接合工程と、を備えたことを特徴とする。
　本発明のその他の特徴は以下に明らかにする。
　この発明によれば、応力緩和部がはんだからの応力を分散させるので電極に亀裂が生じることを抑制できる。
本発明の実施の形態１に係る半導体装置の断面図である。 表面電極、被覆膜、及びはんだの平面図である。 金属膜とはんだの平面図である。 金属膜の外周部分とその周辺の拡大図である。 半導体素子に表面電極を形成したことを示す断面図である。 表面電極の一部にレジストを形成したことを示す断面図である。 金属膜を形成したことを示す断面図である。 レジストを除去したことを示す断面図である。 金属膜の外周部分を被覆膜で覆ったことを示す断面図である。 接合工程で外部電極を接合部にはんだ付けしたことを示す断面図である。 金属膜の膜厚が０．５μｍの場合の金属膜内の応力分布を示す図である。 金属膜の膜厚が１．０μｍの場合の金属膜内の応力分布を示す図である。 金属膜の膜厚が１．５μｍの場合の金属膜内の応力分布を示す図である。 金属膜の厚さと金属膜に発生する応力の関係を示すグラフである。 本発明の実施の形態２に係る半導体装置の金属膜の外周部分とその周辺の断面図である。 金属膜の上に犠牲保護膜を形成したことを示す断面図である。 金属膜の外周部分の酸化防止膜を除去したことを示す断面図である。 改質膜を形成したことを示す断面図である。
　本発明の実施の形態に係る半導体装置と半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、本発明の実施の形態１に係る半導体装置の断面図である。半導体装置１０は、金属で形成されたベース板１２を備えている。ベース板１２の上方には縦型のＩＧＢＴで形成された半導体素子１４が配置されている。半導体素子１４の上面側にはゲート電極１４ａとエミッタ電極（以後、エミッタ電極は表面電極１４ｂという）が形成されている。半導体素子１４の下面側にはコレクタ電極１４ｃが形成されている。ゲート電極１４ａ、及び表面電極１４ｂは、アルミを９５％以上含む材料で形成されている。コレクタ電極１４ｃは、はんだとの接合性を確保するための積層金属膜により形成されている。コレクタ電極１４ｃの積層金属膜は、半導体素子１４側から順にＴｉ／Ｎｉ／Ａｕ、又はＡｌＳｉ／Ｔｉ／Ｎｉ／Ａｕなどにより構成されている。コレクタ電極１４ｃははんだ１６によりベース板１２に固定されている。
　表面電極１４ｂの上には金属膜２０が形成されている。金属膜２０は、金属膜２０の上面の一部を露出させるようにして被覆膜２２に覆われている。金属膜２０のうち被覆膜２２から露出した部分には、ＳｎＡｇＣｕ系のＰｂフリーはんだで形成されたはんだ３０が接合されている。はんだ３０は半導体装置１０の外部に伸びる外部電極３２と金属膜２０を接合している。
　ベース板１２にははんだ４０により外部電極４２が接合されている。ゲート電極１４ａにはワイヤ５０が接続されている。ワイヤ５０は、外部に伸びる外部電極５２とゲート電極１４ａとを接続している。ベース板１２の下面側には絶縁シート６０が貼り付けられている。上記した各構成要素は、外部電極３２、４２、５２、及び絶縁シート６０の下面側を外部に露出させる封止材７０によって覆われている。
　図２は、表面電極、被覆膜、及びはんだの平面図である。はんだ３０は被覆膜２２によって囲まれている。図３は、金属膜とはんだの平面図である。はんだ３０は金属膜２０の中央部のみに形成されている。そのため、金属膜２０の外周部分にははんだ３０が形成されていない。
　図４は、金属膜の外周部分とその周辺の拡大図である。金属膜２０は、接合部２０Ａと、接合部２０Ａと接しつつ接合部２０Ａを囲むように形成された応力緩和部２０Ｂとを有している。応力緩和部２０Ｂとは、図３の金属膜２０の外周部分のことである。まず、図４を参照して、接合部２０Ａについて説明する。接合部２０Ａは、表面電極１４ｂの上にＴｉ又はＭｏで形成された第１密着膜２０ａを有している。さらに、接合部２０Ａは第１密着膜２０ａの上にＮｉで形成された第１接合膜２０ｂを有している。さらに、接合部２０Ａは第１接合膜２０ｂの上に形成されたはんだとＮｉの合金部２０ｃを有している。
　次いで、応力緩和部２０Ｂについて説明する。応力緩和部２０Ｂは、表面電極１４ｂの上にＴｉ又はＭｏで形成された第２密着膜２０ｄを有している。さらに、応力緩和部２０Ｂは第２密着膜２０ｄの上にＮｉで形成された第２接合膜２０ｅを有している。さらに、応力緩和部２０Ｂは第２接合膜２０ｅの上にＡｕ又はＡｇで形成された酸化防止膜２０ｆを有している。第１接合膜２０ｂは第２接合膜２０ｅより薄く形成されている。第１接合膜２０ｂの厚さは０．５μｍ以上とすることが好ましい。応力緩和部２０Ｂは、接合部２０Ａと接する部分から最外周部までの長さ（長さａ）が１０μｍ以上となるように形成されている。
　接合部２０Ａの上面にははんだ３０が接合されている。このはんだ３０を介して接合部２０Ａに外部電極３２が接合されている。はんだ３０は応力緩和部２０Ｂを避けて接合部２０Ａに接合されている。はんだ３０が応力緩和部２０Ｂに接しないように、応力緩和部２０Ｂを覆う被覆膜２２が形成されている。被覆膜２２は、厚さが２～２０μｍのいずれかのポリイミドで形成されることが好ましい。
　次いで、本発明の実施の形態１に係る半導体装置の製造方法について説明する。まず、半導体素子に表面電極１４ｂを形成する。図５は、半導体素子に表面電極を形成したことを示す断面図である。表面電極１４ｂは、例えばＡｌ、ＡｌＳｉ、又はＡｌＣｕをスパッタリング法により形成する。その後、表面電極１４ｂを水素又は窒素雰囲気内において４００～４７０℃で加熱する。この熱処理により表面電極１４ｂの結晶サイズが拡大し表面電極１４ｂの平坦性が向上する。よって表面電極１４ｂに対する金属膜２０のカバレッジを向上させることができる。
　次いで、表面電極１４ｂの一部にレジストを形成する。図６は、表面電極の一部にレジストを形成したことを示す断面図である。レジスト１００は、表面電極１４ｂのうち金属膜を形成したくない領域を被覆するようにリソグラフィー法などで形成する。
　次いで、表面電極１４ｂ及びレジスト１００の上に金属膜を形成する。図７は、金属膜を形成したことを示す断面図である。金属膜は、表面電極１４ｂ側から、Ｔｉ又はＭｏで形成された密着膜２０ｇ、密着膜２０ｇの上にＮｉで形成された接合膜２０ｈ、接合膜２０ｈの上にＡｕ又はＡｇで形成された酸化防止膜２０ｉを有している。密着膜２０ｇ、接合膜２０ｈ、及び酸化防止膜２０ｉはスパッタ法などで形成する。
　密着膜２０ｇ、接合膜２０ｈ、及び酸化防止膜２０ｉのうち、はんだと適切な化合物膜を形成しかつはんだによる過剰侵食に対するバリアとして機能する接合膜２０ｈの厚みがもっとも厚くなっている。実質的に、接合膜２０ｈ（半導体装置１０の第１接合膜２０ｂと第２接合膜２０ｅ）が金属膜２０の機械的な強度を決定する。
　酸化防止膜２０ｉは、Ｎｉで形成された接合膜２０ｈが酸化されて接合膜２０ｈのはんだ濡れ性が低下するのを抑制するために形成されている。ここで、表面電極１４ｂ上に形成された金属膜のうちレジスト１００と接触する部分は、ミクロに見た場合組織が入り混じっていたり、膜厚が所望値からずれたりする場合があり、強度が相対的に弱い部分となっている。
　次いで、レジスト１００を除去する。図８は、レジストを除去したことを示す断面図である。この工程では、レジスト除去用の薬液にレジスト１００を浸漬し、レジスト１００及びその上の金属膜を除去する。こうして、表面電極１４ｂ上の所望領域に金属膜を形成する。
　次いで、金属膜の外周部分を被覆膜２２で覆う。外周部分とは将来応力緩和部となる部分である。図９は、金属膜の外周部分を被覆膜で覆ったことを示す断面図である。被覆膜２２は、感光性ポリイミドを用いてリソグラフィー法により形成する。あるいは、非感光性ポリイミドと感光性レジストを併用してもよい。この場合、リソグラフィー法で感光性レジストを所望の形状に加工した後に非感光性ポリイミドを加工する。被覆膜２２は２～２０μｍ程度の膜厚となるように形成する。
　次いで、接合工程を実施する。図１０は、接合工程で外部電極を接合部にはんだ付けしたことを示す断面図である。接合工程では、例えば外部電極３２に設けられた貫通口から接合部２０Ａへ溶融はんだを滴下し、はんだ３０を介して外部電極３２と接合部２０Ａを接合する。このとき、金属膜２０の外周部分には被覆膜２２が形成されているので、はんだはこの外周部分を避けて金属膜２０の中央部に形成される。つまり、被覆膜２２によりはんだの濡れ広がりを防止する。金属膜２０のうち、はんだが形成される部分は接合部２０Ａとなり、被覆膜２２に覆われてはんだが形成されない部分は応力緩和部２０Ｂになる。
　はんだの滴下を始めると、金属膜２０の中央部の酸化防止膜２０ｉはただちにはんだ中へ拡散する。その後、金属膜２０の中央部の接合膜２０ｈのＮｉとはんだが合金化反応しはんだとＮｉの合金部２０ｃを形成する。金属膜２０の中央部における接合膜２０ｈの膜厚は合金部２０ｃの分（たとえば０．３μｍ程度）だけ減少する。そしてこの膜厚が減少した部分は第１接合膜２０ｂである。なお、外部電極３２と金属膜を半田接合する方法としては、溶融はんだを用いる方法以外にも、例えば板半田を蟻酸雰囲気で溶融させる方法を採用してもよい。上記の各工程を終えると図１の半導体装置１０が完成する。
　半導体素子の冷熱サイクルが原因ではんだに高い応力が発生することがある。図１１－１３に、１２５℃まではんだを加熱しときの金属膜内応力分布の解析結果を示す。金属膜のうちはんだからの応力を支えるのは主として接合膜である。従って金属膜２０´を接合膜の材料であるＮｉのみで形成して解析モデルを構築した。また、応力緩和部は封止材７０に覆われることとした。
　図１１は、金属膜の膜厚が０．５μｍの場合の金属膜内の応力分布を示す図である。　図１２は、金属膜の膜厚が１．０μｍの場合の金属膜内の応力分布を示す図である。図１３は、金属膜の膜厚が１．５μｍの場合の金属膜内の応力分布を示す図である。これらの解析結果から、金属膜中では、主として接合部２０Ａ´の応力が高くなるものの、応力緩和部２０Ｂ´においてもはんだ３０端部から外側へ１０μｍ程度に渡り高い応力が発生することが分かる。本発明の実施の形態１に係る半導体装置によれば、応力緩和部２０Ｂは、接合部２０Ａと接する部分から最外周部までの長さ（ａ）が１０μｍ以上となるように形成されているので、金属膜２０に発生する応力が応力緩和部２０Ｂ中に分散される。よって、応力緩和部２０Ｂで十分にはんだの応力を緩和し表面電極１４ｂへ及ぶ応力を低減させることができる。
　ところで、図１１－１３から明らかなように、接合部２０Ａ´と応力緩和部２０Ｂ´では接合部２０Ａ´の方が大きな応力を負担することになる。従って、接合部２０Ａ´では金属膜の強度が均一かつ強い必要がある。しかし、前述したとおり、金属膜の最外周部はミクロに見た場合組織が入り混じっていたり、膜厚が所望値からずれたりする場合があり、金属膜の強度が相対的に弱い部分となっている。そこで、本発明の実施の形態１では、金属膜２０の強度が強い接合部２０Ａで主として応力を負担させつつ、金属膜の強度が弱い応力緩和部２０Ｂで補助的な応力緩和をすることで、優れた応力緩和効果を得るようにした。このようにすることで、はんだ３０による応力で金属膜２０が変形し表面電極１４ｂが挫屈したり引き剥がされたりして表面電極１４ｂに亀裂が進展することを抑制できる。
　応力緩和部２０Ｂの接合部２０Ａと接する部分から最外周部までの長さ（ａ）は、可能であれば５０～５００μｍのいずれかとすることが好ましい。５０μｍ以上に設定することで被覆膜２２と金属膜２０の位置及びパターンの制御性に対しマージンを確保でき、また簡易な検査でパターン異常を検知できる。また５００μｍ以下に設定することで、酸化防止膜２０ｆと被覆膜２２の密着性を確保できるので、接合工程を含むウエハプロセス中で被覆膜２２が金属膜２０から離脱することを防止できる。このように長さａを大きくすることは、半導体素子の使用温度が上がり、応力緩和部の応力の高い領域が拡大した場合にも応力緩和部で十分に応力を緩和するために有用である。
　図１４は、金属膜の厚さと金属膜に発生する応力の関係を示すグラフである。Ｎｉを用いた一般的なスパッタ法で金属膜を形成した場合、金属膜の降伏応力は４９０ＭＰａである。従って金属膜の応力は４９０ＭＰａ未満としなければならない。図１４から、金属膜の厚みが０．５μｍ以上のとき金属膜に発生する応力は４９０ＭＰａを下回ることが分かる。従って、金属膜の厚みを０．５μｍ以上とすると、金属膜内に発生する応力が金属膜の降伏応力を下回るのではんだからの応力で金属膜が変形せずはんだからの応力を支えきることができる。本発明の実施の形態１では、第１接合膜２０ｂの厚さを０．５μｍ以上としたので金属膜２０の変形を抑制できる。
　図１４から、金属膜の厚みが１μｍを超えると応力低減効果は飽和することが分かる。また、スパッタ法で３μｍ以上のＮｉを堆積させ形状を加工することは、一般的な半導体プロセスでは困難である。従って、機械的強度の確保と製造容易性の確保を考慮して、適切な金属膜の厚みを設定する必要がある。合金化反応により接合部２０Ａの第１接合膜２０ｂは０．３μｍ程度膜厚が減少する。従って、接合工程後の第１接合膜２０ｂを０．５μｍ以上とするためにはスパッタ法で形成する接合膜２０ｈの厚さは０．８μｍ以上とすることが望ましい。ただし、例えば接合膜２０ｈを無電解めっき法によるＮｉ－Ｐで形成する場合は、別途上記と同様の考察により最適な膜厚を定める。
　本発明の実施の形態１に係る半導体装置の製造方法によれば、応力緩和部２０Ｂを覆う被覆膜２２を形成した後に接合工程を実施するので、被覆膜２２によりはんだの濡れ広がりを阻止し「金属膜２０の中央部のみに」はんだ３０を形成できる。また、被覆膜２２に耐熱性が優れたポリイミドを用いることで、接合工程後のプロセスへの影響を回避できる。また、溶融したはんだの濡れ広がりを抑制するためには被覆膜２２の厚みを２～２０μｍのいずれかの値とすることが好ましい。
　本発明の実施の形態１に係る表面電極１４ｂはアルミを９５％以上含むので、Ｓｉ基板など各種半導体基板を用いた半導体素子の電極として容易に形成・加工でき、また金属ワイヤを接続する場合にも接合特性の優れたボンディングが可能となる。第１密着膜２０ａ及び第２密着膜２０ｄにＴｉ又はＭｏを用いたので、表面電極１４ｂと金属膜２０との密着性を確保しつつ、第１接合膜２０ｂと第２接合膜２０ｅのＮｉが表面電極１４ｂ側へ拡散することを防止できる。
　アルミを９５％以上含む表面電極１４ｂにＳｎＡｇＣｕ系のＰｂフリーはんだを接合することは一般に困難である。しかし本発明の実施の形態１に係る半導体装置によれば金属膜２０にはんだ３０を接合するのではんだ３０と金属膜２０の間で良好な接合性とはんだ濡れ性を確保できる。
　本発明の実施の形態１では表面電極１４ｂはエミッタ電極であるとしたが、本発明はこれに限定されない。半導体素子１４の表面に形成された表面電極に上記の金属膜２０及び被覆膜２２を形成すれば表面電極の亀裂を抑制できる。従って表面電極は、半導体素子１４に形成された電極であれば特に限定されない。また、半導体素子１４はＩＧＢＴに限定されず、例えばＭＯＳＦＥＴ又はダイオードなどでもよい。金属膜２０は３層構造でなくてもよく、例えばめっき成長させたＮｉ－Ｐを用いることもできる。なお、これらの変形は、以下の実施の形態に係る半導体装置と半導体装置の製造方法にも応用できる。
実施の形態２．
　本発明の実施の形態２に係る半導体装置と半導体装置の製造方法は、実施の形態１と一致する点が多いので、実施の形態１との相違点を中心に説明する。図１５は、本発明の実施の形態２に係る半導体装置の金属膜の外周部分とその周辺の断面図である。本発明の実施の形態２に係る半導体装置は、応力緩和部２０Ｃの表面に改質膜２００が形成されていることを特徴とする。
　改質膜２００は、はんだ３０が応力緩和部２０Ｃの直上領域に濡れ広がらないように、接合部２０Ａの表面部分よりもはんだが付きにくい材料で形成されている。より具体的には、改質膜２００はＮｉを酸化した金属酸化膜で形成されている。改質膜２００は、接合部２０Ａと接する部分から端部までの長さ（ａ）が１０μｍ以上となっている。また、応力緩和部２０Ｃの接合部２０Ａと接する部分から最外周部までの長さ（ａ）も１０μｍ以上となっている。なお、図１５のａで示される長さは１００～１０００μｍのいずれかであることが好ましい。
　本発明の実施の形態２に係る半導体装置の製造方法を説明する。金属膜２０を形成した後に、犠牲保護膜を形成する。図１６は、金属膜の上に犠牲保護膜を形成したことを示す断面図である。犠牲保護膜２０２は、金属膜２０の中央部にのみ形成され、金属膜の外周部分には形成しない。犠牲保護膜２０２は、例えば感光性レジストとリソグラフィー法を用いて形成することができる。
　次いで、金属膜の外周部分の酸化防止膜を除去する。図１７は、金属膜の外周部分の酸化防止膜を除去したことを示す断面図である。酸化防止膜は、例えばＡｒプラズマによるスパッタエッチング、又はＡｒイオンビームミリングなどのドライエッチングプロセスにより除去する。
　次いで、犠牲保護膜２０２を除去し、金属膜の外周部分の表面に改質膜を形成する。図１８は、改質膜を形成したことを示す断面図である。改質膜２００は、酸素プラズマアッシングなどにより接合膜２０ｈが酸化された金属酸化膜である。改質膜２００は、接合膜２０ｈを選択的に酸化させることで容易に形成できる。また、犠牲保護膜２０２を除去するために有機溶剤などによるウェットエッチングを用いる場合は、乾燥後に接合膜２０ｈにＵＶ光などを照射することで改質膜２００を作ることができる。
　次いで、接合工程を行う。接合工程の詳細は実施の形態１と同様である。このように、接合工程の前に金属膜の外周部分に中央部よりはんだが付きにくい改質膜２００を形成することで、接合工程においてはんだが外周部分へ濡れ広がることを防止できる。よって、改質膜２００を形成した部分を応力緩和部２０Ｃとすることができる。
　本発明の実施の形態２に係る半導体装置の製造方法によれば、改質膜２００によりはんだ３０の濡れ広がりを防止し、応力緩和部２０Ｃを形成することができる。改質膜２００は、接合膜２０ｈを酸化するだけで容易に形成できる。改質膜２００の、接合部２０Ａと接する部分から端部までの長さ（ａ）を１００～１０００μｍのいずれかとしたのは以下の理由による。１００μｍ以上に設定することで濡れ性の悪い改質膜２００へはんだが濡れ広がらないように十分なマージンを確保することができる。１０００μｍを越えないようにすることで、十分な面積のはんだ－表面電極接合部を確保でき、はんだ強度と大電流通電性能を維持できる。
　改質膜２００は、Ｎｉを酸化した金属酸化膜に限らず、接合工程におけるはんだの濡れ広がりを抑制できる膜であれば特に限定されない。また、応力緩和部に酸化防止膜を形成しないプロセスを採用すれば、酸化防止膜を除去する工程を省略できる。
　本発明の実施の形態１では被覆膜２２を用い、本発明の実施の形態２では改質膜２００を用いてはんだの濡れ広がりを防止した。しかし、被覆膜２２又は改質膜２００以外の手段で、金属膜の中央部にのみはんだを形成しても応力緩和部を形成することができる。従って、はんだの濡れ広がりを防止できる限り、被覆膜２２又は改質膜２００以外の手段を用いても良い。
　１０　半導体装置、　１２　ベース板、　１４　半導体素子、　１４ａ　ゲート電極、　１４ｂ　表面電極、　１４ｃ　コレクタ電極、　１６，３０　はんだ、　２０　金属膜、　２０Ａ　接合部、　２０Ｂ，２０Ｃ　応力緩和部、　２０ａ　第１密着膜、　２０ｂ　第１接合膜、　２０ｃ　合金部、　２０ｄ　第２密着膜、　２０ｅ　第２接合膜、　２０ｆ　酸化防止膜、　２０ｇ　密着膜、　２０ｈ　接合膜、　２０ｉ　酸化防止膜、　２２　被覆膜、　３２，４２，５２　外部電極、　５０　ワイヤ、　６０　絶縁シート、　７０　封止材、　１００　レジスト、　２００　改質膜、　２０２　犠牲保護膜

Claims (12)

  1. 　半導体素子と、
    　前記半導体素子の表面に形成された表面電極と、
    　前記表面電極上に、接合部と、前記接合部と接しつつ前記接合部を囲むように形成された応力緩和部とを有するように形成された金属膜と、
    　前記応力緩和部を避けて前記接合部に接合されたはんだと、
    　前記はんだを介して前記接合部に接合された外部電極と、を備えたことを特徴とする半導体装置。
  2. 　前記応力緩和部は、前記接合部と接する部分から最外周部までの長さが１０μｍ以上となるように形成されたことを特徴とする請求項１に記載の半導体装置。
  3. 　前記接合部は、前記表面電極の上にＴｉ又はＭｏで形成された第１密着膜、前記第１密着膜の上にＮｉで形成された第１接合膜、及び前記第１接合膜の上に形成された前記はんだとＮｉの合金部を有し
    　前記応力緩和部は、前記表面電極の上にＴｉ又はＭｏで形成された第２密着膜、前記第２密着膜の上にＮｉで形成された第２接合膜、及び前記第２接合膜の上にＡｕ又はＡｇで形成された酸化防止膜を有し、
    　前記第１接合膜は前記第２接合膜より薄く形成され、
    　前記第１接合膜の厚さは０．５μｍ以上であることを特徴とする請求項１又は２に記載の半導体装置。
  4. 　前記はんだが前記応力緩和部に接しないように、前記応力緩和部を覆う被覆膜を備えたことを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。
  5. 　前記被覆膜は、厚さが２～２０μｍのいずれかのポリイミドで形成されたことを特徴とする請求項４に記載の半導体装置。
  6. 　前記はんだが前記応力緩和部の直上領域に濡れ広がらないように、前記応力緩和部の表面に前記接合部の表面部分よりも前記はんだが付きにくい材料で形成された改質膜を備えたことを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。
  7. 　前記改質膜は、前記接合部と接する部分から端部までの長さが１００～１０００μｍのいずれかであることを特徴とする請求項６に記載の半導体装置。
  8. 　前記改質膜は金属酸化膜で形成されたことを特徴とする請求項６又は７に記載の半導体装置。
  9. 　前記表面電極は、アルミを９５％以上含む材料で形成されたことを特徴とする請求項１乃至８のいずれか１項に記載の半導体装置。
  10. 　半導体素子に表面電極を形成する工程と、
    　前記表面電極の上に金属膜を形成する工程と、
    　前記金属膜の外周部分を避けて前記金属膜の中央部にはんだを形成し、前記はんだを介して前記金属膜と外部電極を接合する接合工程と、を備えたことを特徴とする半導体装置の製造方法。
  11. 　前記接合工程の前に、前記外周部分を被覆膜で覆う工程を備えたことを特徴とする請求項１０に記載の半導体装置の製造方法。
  12. 　前記接合工程の前に、前記外周部分に前記中央部より前記はんだが付きにくい改質膜を形成する工程を備えたことを特徴とする請求項１０に記載の半導体装置の製造方法。
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JP2020009823A (ja) * 2018-07-04 2020-01-16 三菱電機株式会社 半導体装置及び半導体装置の製造方法
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