CN104603921B - 半导体装置、半导体装置的制造方法 - Google Patents
半导体装置、半导体装置的制造方法 Download PDFInfo
- Publication number
- CN104603921B CN104603921B CN201280075614.5A CN201280075614A CN104603921B CN 104603921 B CN104603921 B CN 104603921B CN 201280075614 A CN201280075614 A CN 201280075614A CN 104603921 B CN104603921 B CN 104603921B
- Authority
- CN
- China
- Prior art keywords
- film
- solder
- metal film
- semiconductor device
- surface electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16113—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/07—Polyamine or polyimide
- H01L2924/07025—Polyimide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20641—Length ranges larger or equal to 100 microns less than 200 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20642—Length ranges larger or equal to 200 microns less than 300 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20643—Length ranges larger or equal to 300 microns less than 400 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20644—Length ranges larger or equal to 400 microns less than 500 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20645—Length ranges larger or equal to 500 microns less than 600 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20646—Length ranges larger or equal to 600 microns less than 700 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20647—Length ranges larger or equal to 700 microns less than 800 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20648—Length ranges larger or equal to 800 microns less than 900 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/20649—Length ranges larger or equal to 900 microns less than 1000 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/2065—Length ranges larger or equal to 1000 microns less than 1500 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
本申请的发明所涉及的半导体装置,其特征在于,具有:半导体元件;表面电极,其形成在该半导体元件的表面;金属膜,其形成在该表面电极上,具有接合部、以及以与该接合部接触并且包围该接合部的方式形成的应力缓和部;焊料,其避开该应力缓和部而与该接合部接合;以及外部电极,其经由该焊料而与该接合部接合。
Description
技术领域
本发明涉及一种在大电流的通断等中使用的半导体装置及该半导体装置的制造方法。
背景技术
在专利文献1中,公开有一种通过焊料将作为铜板的外部电极和半导体元件电极直接接合的半导体装置。通过焊料将外部电极和半导体元件电极直接接合的目的在于,降低电阻并且实现能够进行大电流通电的配线连接。
在专利文献2中,公开有一种在半导体元件电极(发射极电极)的一部分形成与焊料的接合性良好的金属膜(镀敷电极)的技术。该金属膜通过焊料与散热器接合。而且,通过控制金属膜和散热器的距离、相对位置,从而防止应力向金属膜的外缘部集中。
专利文献1:日本特开2008-182074号公报
专利文献2:日本特开2008-244045号公报
发明内容
在具有半导体元件的半导体装置中,半导体元件的流过电流的部分受到由温度循环而产生的热应力。在上述的热应力环境下,如果如专利文献1的半导体装置那样,焊料和半导体元件电极相接触,则存在下述问题,即,由于焊料和半导体元件电极的线膨胀系数的差而产生热应力,使半导体元件电极中产生龟裂。
另外,在专利文献2所公开的技术中存在下述问题,即,由于需要对金属膜和散热器的距离、相对位置进行精密的控制,因此生产率较低。
本发明就是为了解决上述问题而提出的,其目的在于提供一种半导体装置及该半导体装置的制造方法,能够通过简单的方法抑制因来自焊料的应力而在电极中产生龟裂。
本申请的发明所涉及的半导体装置,其特征在于,具有:半导体元件;表面电极,其形成在该半导体元件的表面;金属膜,其形成在该表面电极上,具有接合部、以及以与该接合部接触并且包围该接合部的方式形成的应力缓和部;焊料,其避开该应力缓和部而与该接合部接合;以及外部电极,其经由该焊料而与该接合部接合。
本申请的发明所涉及的半导体装置的制造方法,其特征在于,具有:在半导体元件上形成表面电极的工序;在该表面电极上形成金属膜的工序;以及避开该金属膜的外周部分而在该金属膜的中央部形成焊料,并经由该焊料将该金属膜和外部电极接合的接合工序。
本发明的其他特征在以下部分得以明确。
发明的效果
根据本发明,由于应力缓和部使来自焊料的应力分散,因此能够抑制在电极中产生龟裂。
附图说明
图1是本发明的实施方式1所涉及的半导体装置的剖面图。
图2是表面电极、包覆膜以及焊料的俯视图。
图3是金属膜和焊料的俯视图。
图4是金属膜的外周部分及其周边的放大图。
图5是表示在半导体元件上形成表面电极后的剖面图。
图6是表示在表面电极的一部分处形成抗蚀层后的剖面图。
图7是表示形成金属膜后的剖面图。
图8是表示去除抗蚀层后的剖面图。
图9是表示利用包覆膜覆盖金属膜的外周部分后的剖面图。
图10是表示在接合工序中将外部电极软钎焊至接合部后的剖面图。
图11是表示在金属膜的膜厚为0.5μm的情况下的金属膜内的应力分布的图。
图12是表示在金属膜的膜厚为1.0μm的情况下的金属膜内的应力分布的图。
图13是表示在金属膜的膜厚为2.0μm的情况下的金属膜内的应力分布的图。
图14是表示金属膜的厚度和在金属膜中产生的应力的关系的图表。
图15是本发明的实施方式2所涉及的半导体装置的金属膜的外周部分及其周边的剖面图。
图16是表示在金属膜上形成牺牲保护膜后的剖面图。
图17是表示去除金属膜的外周部分的防氧化膜后的剖面图。
图18是表示形成改质膜后的剖面图。
具体实施方式
参照附图,对本发明的实施方式所涉及的半导体装置和半导体装置的制造方法进行说明。有时对相同或对应的构成要素标注相同的标号,省略重复说明。
实施方式1.
图1是本发明的实施方式1所涉及的半导体装置的剖面图。半导体装置10具有由金属形成的基座板12。在基座板12的上方配置有由纵向型的IGBT形成的半导体元件14。在半导体元件14的上表面侧形成有栅极电极14a和发射极电极(以后,发射极电极称为表面电极14b)。在半导体元件14的下表面侧形成有集电极电极14c。栅极电极14a以及表面电极14b由含有大于或等于95%的铝的材料形成。集电极电极14c由用于确保与焊料的接合性的层叠金属膜形成。集电极电极14c的层叠金属膜从半导体元件14侧依次由Ti/Ni/Au、或AlSi/Ti/Ni/Au等构成。集电极电极14c通过焊料16固定于基座板12。
在表面电极14b上形成有金属膜20。金属膜20以使金属膜20的上表面的一部分露出的方式被包覆膜22覆盖。在金属膜20中的从包覆膜22露出的部分处接合有由SnAgCu类的无铅焊料形成的焊料30。焊料30将向半导体装置10的外部伸出的外部电极32和金属膜20接合。
在基座板12上通过焊料40接合有外部电极42。在栅极电极14a上连接有导线50。导线50将向外部伸出的外部电极52和栅极电极14a连接。在基座板12的下表面侧粘贴有绝缘片60。上述的各结构要素由封装材料70覆盖,该封装材料70使外部电极32、42、52以及绝缘片60的下表面侧向外部露出。
图2是表面电极、包覆膜以及焊料的俯视图。焊料30由包覆膜22包围。图3是金属膜和焊料的俯视图。焊料30仅形成在金属膜20的中央部。因此,在金属膜20的外周部分处没有形成焊料30。
图4是金属膜的外周部分及其周边的放大图。金属膜20具有接合部20A以及应力缓和部20B,该应力缓和部20B以与接合部20A接触并且包围接合部20A的方式形成。所谓应力缓和部20B是指图3的金属膜20的外周部分。首先,参照图4对接合部20A进行说明。接合部20A具有在表面电极14b上由Ti或Mo形成的第1密接膜20a。并且,接合部20A具有在第1密接膜20a上由Ni形成的第1接合膜20b。并且,接合部20A具有在第1接合膜20b上形成的焊料和Ni的合金部20c。
下面,对应力缓和部20B进行说明。应力缓和部20B具有在表面电极14b上由Ti或Mo形成的第2密接膜20d。并且,应力缓和部20B具有在第2密接膜20d上由Ni形成的第2接合膜20e。并且,应力缓和部20B具有在第2接合膜20e上由Au或Ag形成的防氧化膜20f。第1接合膜20b与第2接合膜20e相比形成得较薄。优选将第1接合膜20b的厚度设为大于或等于0.5μm。应力缓和部20B形成为,从与接合部20A接触的部分至最外周部为止的长度(长度a)大于或等于10μm。
在接合部20A的上表面接合有焊料30。外部电极32经由该焊料30与接合部20A接合。焊料30避开应力缓和部20B与接合部20A接合。形成有覆盖应力缓和部20B的包覆膜22,以使得焊料30不与应力缓和部20B接触。包覆膜22优选由厚度为2~20μm中的某一值的聚酰亚胺形成。
下面,对本发明的实施方式1所涉及的半导体装置的制造方法进行说明。首先,在半导体元件上形成表面电极14b。图5是表示在半导体元件上形成表面电极后的剖面图。表面电极14b是例如通过溅射法利用Al、AlSi、或AlCu而形成的。然后,将表面电极14b在氢气或氮气气氛内以400~470℃加热。通过该热处理,表面电极14b的晶体尺寸扩大,表面电极14b的平坦性提高。由此,能够使金属膜20相对于表面电极14b的覆盖率提高。
然后,在表面电极14b的一部分处形成抗蚀层。图6是表示在表面电极的一部分处形成抗蚀层后的剖面图。抗蚀层100是以对表面电极14b中的不希望形成金属膜的区域进行覆盖的方式通过光刻法等形成的。
然后,在表面电极14b以及抗蚀层100上形成金属膜。图7是表示形成金属膜后的剖面图。金属膜从表面电极14b侧起,具有由Ti或Mo形成的密接膜20g、在密接膜20g上由Ni形成的接合膜20h、以及在接合膜20h上由Au或Ag形成的防氧化膜20i。密接膜20g、接合膜20h以及防氧化膜20i是通过溅射法等形成的。
在密接膜20g、接合膜20h以及防氧化膜20i中,接合膜20h的厚度最厚,该接合膜20h与焊料形成适当的化合物膜且作为应对由焊料引起的过量侵蚀的阻挡层起作用。实质上,接合膜20h(半导体装置10的第1接合膜20b和第2接合膜20e)决定金属膜20的机械强度。
形成有防氧化膜20i的目的在于,对由Ni形成的接合膜20h被氧化而导致接合膜20h的焊料浸润性下降进行抑制。在此,在表面电极14b上形成的金属膜中的与抗蚀层100接触的部分,有时在微观观察的情况下组织相混合,或膜厚偏离期望值,成为强度相对较弱的部分。
然后,去除抗蚀层100。图8是表示去除抗蚀层后的剖面图。在该工序中,将抗蚀层100浸渍在抗蚀层去除用的药液中,去除抗蚀层100及其上的金属膜。这样,在表面电极14b上的期望区域中形成金属膜。
然后,利用包覆膜22覆盖金属膜的外周部分。所谓外周部分是指将来成为应力缓和部的部分。图9是表示利用包覆膜覆盖金属膜的外周部分后的剖面图。包覆膜22是使用感光性聚酰亚胺通过光刻法形成的。或者,也可以同时使用非感光性聚酰亚胺和感光性抗蚀层。在该情况下,在通过光刻法将感光性抗蚀层加工成期望的形状后,对非感光性聚酰亚胺进行加工。包覆膜22形成为2~20μm左右的膜厚。
然后,实施接合工序。图10是表示在接合工序中将外部电极软钎焊至接合部后的剖面图。在接合工序中,例如将熔融焊料从设置于外部电极32的贯穿口向接合部20A滴下,经由焊料30将外部电极32和接合部20A接合。此时,由于在金属膜20的外周部分处形成有包覆膜22,因此,焊料避开该外周部分而形成在金属膜20的中央部。即,利用包覆膜22防止焊料的浸润扩展。在金属膜20中,用于形成焊料的部分成为接合部20A,被包覆膜22覆盖而没有形成焊料的部分成为应力缓和部20B。
如果开始滴下焊料,则金属膜20的中央部的防氧化膜20i立即向焊料中扩散。然后,金属膜20的中央部的接合膜20h的Ni和焊料发生合金化反应,形成焊料和Ni的合金部20c。金属膜20的中央部中的接合膜20h的膜厚减少与合金部20c对应的量(例如0.3μm左右)。而且,该膜厚减少后的部分是第1接合膜20b。此外,作为将外部电极32和金属膜进行焊料接合的方法,除了使用熔融焊料的方法以外,也可以采用例如使板焊料在甲酸气氛中熔融的方法。如果结束上述的各工序,则图1的半导体装置10完成。
有时由于半导体元件的冷热循环的原因而在焊料中产生较高的应力。在图11-13中表示将焊料加热至125℃时的金属膜内应力分布的解析结果。金属膜中承受来自焊料的应力的部位主要是接合膜。因此,仅由作为接合膜的材料的Ni形成金属膜20’而构筑出解析模型。另外,使应力缓和部被封装材料70覆盖。
图11是表示在金属膜的膜厚为0.5μm的情况下的金属膜内的应力分布的图。图12是表示在金属膜的膜厚为1.0μm的情况下的金属膜内的应力分布的图。图13是表示在金属膜的膜厚为2.0μm的情况下的金属膜内的应力分布的图。从这些解析结果可知,在金属膜中,虽然主要是接合部20A’的应力变高,但在应力缓和部20B’中,在从焊料30端部向外侧延伸10μm左右的区域中也产生较高的应力。根据本发明的实施方式1所涉及的半导体装置,应力缓和部20B形成为从与接合部20A接触的部分至最外周部的长度(a)大于或等于10μm,因此金属膜20处产生的应力在应力缓和部20B中分散。由此,通过应力缓和部20B能够充分地缓和焊料的应力,减小到达表面电极14b的应力。
另外,根据图11-13明确可知,在接合部20A’和应力缓和部20B’中,接合部20A’承担较大的应力。因此,在接合部20A’中需要金属膜的强度均匀且较强。但是,如前述那样,金属膜的最外周部有时在微观观察的情况下组织相混合,或膜厚偏离期望值,成为金属膜的强度相对较弱的部分。因此,在本发明的实施方式1中,通过主要利用金属膜20的强度较强的接合部20A承担应力,并且利用金属膜的强度较弱的应力缓和部20B进行辅助的应力缓和,从而得到优异的应力缓和效果。由此,能够抑制以下现象,即,由于焊料30所引起的应力,金属膜20变形、表面电极14b弯曲或剥离而在表面电极14b中龟裂加深。
关于应力缓和部20B的从与接合部20A接触的部分至最外周部为止的长度(a),如果可能的话,优选设为50~500μm中的某一值。通过设定为大于或等于50μm,从而能够针对包覆膜22与金属膜20的位置以及图案的控制性而确保余量,另外,能够通过简单的检查对图案异常进行检测。另外,通过设定为小于或等于500μm,从而能够确保防氧化膜20f和包覆膜22的密接性,因此能够防止在包含接合工序在内的晶片工艺中包覆膜22从金属膜20脱离。如上所述,将长度a增大的作用在于,即使在半导体元件的使用温度上升、应力缓和部的应力较高的区域扩大的情况下,也利用应力缓和部充分地缓和应力。
图14是表示金属膜的厚度和在金属膜中产生的应力的关系的图表。在通过通常的溅射法使用Ni而形成金属膜的情况下,金属膜的屈服应力为490MPa。因此,必须使金属膜的应力小于490MPa。从图14可知,在金属膜的厚度为大于或等于0.5μm时在金属膜中产生的应力低于490MPa。因此,如果将金属膜的厚度设为大于或等于0.5μm,则在金属膜内产生的应力低于金属膜的屈服应力,因此,能够承受来自焊料的应力而不会因来自焊料的应力使金属膜变形。在本发明的实施方式1中,由于将第1接合膜20b的厚度设为大于或等于0.5μm,因此能够抑制金属膜20的变形。
从图14可知,如果金属膜的厚度超过1μm,则应力减小效果饱和。另外,通过溅射法堆积大于或等于3μm的Ni而加工出形状,这对于通常的半导体工艺而言是困难的。因此,考虑到确保机械强度和确保制造容易性,需要设定适当的金属膜的厚度。通过合金化反应,接合部20A的第1接合膜20b的膜厚减少0.3μm左右。因此,为了将接合工序后的第1接合膜20b设为大于或等于0.5μm,优选将通过溅射法形成的接合膜20h的厚度设为大于或等于0.8μm。但是,例如在通过无电解镀法由Ni-P形成接合膜20h的情况下,通过与上述相同的考量而另外确定最佳的膜厚。
根据本发明的实施方式1所涉及的半导体装置的制造方法,在形成覆盖应力缓和部20B的包覆膜22后实施接合工序,因此,能够通过包覆膜22阻止焊料的浸润扩展并“仅在金属膜20的中央部”形成焊料30。另外,通过在包覆膜22中使用耐热性优异的聚酰亚胺,从而能够避免对接合工序后的工艺的影响。另外,为了抑制熔融的焊料的浸润扩展,优选将包覆膜22的厚度设为2~20μm中的某一值。
本发明的实施方式1所涉及的表面电极14b含有大于或等于95%的铝,因此,作为使用Si衬底等各种半导体衬底形成的半导体元件的电极,能够容易地进行形成、加工,另外,即使在连接金属导线的情况下,也能够实现接合特性优异的接合。在第1密接膜20a以及第2密接膜20d中使用了Ti或Mo,因此,能够确保表面电极14b和金属膜20的密接性,并且能够防止第1接合膜20b和第2接合膜20e的Ni向表面电极14b侧扩散。
将SnAgCu类的无铅焊料接合至含有大于或等于95%的铝的表面电极14b通常是困难的。但是,根据本发明的实施方式1所涉及的半导体装置,由于将焊料30接合至金属膜20,因此能够在焊料30和金属膜20之间确保良好的接合性和焊料浸润性。
在本发明的实施方式1中,使表面电极14b为发射极电极,但本发明并不限定于此。只要在形成于半导体元件14表面的表面电极上形成上述金属膜20以及包覆膜22,就能够抑制表面电极的龟裂。因此,表面电极只要是在半导体元件14上形成的电极即可,没有特别地限定。另外,半导体元件14并不限定于IGBT,也可以是例如MOSFET或二极管等。金属膜20也可以不是3层构造,例如也能够使用通过镀敷生长而成的Ni-P。此外,这些变形也能够应用于下面的实施方式所涉及的半导体装置和半导体装置的制造方法。
实施方式2.
本发明的实施方式2所涉及的半导体装置和半导体装置的制造方法,由于与实施方式1一致的部分较多,因此以与实施方式1的不同点为中心进行说明。图15是本发明的实施方式2所涉及的半导体装置的金属膜的外周部分及其周边的剖面图。本发明的实施方式2所涉及的半导体装置,其特征在于在应力缓和部20C的表面形成有改质膜200。
改质膜200由与接合部20A的表面部分相比焊料难以附着的材料形成,以使得焊料30不会向应力缓和部20C的正上方区域浸润扩展。更具体地说,改质膜200由将Ni氧化后而得到的金属氧化膜形成。改质膜200从与接合部20A接触的部分至端部为止的长度(a)大于或等于10μm。另外,应力缓和部20C的从与接合部20A接触的部分至最外周部为止的长度(a)也大于或等于10μm。此外,优选图15中的由a所示的长度为100~1000μm中的某一值。
对本发明的实施方式2所涉及的半导体装置的制造方法进行说明。在形成金属膜20后,形成牺牲保护膜。图16是表示在金属膜上形成牺牲保护膜后的剖面图。牺牲保护膜202仅形成在金属膜20的中央部,没有形成在金属膜的外周部分。牺牲保护膜202能够使用例如感光性抗蚀层和光刻法而形成。
然后,去除金属膜的外周部分的防氧化膜。图17是表示去除金属膜的外周部分的防氧化膜后的剖面图。防氧化膜通过例如由Ar等离子实现的溅射蚀刻、或Ar离子铣等干蚀刻工艺进行去除。
然后,去除牺牲保护膜202,在金属膜的外周部分的表面形成改质膜。图18是表示形成改质膜后的剖面图。改质膜200是通过氧等离子灰化等对接合膜20h进行氧化后而得到的金属氧化膜。通过对接合膜20h进行选择性的氧化,从而能够容易地形成改质膜200。另外,在为了去除牺牲保护膜202而使用由有机溶剂等进行的湿蚀刻的情况下,能够通过在干燥后向接合膜20h照射UV光等制作改质膜200。
然后,进行接合工序。接合工序的详细内容与实施方式1相同。如上所述,通过在接合工序前在金属膜的外周部分形成与中央部相比焊料难以附着的改质膜200,从而能够在接合工序中防止焊料向外周部分浸润扩展。由此,能够将形成有改质膜200的部分作为应力缓和部20C。
根据本发明的实施方式2所涉及的半导体装置的制造方法,能够通过改质膜200防止焊料30的浸润扩展,并形成应力缓和部20C。仅通过接合膜20h的氧化便能够容易地形成改质膜200。将改质膜200的从与接合部20A接触的部分至端部为止的长度(a)设为100~1000μm中的某一值的理由如下。通过设定为大于或等于100μm,从而能够确保充分的余量,以不会使焊料向浸润性较差的改质膜200浸润扩展。通过设为不超过1000μm,从而能够确保足够面积的焊料-表面电极接合部,能够维持焊料强度和大电流通电性能。
改质膜200并不限定于将Ni氧化后而得到的金属氧化膜,只要是能够对在接合工序中的焊料的浸润扩展进行抑制的膜即可,没有特别地限定。另外,如果采用在应力缓和部不形成防氧化膜的工艺,则能够省略去除防氧化膜的工序。
在本发明的实施方式1中使用包覆膜22,在本发明的实施方式2中使用改质膜200,防止焊料的浸润扩展。但是,利用除了包覆膜22或改质膜200以外的方法,仅在金属膜的中央部形成焊料,也能够形成应力缓和部。因此,只要能够防止焊料的浸润扩展,也可以使用除了包覆膜22或改质膜200以外的方法。
标号的说明
10半导体装置,12基座板,14半导体元件,14a栅极电极,14b表面电极,14c集电极电极,16、30焊料,20金属膜,20A接合部,20B、20C应力缓和部,20a第1密接膜,20b第1接合膜,20c合金部,20d第2密接膜,20e第2接合膜,20f防氧化膜,20g密接膜,20h接合膜,20i防氧化膜,22包覆膜,32、42、52外部电极,50导线,60绝缘片,70封装材料,100抗蚀层,200改质膜,202牺牲保护膜。
Claims (10)
1.一种半导体装置,其特征在于,具有:
半导体元件;
表面电极,其形成在所述半导体元件的表面;
金属膜,其形成在所述表面电极上,具有接合部、以及以与所述接合部接触并且包围所述接合部的方式形成的应力缓和部;
包覆膜,其覆盖所述应力缓和部;
焊料,其避开所述包覆膜而与所述接合部接合;以及
外部电极,其经由所述焊料而与所述接合部接合,
所述应力缓和部形成为,从与所述接合部接触的部分至最外周部为止的长度大于或等于10μm。
2.根据权利要求1所述的半导体装置,其特征在于,
所述接合部具有在所述表面电极上由Ti或Mo形成的第1密接膜、在所述第1密接膜上由Ni形成的第1接合膜、以及在所述第1接合膜上形成的所述焊料和Ni的合金部,
所述应力缓和部具有在所述表面电极上由Ti或Mo形成的第2密接膜、在所述第2密接膜上由Ni形成的第2接合膜、以及在所述第2接合膜上由Au或Ag形成的防氧化膜,
所述第1接合膜与所述第2接合膜相比形成得较薄,
所述第1接合膜的厚度为大于或等于0.5μm。
3.根据权利要求1所述的半导体装置,其特征在于,
所述包覆膜由厚度为2~20μm中的某一值的聚酰亚胺形成。
4.根据权利要求1所述的半导体装置,其特征在于,
所述表面电极由含有大于或等于95%的铝的材料形成。
5.一种半导体装置,其特征在于,具有:
半导体元件;
表面电极,其形成在所述半导体元件的表面;
金属膜,其形成在所述表面电极上,具有接合部、以及以与所述接合部接触并且包围所述接合部的方式形成的应力缓和部;
焊料,其避开所述应力缓和部而与所述接合部接合;以及
外部电极,其经由所述焊料而与所述接合部接合,
所述半导体装置具有改质膜,所述改质膜在所述应力缓和部的表面由与所述接合部的表面部分相比所述焊料难以附着的材料形成,以使得所述焊料不向所述应力缓和部的正上方区域浸润扩展,
所述改质膜的从与所述接合部接触的部分至端部为止的长度为100~1000μm中的某一值。
6.根据权利要求5所述的半导体装置,其特征在于,
所述改质膜由金属氧化膜形成。
7.一种半导体装置的制造方法,其特征在于,具有:
在半导体元件上形成表面电极的工序;
在所述表面电极上形成金属膜的工序;
利用包覆膜对所述金属膜的外周部分进行覆盖的工序;以及
避开所述包覆膜而在所述金属膜的中央部形成焊料,并经由所述焊料将所述金属膜和外部电极接合的接合工序,
所述外周部分形成为,从与所述中央部接触的部分至最外周部为止的长度大于或等于10μm。
8.根据权利要求7所述的半导体装置的制造方法,其特征在于,
所述包覆膜由聚酰亚胺形成。
9.一种半导体装置的制造方法,其特征在于,具有:
在半导体元件上形成表面电极的工序;
在所述表面电极上形成金属膜的工序;以及
避开所述金属膜的外周部分而在所述金属膜的中央部形成焊料,并经由所述焊料将所述金属膜和外部电极接合的接合工序,
所述半导体装置的制造方法具有在所述接合工序之前,在所述外周部分处形成与所述中央部相比所述焊料难以附着的改质膜的工序,
所述改质膜的从与所述中央部接触的部分至端部为止的长度为100~1000μm中的某一值。
10.一种半导体装置,其特征在于,具有:
半导体元件;
表面电极,其形成在所述半导体元件的表面;
金属膜,其形成在所述表面电极上,具有接合部、以及以与所述接合部接触并且包围所述接合部的方式形成的应力缓和部;
焊料,其避开所述应力缓和部而与所述接合部接合;以及
外部电极,其经由所述焊料而与所述接合部接合,
所述接合部具有在所述表面电极上由Ti或Mo形成的第1密接膜、在所述第1密接膜上由Ni形成的第1接合膜、以及在所述第1接合膜上形成的所述焊料和Ni的合金部,
所述应力缓和部具有在所述表面电极上由Ti或Mo形成的第2密接膜、在所述第2密接膜上由Ni形成的第2接合膜、以及在所述第2接合膜上由Au或Ag形成的防氧化膜,
所述第1接合膜与所述第2接合膜相比形成得较薄,
所述第1接合膜的厚度为大于或等于0.5μm。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2012/072476 WO2014037996A1 (ja) | 2012-09-04 | 2012-09-04 | 半導体装置、半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104603921A CN104603921A (zh) | 2015-05-06 |
CN104603921B true CN104603921B (zh) | 2018-07-24 |
Family
ID=50236649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201280075614.5A Active CN104603921B (zh) | 2012-09-04 | 2012-09-04 | 半导体装置、半导体装置的制造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9653390B2 (zh) |
JP (1) | JP6156381B2 (zh) |
KR (2) | KR20160132499A (zh) |
CN (1) | CN104603921B (zh) |
DE (1) | DE112012006875T5 (zh) |
WO (1) | WO2014037996A1 (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6264230B2 (ja) * | 2014-08-28 | 2018-01-24 | 三菱電機株式会社 | 半導体装置 |
US10181445B2 (en) * | 2014-12-29 | 2019-01-15 | Mitsubishi Electric Corporation | Power module |
US10727163B2 (en) * | 2016-07-26 | 2020-07-28 | Mitsubishi Electric Corporation | Semiconductor device |
DE102018101392A1 (de) * | 2017-01-24 | 2018-07-26 | Toyota Jidosha Kabushiki Kaisha | Halbleitereinrichtung und verfahren zum herstellen derselben |
JP6641526B2 (ja) * | 2017-03-27 | 2020-02-05 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
JP7005356B2 (ja) | 2018-01-19 | 2022-01-21 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP2020009823A (ja) | 2018-07-04 | 2020-01-16 | 三菱電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP6993946B2 (ja) * | 2018-08-21 | 2022-01-14 | 株式会社東芝 | 半導体素子 |
JP7472435B2 (ja) | 2019-05-13 | 2024-04-23 | 富士電機株式会社 | 半導体モジュールの製造方法 |
CN115552632A (zh) * | 2020-05-13 | 2022-12-30 | 三菱电机株式会社 | 半导体元件 |
JP2021007182A (ja) * | 2020-10-19 | 2021-01-21 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6191493B1 (en) * | 1993-02-18 | 2001-02-20 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package and manufacturing method of the same |
CN101567353A (zh) * | 2008-04-25 | 2009-10-28 | 三星电子株式会社 | 球栅阵列基板及其制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5891756A (en) * | 1997-06-27 | 1999-04-06 | Delco Electronics Corporation | Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby |
DE19750073A1 (de) | 1997-11-12 | 1999-05-20 | Bosch Gmbh Robert | Schaltungsträgerplatte |
JPH11284180A (ja) | 1998-03-30 | 1999-10-15 | Toshiba Corp | 半導体素子およびそれを用いた半導体装置 |
DE19839760A1 (de) * | 1998-09-01 | 2000-03-02 | Bosch Gmbh Robert | Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung |
US7276801B2 (en) * | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
JP2006049427A (ja) | 2004-08-02 | 2006-02-16 | Nec Electronics Corp | 半導体装置の製造方法 |
JP4455488B2 (ja) * | 2005-12-19 | 2010-04-21 | 三菱電機株式会社 | 半導体装置 |
JP4640345B2 (ja) | 2007-01-25 | 2011-03-02 | 三菱電機株式会社 | 電力用半導体装置 |
JP5056105B2 (ja) | 2007-03-27 | 2012-10-24 | 株式会社デンソー | 半導体装置およびその製造方法 |
WO2009151108A1 (ja) | 2008-06-12 | 2009-12-17 | 日本電気株式会社 | 実装基板、及び基板、並びにそれらの製造方法 |
DE102008042777A1 (de) * | 2008-10-13 | 2010-04-15 | Robert Bosch Gmbh | Selektiver Lötstop |
JP5271861B2 (ja) * | 2009-10-07 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5565315B2 (ja) * | 2010-05-18 | 2014-08-06 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP5605095B2 (ja) * | 2010-08-31 | 2014-10-15 | 三菱電機株式会社 | 半導体装置 |
JP5855361B2 (ja) | 2011-05-31 | 2016-02-09 | 三菱電機株式会社 | 半導体装置 |
-
2012
- 2012-09-04 DE DE112012006875.0T patent/DE112012006875T5/de active Pending
- 2012-09-04 JP JP2014534065A patent/JP6156381B2/ja active Active
- 2012-09-04 KR KR1020167031425A patent/KR20160132499A/ko active IP Right Grant
- 2012-09-04 WO PCT/JP2012/072476 patent/WO2014037996A1/ja active Application Filing
- 2012-09-04 US US14/422,573 patent/US9653390B2/en active Active
- 2012-09-04 KR KR1020157005393A patent/KR20150038535A/ko active Application Filing
- 2012-09-04 CN CN201280075614.5A patent/CN104603921B/zh active Active
-
2017
- 2017-03-13 US US15/456,746 patent/US9911705B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6191493B1 (en) * | 1993-02-18 | 2001-02-20 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package and manufacturing method of the same |
CN101567353A (zh) * | 2008-04-25 | 2009-10-28 | 三星电子株式会社 | 球栅阵列基板及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US9653390B2 (en) | 2017-05-16 |
US20170186714A1 (en) | 2017-06-29 |
US20150235925A1 (en) | 2015-08-20 |
JP6156381B2 (ja) | 2017-07-05 |
WO2014037996A1 (ja) | 2014-03-13 |
DE112012006875T5 (de) | 2015-06-03 |
US9911705B2 (en) | 2018-03-06 |
CN104603921A (zh) | 2015-05-06 |
JPWO2014037996A1 (ja) | 2016-08-08 |
KR20160132499A (ko) | 2016-11-18 |
KR20150038535A (ko) | 2015-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104603921B (zh) | 半导体装置、半导体装置的制造方法 | |
JP5384913B2 (ja) | 半導体装置およびその製造方法 | |
TWI556392B (zh) | 半導體裝置 | |
US7659611B2 (en) | Vertical power semiconductor component, semiconductor device and methods for the production thereof | |
US8630097B2 (en) | Power module using sintering die attach and manufacturing method thereof | |
US20170304922A1 (en) | Directly Cooled Substrates for Semiconductor Modules | |
JP2006520103A (ja) | 被覆ワイヤーで形成された、フリップチップ用被覆金属のスタッドバンプ | |
US20070166877A1 (en) | Electronic component and method for its assembly | |
JP2007227893A (ja) | 半導体装置の製造方法 | |
EP1906452B1 (en) | Semiconductor device | |
JPWO2011145176A1 (ja) | 半導体装置及びその製造方法 | |
WO2014136303A1 (ja) | 半導体装置および半導体装置の製造方法 | |
TWI599664B (zh) | 用於功率模組封裝之金屬帶材 | |
JP2007005368A (ja) | 半導体装置の製造方法 | |
CN103295918B (zh) | 一种大功率场效应晶体管铝-金键合过渡片的制备方法 | |
JP2014112581A (ja) | ボンディングワイヤ及びボンディングリボン | |
US9013029B2 (en) | Joined body having an anti-corrosion film formed around a junction portion, and a semiconductor device having the same | |
JP3671123B2 (ja) | 集積回路ウエハに取り付けられた絶縁ゲート型バイポーラトランジスタチップを電気接続する方法 | |
US11908830B2 (en) | Semiconductor device and method for fabricating the same | |
JP2019110280A (ja) | 半導体装置の製造方法 | |
JP5082972B2 (ja) | パワーモジュール用基板の製造方法 | |
CN104465578A (zh) | 半导体装置及半导体模块 | |
EP3248216A1 (en) | Method of generating a power semiconductor module | |
JP2010067784A (ja) | 半導体装置およびその製造方法 | |
JP2013111632A (ja) | 金属接合方法および金属接合構造 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |