WO2014136303A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- WO2014136303A1 WO2014136303A1 PCT/JP2013/077115 JP2013077115W WO2014136303A1 WO 2014136303 A1 WO2014136303 A1 WO 2014136303A1 JP 2013077115 W JP2013077115 W JP 2013077115W WO 2014136303 A1 WO2014136303 A1 WO 2014136303A1
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Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device having a wire connection structure corresponding to a large current capacity and a method of manufacturing the semiconductor device.
- Patent Document 1 direct bonding of an external electrode, which is a copper plate, and an element electrode of a semiconductor element with solder is disclosed. In this way, a connection capable of conducting a large current can be realized while reducing the electrical resistance.
- JP 2010-272711 A (patent document 2), it is disclosed that the reliability at the time of solder bonding is improved by forming a Ni layer having a proper thickness as a metal film for solder bonding. . By optimizing the Ni thickness, it is possible to achieve both process feasibility and junction reliability better.
- a portion through which current of the semiconductor element flows is subjected to thermal stress due to temperature cycles.
- a semiconductor device having a junction structure as disclosed in Patent Document 1 has an appropriate thickness of a metal film for solder junction in order to enhance junction reliability as in Patent Document 2. Need to be formed.
- the metal film is patterned into an appropriate shape in order to control the spread shape of the solder when bonding the external electrode thereon.
- a lift-off method which is a simple patterning method, is suitable for this patterning.
- the ease of removing the unnecessary part in the lift-off method, that is, the lift-off property decreases as the thickness of the metal film increases. For this reason, when the thickness of the metal film is large, a portion to be lifted off may remain, or the surface exposed by the lift off may be scratched. Thus, if the thickness of the metal film is large, the yield of the lift-off process is reduced. For this reason, it has been difficult to form a metal film for controlling the spread shape of the solder with high productivity.
- the present invention has been made to solve the above-described problems, and a semiconductor device and a semiconductor capable of forming a metal film for controlling the spread shape of solder when bonding external electrodes with high productivity.
- the present invention provides a method of manufacturing a device.
- a semiconductor device includes a semiconductor element, an element electrode, a metal film, and an external electrode.
- the element electrode is provided on the surface of the semiconductor element.
- the metal film is provided on the device electrode and has an inner region and an outer region located around the inner region.
- the metal film is provided with an opening for exposing the device electrode between the inner region and the outer region.
- the element electrode has solder wettability lower than that of the metal film.
- the outer electrode is soldered to the inner region of the metal film.
- a semiconductor device includes a semiconductor element, an element electrode, a metal film, a covering film, and an external electrode.
- the element electrode is provided on the surface of the semiconductor element.
- the metal film is provided on the device electrode.
- the covering film is partially provided on the metal film, and divides the metal film into an inner region and an outer region surrounding the inner region.
- the coating film has solder wettability lower than that of the metal film.
- the outer electrode is soldered to the inner region of the metal film.
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device described above, and includes the following steps.
- a substrate provided with a main surface having an effective area in which a semiconductor element provided with an element electrode is disposed and an ineffective area outside the effective area is formed.
- a metal film is formed on the device electrode.
- the metal film includes a portion located on the ineffective region. After the metal film is formed, the semiconductor element is cut out by dicing along dicing lines in the ineffective region.
- the external electrode is soldered to the inner region of the metal film.
- FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic plan view which shows the pattern of the metal film which the semiconductor device of FIG. 1 has.
- FIG. 3 is a schematic partial cross-sectional view along line III-III of FIG. 2;
- FIG. 7 is a flow diagram schematically showing a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 8 is a schematic partial cross sectional view showing the first step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 16 is a schematic partial cross sectional view showing the second step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 16 is a schematic partial cross sectional view showing the third step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 14 is a schematic partial cross-sectional view showing a fourth step of the method of manufacturing a semiconductor device in the first embodiment of the present invention. It is a schematic plan view (A) which shows the pattern of the photoresist in the process of FIG. 7, and the enlarged view (B) of the IXB part. It is a schematic plan view which shows the pattern of the metal film which the semiconductor device in Embodiment 2 of this invention has.
- FIG. 11 is a schematic partial cross-sectional view (A) along line XIA-XIA in FIG.
- FIG. 10 and a schematic partial cross-sectional view (B) along line XIB-XIB. It is a schematic plan view which shows the pattern of the metal film which the semiconductor device in Embodiment 3 of this invention has.
- FIG. 13 is a schematic partial cross-sectional view (A) along line XIIIA-XIIIA in FIG. 12 and a schematic partial cross-sectional view (B) along line XIIIB-XIIIB. It is a schematic plan view which shows the pattern of the metal film which the semiconductor device in Embodiment 4 of this invention has.
- FIG. 15 is a schematic partial cross-sectional view along the line XV-XV in FIG. It is a schematic plan view which shows the pattern of the metal film which the semiconductor device in Embodiment 5 of this invention has.
- FIG. 15 is a schematic partial cross-sectional view along the line XVII-XVII in FIG.
- FIG. 1 is a cross-sectional view showing a structure of a semiconductor device 200 according to the present embodiment.
- FIG. 2 is a plan view showing a pattern of the metal film 105 of the semiconductor element 101 according to the present embodiment. In FIG. 2, the openings of the metal film 105 are hatched in order to make the drawing easy to see.
- the semiconductor device 200 includes a semiconductor element 101, an emitter electrode 103 (element electrode), a metal film 105, and an external electrode 117.
- Emitter electrode 103 is provided on the surface of semiconductor element 101.
- the metal film 105 is provided on the emitter electrode 103, and has an inner region 105a and an outer region 105b1 located around the inner region 105a.
- the metal film 105 is provided with a moat-shaped opening TR which exposes the emitter electrode 103 between the inner region 105a and the outer region 105b1.
- the moat-shaped opening TR is provided in a moat between the inner region 105a and the outer region 105b1.
- the inner region 105a and the outer region 105b1 of the metal film 105 are separated by the moat-shaped opening TR.
- the emitter electrode 103 has solder wettability lower than that of the metal film 105.
- the emitter electrode 103 is soldered to the inner region 105 a of the metal film 105 by a solder portion 121.
- the inner region 105a and the outer region 105b1 are formed of the same material. For this reason, the inner region 105a and the outer region 105b1 can be formed in the same process, specifically, a lift-off process.
- the outer region 105b1 is left during patterning of the metal film 105 by the lift-off process, so the area of the portion removed by the lift-off is reduced.
- the thickness of the metal film 105 is preferably 1 ⁇ m or more in order to sufficiently protect the emitter electrode 103 at the time of soldering.
- the semiconductor device 200 further includes the insulating sheet 111, the base plate 113, the solder layer 115, the other external electrode 118, the solder portion 122, and the sealing material. 123, a gate pad 203 (control electrode), a metal wire 213, and an external control electrode 223 can be provided.
- the semiconductor element 101 is, for example, a vertical IGBT (Insulated Gate Bipolar Transistor) having electrodes on the front surface side and the back surface side.
- An emitter electrode 103 as a first main electrode is provided on the upper surface side of the semiconductor element 101.
- a metal film 105 is formed on the emitter electrode 103, and the metal film 105 is an inner region 105a as a metal film for solder bonding through an exposed portion for forming an opening so as to expose the emitter electrode 103 in a moat shape.
- an outer region 105b1 as a dummy metal film.
- a gate wiring (not shown) is formed to surround emitter electrode 103 and is electrically connected to gate pad 203.
- a termination region 205 is formed outside the gate wiring.
- the semiconductor element 101 has a protective film 209 around the metal film 105 in a region other than the gate pad 203.
- the semiconductor element 101 also has a collector electrode 109 as a second main electrode on the lower surface side.
- the collector electrode 109 is connected to the base plate 113 on the insulating sheet 111 via the solder layer 115.
- the emitter electrode 103 is made of metal and preferably contains Al as a main component. Specifically, the emitter electrode 103 is preferably made of a material containing 95% or more of Al.
- the gate pad 203 can be made of the same material as the emitter electrode 103. In addition, it is general to form the gate pad 203 in the same manufacturing process as the emitter electrode 103. By employing a material mainly containing Al as the emitter electrode 103 and the gate pad 203, it can be easily formed and processed by an existing method as an electrode of a semiconductor element using various substrates such as a Si substrate. Further, by using Al as described above, when the metal wire 213 is bonded to the gate pad 203 by wire bonding, it is possible to secure a connection having excellent connection reliability. Since the resistance increases as the Al content decreases, it is not preferable as an electrode of a semiconductor device that handles a large current. By containing 95% or more of Al, the compatibility with the Al wire bond is good, and the conductivity can be increased.
- FIG. 3 is a schematic partial cross-sectional view showing a structure taken along line III-III in FIG.
- the metal film 105 formed on the emitter electrode 103 is, for example, a laminated metal film in which an adhesion securing metal film 105c, a solder bonding metal film 105d, and an oxidation preventing metal film 105e are sequentially stacked from the emitter electrode 103 side. It is.
- Ti may be used as the adhesion securing metal film 105c
- Ni may be used as the solder bonding metal film 105d
- Au may be used as the oxidation preventing metal film 105e.
- the reason why Ti is deposited on the emitter electrode 103 is that the adhesion between the emitter electrode 103 mainly made of a material containing Al and the solder bonding metal film 105d formed of Ni is secured while the metal for the solder bonding is used. This is to prevent Ni of the film 105 d from diffusing into the semiconductor element 101.
- the adhesion securing metal film 105c for securing the adhesion to the emitter electrode 103 may be other than Ti, for example, Mo.
- Emitter electrode 103 mainly made of a material containing Al is difficult to join, for example, SnAgCu-based Pb-free solder, so by depositing Ni via Ti, it is possible to join with solder and have solderability. I have secured.
- the solder wettability decreases when the Ni film is oxidized
- Au is deposited as the oxidation preventing metal film 105 e for the purpose of preventing the oxidation of Ni.
- the oxidation preventing metal film 105e may be other than Au, for example, Ag.
- a Ti / Ni / Au film can be deposited as the metal film 105 on the emitter electrode 103 so that SnAgCu-based Pb-free solder can be joined and the adhesion to the emitter electrode 103 is ensured. It is suitable.
- FIG. 4 shows a flowchart of a method of manufacturing the semiconductor device 200.
- step S10 a so-called wafer level process is roughly completed except for the formation of metal film 105. That is, a wafer (substrate) provided with a main surface having an effective region where the semiconductor element 101 provided with the emitter electrode 103 (element electrode) is disposed and an ineffective region outside the effective region is formed.
- the emitter electrode 103 is an Al or AlSi or AlCu film formed by sputtering.
- the electrode may be heat treated at 400-470 ° C. in a hydrogen or nitrogen atmosphere. The heat treatment enlarges the crystal size and improves the flatness. Thereby, the coverage of the metal film 105 formed later can be improved.
- the metal film 105 is formed (FIG. 4: step S20). Specifically, referring to FIG. 6, first, a photoresist 501 is applied. Referring to FIG. 7, photoresist 501 is patterned by performing exposure and development on photoresist 501. Thus, the patterning of the photoresist 501 can be performed by photolithography. This patterning is performed such that the area where the metal film 105 is not finally left is covered by the photoresist 501.
- metal films 105c, 105d and 105e constituting metal film 105 are formed. Specifically, Ti, Ni and Au are sequentially stacked by sputtering or the like. In order to improve the resistance to thermal stress, it is preferable to deposit Ni thicker than Ti and Au as the main metal of the metal film 105.
- the metal film 105 is at least partially It also has high hardness. Thus, when solder bonding is performed on the metal film 105 described later, the emitter electrode 103 can be protected, and the destruction of the emitter electrode 103 can be suppressed.
- the thickness of the metal film 105 is reduced due to solder corrosion. Therefore, the thickness of Ni of the metal film 105 is preferably 1 ⁇ m or more. Further, the residual Ni thickness after soldering is preferably 0.5 ⁇ m or more, whereby the electrode can be sufficiently protected.
- the photoresist 501 and the metal film 105f thereon are removed by a lift-off process.
- the following process is an example of the lift-off process.
- the photoresist 501 is melted using a thinner as the organic solvent.
- thinner or pure water is applied to the wafer at high pressure to physically remove the photoresist 501 and the metal film 105f formed thereon.
- a pattern having the inner region 105 a and the outer region 105 b 1 is formed on the metal film 105.
- FIG. 9A shows the pattern of the photoresist 501 (FIG. 7) over the entire main surface of the wafer 100 (substrate), and FIG. 9B shows an enlarged view of the IXB portion.
- the hatched portions in FIGS. 9A and 9B indicate regions where the photoresist 501 is disposed in plan view.
- the photoresist 501 has a grid-like region 401 and a moat-like region 403.
- the moat region 403 is for forming the moat-shaped opening TR (FIG. 3) in the metal film 105.
- the grid-like region 401 is for the dicing line DL to be positioned at the opening of the metal film 105 when dicing of the wafer 100 is performed along the dicing line DL.
- the metal film 105 on the dicing line DL is at least partially removed by lift-off, so that an opening is formed in the metal film 105 on the dicing line DL, which makes it possible to perform easier dicing thereafter.
- an opening region 509 is provided in the photoresist 501 by photolithography.
- the opening region 509 further includes a region 409 in addition to the region 405 corresponding to the inner region 105a (FIG. 2) and the region 407 corresponding to the outer region 105b1.
- the region 409 is disposed outside the effective region ER in which the semiconductor element 101 is disposed.
- the region 409 is disposed in the ineffective region IR of the wafer 100 which does not finally become the semiconductor element 101.
- the invalid area IR includes an outer peripheral area of the wafer 100 and an area near the dicing line DL.
- the metal film 105 has to be removed as an extra metal film region while securing the function of controlling the solder shape. Can be reduced as much as possible.
- step S30 (FIG. 4) dicing along dicing lines DL in the ineffective region IR is performed.
- the semiconductor element 101 is cut out.
- a semiconductor device 200 (FIG. 1) is obtained by packaging the semiconductor element 101 that has been cut out.
- the external electrode 117 is soldered to the inner region 105a of the metal film 105 (FIG. 4: step S40). The solder bonding process will be described below.
- Solder bonding of the external electrode 117 and the inner region 105a of the metal film 105 by the solder portion 121 is performed, for example, by dropping molten solder from a through hole 119 (FIG. 1) provided in the external electrode 117.
- the dropped solder wets and spreads on the inner region 105a.
- the spread of the solder stops when reaching the moat-shaped opening TR. This is because the emitter electrode 103 exposed by the moat-shaped opening TR has lower solder wettability than the solder wettability of the inner region 105a.
- the main material of the emitter electrode 103 is Al, a natural oxide film is formed on the surface, so that the solder wettability of the exposed portion of the emitter electrode 103 is poor, and the solder at the exposed portion of the emitter electrode 103 at the metal film end is Wet spreading stops. As described above, since the wetting and spreading of the solder is inhibited by the emitter electrode 103, the solder does not progress to the outer region 105b1 outside the exposed portion of the emitter electrode 103, and the solder shape is restrained in the inner region 105a. A solder portion 121 having a desired shape is obtained.
- step S50 the semiconductor device 200 which is a module to which the external electrode 117 and the like are attached is completed.
- the metal film 105 has the outer region 105b1 in addition to the inner region 105a used for solder bonding. That is, the outer region 105b1 is not removed by lift-off. As a result, the rate of removal of the metal film 105 by lift-off can be reduced compared to when the outer region 105b1 is removed. Thereby, lift-off can be performed more easily and reliably. In addition, the amount of the metal film 105f removed by lift-off is small, and the area of the emitter electrode 103 exposed is correspondingly small, so that the metal film 105f removed at the time of lift-off is caused to hit the emitter electrode 103. The occurrence of wounds is suppressed.
- the yield of the lift-off process can be increased.
- the lift-off of the metal film 105 can be performed more easily and reliably. Therefore, even if the metal film 105 is deposited thick, the yield of the lift-off process can be maintained, and the decrease in productivity can be suppressed.
- FIG. 10 is a plan view showing a pattern of the metal film 105 of the semiconductor device according to the present embodiment.
- the openings of the metal film 105 are hatched to make the drawing easier to see.
- FIGS. 11A and 11B is a schematic partial cross-sectional view showing a structure along lines XIA-XIA and XIB-XIB in FIG.
- the metal film 105 has an inner region 105a and an outer region 105b2 located around the inner region 105a.
- the outer region 105b2 like the outer region 105b1 (FIG. 2), is a dummy metal film which is not particularly necessary for solder bonding.
- the outer region 105b2 has a plurality of portions discretely located around the inner region 105a. In other words, the lattice-like openings SP are provided in the outer region 105b2 so as to separate these portions from one another.
- the other configuration of the present embodiment is the same as that of the first embodiment.
- solder which wets and spreads in the inner region 105a is not wetted in the sufficiently small outer region 105b2 and is restrained in the inner region 105a, so the shape of the solder portion 121 (FIG. 1), ie, the solder shape after solder bonding is controlled. be able to.
- the advantage is that the total edge length of the photoresist used for lift-off of the metal film 105 is increased. There is. This increases the chances of thinner entering and melting of the photoresist in the lift-off process, so lift-off can be performed more easily and reliably.
- FIG. 12 is a plan view showing a pattern of the metal film 105 on the semiconductor element according to the present embodiment.
- the openings of the metal film 105 are hatched in order to make the drawing easy to see.
- FIGS. 13 (A) and 13 (B) is a schematic partial cross-sectional view showing a structure taken along line XIIIA-XIIIA and XIIIB-XIIIB in FIG.
- the metal film 105 has an inner region 105a and an outer region 105b3 located around the inner region 105a.
- the outer region 105b3 is provided with a plurality of discrete openings IL for exposing the emitter electrode 103.
- the inner region 105a and the outer region 105b3 are connected to each other only in the dimension WD (one dimension) or less, as shown in FIG.
- the dimension WD is small enough to prevent the spread of the solder from the inner region 105a to the outer region 105b3 when the molten solder is disposed on the inner region 105a.
- the solder which wets and spreads the inner region 105 a of the metal film 105 during soldering is blocked by the exposed emitter electrode 103 at the discrete opening IL. Specifically, since the line width (in the figure, dimension WD) of the outer region 105b3 between the exposed emitter electrodes 103 around the inner region 105a is sufficiently small, the solder wets to the outside of the inner region 105a. Since it does not spread and is confined within the inner region 105a, the shape of the solder portion 121 (FIG. 1), that is, the solder shape after solder bonding can be controlled.
- the other configuration of the present embodiment is the same as that of the first embodiment.
- the outer region 105b3 may have a dimension equal to or smaller than the dimension WD also in the portion separated from the inner region 105a by the discrete opening IL. Thereby, the wetting and spreading of the solder can be more reliably prevented.
- the advantage is that the edge length of the photoresist used for lift-off of the metal film 105 is increased. is there. This increases the chances of thinner entering and melting of the photoresist in the lift-off process, so lift-off can be performed more easily and reliably.
- FIG. 14 is a plan view showing a pattern of the metal film 105 of the semiconductor element according to the present embodiment.
- the covering film 1101 on the metal film 105 is hatched to make it easy to see the figure.
- FIG. 15 is a schematic partial cross-sectional view showing a structure along line XV-XV in FIG.
- the metal film 105 has an inner region 105a and an outer region 105b4 located around the inner region 105a.
- the inner region 105a and the outer region 105b4 constitute an integral metal film having no opening. In other words, both are connected to each other in the entire boundary between the inner region 105a and the outer region 105b4. That is, the metal film 105 is formed on the entire surface of the emitter electrode 103.
- a covering film 1101 is formed on the metal film 105 to prevent the solder from developing when the external electrode 117 (FIG. 1) is soldered.
- the covering film 1101 is partially provided on the metal film 105, and divides the metal film 105 into an inner area 105a and an outer area 105b4 surrounding the inner area 105a. Solder bonding of the external electrode 117 and the metal film 105 is performed on the inner region 105a.
- the covering film 1101 surrounds the inner region 105a.
- the other configuration of the present embodiment is the same as that of the first embodiment.
- the coating film 1101 has solder wettability lower than that of the metal film 105.
- the covering film 1101 is preferably an insulating film made of polyimide.
- the thickness is preferably about 2 ⁇ m or more and about 20 ⁇ m or less. If the film thickness of the polyimide exceeds 20 ⁇ m, the warpage of the wafer due to the shrinkage stress of the polyimide generated when the polyimide is baked tends to be excessive. In addition, if it is attempted to deposit polyimide over 20 ⁇ m, the in-plane uniformity of the wafer tends to be impaired.
- this polyimide also serves to cover and protect the termination region 205 etc., and if the polyimide film thickness is less than 2 ⁇ m, the step portion of these termination regions 205 It is easy for the formation defect to occur.
- the solder that wets and spreads on the inner region 105a is blocked by the coating film 1101 and does not spread to the metal film 105 outside the coating film 1101, ie, the outer region 105b4, and is restrained in the inner region 105a.
- the shape of the portion 121 (FIG. 1) that is, the solder shape after solder bonding can be controlled.
- the covering film 1101 By forming the covering film 1101 with the same material as the passivation film (not shown) provided on the semiconductor element 101, the process can be simplified. Moreover, if both are formed collectively, it is possible to reduce the number of processes.
- As a material of the passivation film there are polybenzoxador and other silicon resin materials other than polyimide. By using these, the formation process of the coating film 1101 can be completed in the wafer process before dicing. Also, as another material used in the wafer process, a silicon oxide film or a silicon nitride film formed by a CVD (Chemical Vapor Deposition) method is used in addition to an organic material represented by polyimide or polybenzoxador. It is also possible to form a coating 1101.
- CVD Chemical Vapor Deposition
- the solder bonding metal film 105d is deposited on the oxidation preventing metal film 105e due to a thermal load during CVD, and the precipitate is oxidized to cause solder wettability. May be inhibited.
- the oxidation preventing metal film 105e is formed of Au or Ag, the cost increases if the oxidation preventing metal film 105e is thickened. Therefore, when the metal film 105e for preventing oxidation is formed of Au or Ag, the material of the covering film 1101 is preferably an organic material represented by polyimide or polybenzoxador.
- lift-off of the metal film 105 on the emitter electrode 103 is not particularly required, and lift-off of the metal film 105 is performed by the termination region 205, dicing line DL, gate It may be performed only on the pad 203 or the like. This simplifies the lift-off process and increases productivity.
- FIG. 16 is a plan view showing a pattern of the metal film 105 of the semiconductor element according to the present embodiment.
- the covering film 1101 is hatched in order to make the drawing easy to see.
- FIG. 17 is a schematic partial cross-sectional view showing a structure taken along line XVII-XVII in FIG.
- the metal film 105 has an inner region 105a and an outer region 105b5 located around the inner region 105a.
- the outer region 105b5 is substantially similar to the outer region 105b1 (FIG. 2).
- the metal film 105 has a moat-shaped opening TR (FIG. 17) that exposes the emitter electrode 103 between the inner region 105a and the outer region 105b5.
- the moat-shaped opening TR surrounds an inner area 105a which is an area where solder bonding is performed. Over the moat-shaped opening TR, a coating film 1301 is formed to prevent the progress of the solder. As shown in FIG.
- the covering film 1301 has a width wider than the opening width of the moat-shaped opening TR, and like the moat-shaped opening TR, surrounds a region where solder bonding is to be performed.
- the material and formation method of the coating film 1301 are the same as those of the coating film 1101 (Embodiment 4).
- the configuration other than the above is substantially the same as the configuration of the fourth embodiment described above, so the same or corresponding elements are denoted by the same reference characters and description thereof will not be repeated.
- the coating film 1301 is a polyimide film
- the adhesion between Au and polyimide is low.
- polyimide may be released during solder bonding.
- the polyimide film and the emitter electrode 103 are in close contact with each other through the moat-shaped opening TR of the metal film 105, detachment of the polyimide can be prevented.
- a material having an Al content higher than that of the metal film 105 is used for the emitter electrode 103, this effect is large.
- the emitter electrode 103 formed of a material containing 95% or more of Al has good adhesion to polyimide, the risk of detachment of the polyimide film can be further reduced. The same effect can be obtained even when a material containing Au or Ag is used for the outermost surface layer of the metal film 105 and a material having a smaller content of Au or Ag than the outermost surface layer of the metal film 105 is used for the emitter electrode 103. can get.
- the coating film 1301 which is less likely to be detached than the coating film 1101 of the fourth embodiment. Therefore, control of the shape of the solder portion 121 (FIG. 1) by the covering film 1301 can be performed more reliably.
- the opening formed in the metal film 105 is the moat-shaped opening TR similar to that of the first embodiment, but the shape of the opening is not limited to this.
- the same shape as that of the lattice-like aperture SP (FIG. 10: Embodiment 2) or the discrete aperture IL (FIG. 12: Embodiment 3) may be used.
- the lift-off process in each of the above embodiments is not limited to one performed by applying thinner or pure water to the photoresist at a high pressure.
- the lift-off may be performed, for example, by applying a tape to a metal film and peeling off the tape. In this case, the adhesive force of the tape removes the metal film on the photoresist.
- the present invention can freely combine the above-described embodiments within the scope of the invention, and can arbitrarily modify or omit any component of each embodiment.
- the present specification includes the disclosures of (i) to (ix) below.
- the first metal film is disposed in a shape covering an area other than the first metal film of the electrode so as to form an exposed portion which forms an opening (TR) for exposing the electrode in a moat shape along the outer periphery of the first metal film.
- a second metal film (105b1) An external electrode (117) soldered to the first metal film;
- a semiconductor device (200) comprising:
- the configuration of this semiconductor device can be read, for example, from the first embodiment.
- a semiconductor element 101
- An electrode (103) provided on the surface of the semiconductor element;
- a first metal film (105a) provided on the surface of the electrode in such a manner as to control a solder shape after solder bonding;
- a second metal film (105b2) discretely disposed in a plurality of shapes smaller than the first metal film in an exposed portion where the electrode is exposed in the periphery of the first metal film;
- a semiconductor device (200) comprising:
- the configuration of this semiconductor device can be read, for example, from the second embodiment.
- a semiconductor element 101
- An electrode (103) provided on the surface of the semiconductor element
- a first metal film (105) provided on the surface of the electrode
- An external electrode (117) soldered to the first metal film; Equipped with The first metal film includes a solder bonding area (105a) for solder bonding with the external electrode;
- a semiconductor device (200) comprising an exposed portion (IL) in which the electrode is exposed in a region other than the solder bonding region so as to have a thin line width (WD) which inhibits solder growth.
- the configuration of this semiconductor device can be read, for example, from the third embodiment.
- the semiconductor device (200) according to any one of (i) to (iii) above.
- the configuration of this semiconductor device can be read, for example, from the fifth embodiment.
- a semiconductor device (200) comprising:
- the configuration of this semiconductor device can be read, for example, from the fourth embodiment.
- Reference Signs List 100 wafer (substrate), 101 semiconductor element, 103 emitter electrode (element electrode), 105 metal film, 105a inner region, 105b1 to 105b5 outer region, 117 external electrode, 121 solder portion, 200 semiconductor device, 1101, 1301 coating film , DL dicing line, ER effective area, IL discrete opening (aperture), IR invalid area, SP lattice-like opening (aperture), TR moat-like opening (aperture).
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Abstract
Description
はじめに半導体装置200の構成の概要について説明する。図1は、本実施の形態に係る半導体装置200の構造を示す断面図である。また、図2は本実施の形態の半導体素子101の金属膜105のパターンについて示す平面図である。なお図2において、図を見やすくするために、金属膜105の開口部にハッチングを付している。
図10は、本実施の形態に係る半導体素子の金属膜105のパターンについて示す平面図である。図10において、図を見やすくするために、金属膜105の開口部にハッチングを付している。また、図11(A)および(B)のそれぞれは、図10中の線XIA-XIAおよびXIB-XIBに沿う構造について示す概略部分断面図である。
図12は、本実施の形態に係る半導体素子上の金属膜105のパターンについて示す平面図である。図12において、図を見やすくするために、金属膜105の開口部にハッチングを付している。図13(A)および(B)のそれぞれは、図12中の線XIIIA-XIIIAおよびXIIIB-XIIIBに沿う構造について示す概略部分断面図である。
図14は、本実施の形態に係る半導体素子の金属膜105のパターンについて示す平面図である。図14において、図を見やすくするために、金属膜105上の被覆膜1101にハッチングを付している。図15は、図14中の線XV-XVに沿う構造について示す概略部分断面図である。
図16は、本実施の形態に係る半導体素子の金属膜105のパターンについて示す平面図である。図16において、図を見やすくするために、被覆膜1101にハッチングを付している。図17は、図16中の線XVII-XVIIに沿う構造について示す概略部分断面図である。
本明細書は、以下の(i)~(ix)の開示を含む。
(i) 半導体素子(101)と、
前記半導体素子の表面に設けられた電極(103)と、
前記電極の表面に半田接合後の半田形状を制御する形で設けられた第1の金属膜(105a)と、
前記第1の金属膜の外周に沿って堀状に前記電極を露出する開口(TR)を形成する露出部を形成するように前記電極の前記第1の金属膜以外の領域を覆う形状で配置された第2の金属膜(105b1)と、
前記第1の金属膜に半田接合された外部電極(117)と、
を備えたことを特徴とする半導体装置(200)。
(ii) 半導体素子(101)と、
半導体素子表面に設けられた電極(103)と、
前記電極の表面に半田接合後の半田形状を制御する形で設けられた第1の金属膜(105a)と、
前記第1の金属膜の周辺の前記電極が露出した露出部に、前記第1の金属膜より小さい形状で離散的に複数個配置された第2の金属膜(105b2)と、
前記第1の金属膜に半田接合された外部電極(117)と、
を備えたことを特徴とする半導体装置(200)。
(iii) 半導体素子(101)と、
半導体素子表面に設けられた電極(103)と、
前記電極の表面に設けられた第1の金属膜(105)と、
前記第1の金属膜に半田接合された外部電極(117)と、
を備え、
前記第1の金属膜は、前記外部電極と半田接合するための半田接合領域(105a)と、
前記半田接合領域以外の領域に、半田進展を阻害する細線幅(WD)となるように前記電極を露出させた露出部(IL)を有することを特徴とする半導体装置(200)。
(iv) 前記露出部上に半田接合時の半田形状を制御する形で設けられた被覆膜(1301)と、
を備えたことを特徴とする、上記(i)~(iii)のいずれか1項に記載の半導体装置(200)。
(v) 半導体素子(101)と、
半導体素子表面に設けられた電極(103)と、
前記電極の表面に設けられた金属膜(105)と、
前記金属膜上に半田接合時の半田形状を制御する形で設けられた被覆膜(1101)と、
を備えたことを特徴とする半導体装置(200)。
(vi) 前記被覆膜が、厚さが2~20μmのポリイミドで形成されていることを特徴とする、上記(iv)または(v)に記載の半導体装置。
(vii) 前記電極がアルミを95%以上含む材料からなっていることを特徴とする、上記(i)~(vi)のいずれか1項に記載の半導体装置。
(viii) 上記(i)~(vii)のいずれか1項に記載の半導体装置の製造方法であって、
前記第1の金属膜の形成工程で、ウエハ(100)面内全領域中で半導体装置として使用しない無効領域(IR)上にも前記第1の金属膜と同等の金属膜を形成することを特徴とする半導体装置の製造方法。
(ix) 前記無効領域上の金属膜に開口を形成し、前記開口がダイシングライン(DL)上にあることを特徴とする、上記(viii)に記載の半導体装置の製造方法。
Claims (16)
- 半導体素子(101)と、
前記半導体素子の表面に設けられた素子電極(103)と、
前記素子電極上に設けられ、内側領域(105a)と前記内側領域の周りに位置する外側領域(105b1~105b3)とを有する金属膜(105)とを備え、前記金属膜には前記内側領域および前記外側領域の間で前記素子電極を露出する開口(TR,SP,IL)が設けられており、前記素子電極は前記金属膜の半田濡れ性よりも低い半田濡れ性を有し、さらに
前記金属膜の前記内側領域に半田接合された外部電極(117)を備えた、
半導体装置。 - 前記金属膜の前記内側領域および前記外側領域(105b1,105b2)は前記開口(TR,SP)によって分離されている、請求項1に記載の半導体装置。
- 前記開口(TR)は、前記金属膜の前記内側領域および前記外側領域(105b1)の間に堀状に設けられている、請求項2に記載の半導体装置。
- 前記金属膜の前記外側領域(105b2)は、離散的に配置された複数の部分を有する、請求項2に記載の半導体装置。
- 前記金属膜の前記内側領域および前記外側領域(105b3)は互いに一の寸法(WD)以下でのみつながっており、前記一の寸法は、溶融した半田が前記金属膜の前記内側領域上に配置された場合に前記内側領域から前記外側領域への半田の広がりが阻害される程度に小さい、請求項1に記載の半導体装置。
- 前記金属膜の前記内側領域および前記外側領域は同じ材料で形成されている、請求項1~5のいずれか1項に記載の半導体装置。
- 前記金属膜の前記内側領域および前記外側領域は同じ工程で形成されている、請求項1~5のいずれか1項に記載の半導体装置。
- 前記金属膜は、少なくとも部分的に、前記素子電極の硬度よりも高い硬度を有する、請求項1~5のいずれか1項に記載の半導体装置。
- 前記金属膜は1μm以上の厚さを有する、請求項1~5のいずれか1項に記載の半導体装置。
- 半導体素子(101)と、
前記半導体素子の表面に設けられた素子電極(103)と、
前記素子電極上に設けられた金属膜(105)と、
前記金属膜上に部分的に設けられ、前記金属膜を内側領域(105a)と前記内側領域を囲む外側領域(105b4,105b5)とに区分し、前記金属膜の半田濡れ性よりも低い半田濡れ性を有する被覆膜(1101,1301)と、
前記金属膜の前記内側領域に半田接合された外部電極(117)とを備えた、
半導体装置。 - 前記金属膜の前記内側領域および前記外側領域(105b4)は、前記内側領域と前記外側領域との境界の全体において互いにつながっている、請求項10に記載の半導体装置。
- 前記金属膜には前記内側領域および前記外側領域の間で前記素子電極を露出する開口が設けられており、前記被覆膜(1301)は前記開口に配置されている、請求項10に記載の半導体装置。
- 前記被覆膜は、厚さ2μm以上20μm以下を有するポリイミド膜を含む、請求項10~12のいずれか1項に記載の半導体装置。
- 前記素子電極は、アルミニウムを95%以上含む材料から作られている、請求項10~12のいずれか1項に記載の半導体装置。
- 請求項1~5および10~12のいずれか1項に記載の半導体装置の製造方法であって、
前記素子電極が設けられた前記半導体素子が配置された有効領域(ER)と、前記有効領域の外側の無効領域(IR)と、を有する主面が設けられた基板(100)を形成する工程と、
前記素子電極上に前記金属膜を形成する工程とを備え、前記金属膜は前記無効領域上に位置する部分を含み、さらに
前記金属膜が形成された後に、前記無効領域におけるダイシングライン(DL)に沿ったダイシングによって、前記半導体素子を切り出す工程と、
前記金属膜の前記内側領域に前記外部電極を半田接合する工程とを備えた、
半導体装置の製造方法。 - 前記金属膜を形成する工程は、前記ダイシングライン上において前記金属膜に開口を形成する工程を含む、請求項15に記載の半導体装置の製造方法。
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WO2020067059A1 (ja) * | 2018-09-26 | 2020-04-02 | 三菱電機株式会社 | 半導体装置、電力変換装置、及び半導体装置の製造方法 |
US10804169B2 (en) | 2016-11-08 | 2020-10-13 | Mitsubishi Electric Corporation | Semiconductor device |
US11424203B2 (en) | 2019-05-13 | 2022-08-23 | Fuji Electric Co., Ltd. | Semiconductor module and method of manufacturing semiconductor module |
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DE112017007319T5 (de) * | 2017-03-27 | 2020-01-02 | Mitsubishi Electric Corporation | Halbleitervorrichtung, Leistungsumwandlungsvorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
US11127603B2 (en) * | 2017-09-04 | 2021-09-21 | Mitsubishi Electric Corporation | Semiconductor module and power conversion device |
DE102018125300A1 (de) * | 2018-10-12 | 2020-04-16 | Osram Opto Semiconductors Gmbh | Elektronisches Bauteil und Verfahren zum Aufbringen von zumindest einem Lötpad auf ein elektronisches Bauteil |
JP2022144711A (ja) * | 2021-03-19 | 2022-10-03 | 三菱電機株式会社 | 半導体装置の製造方法 |
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JP2010232230A (ja) * | 2009-03-25 | 2010-10-14 | Casio Computer Co Ltd | 半導体装置およびその製造方法 |
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US10804169B2 (en) | 2016-11-08 | 2020-10-13 | Mitsubishi Electric Corporation | Semiconductor device |
WO2020067059A1 (ja) * | 2018-09-26 | 2020-04-02 | 三菱電機株式会社 | 半導体装置、電力変換装置、及び半導体装置の製造方法 |
JPWO2020067059A1 (ja) * | 2018-09-26 | 2021-08-30 | 三菱電機株式会社 | 半導体装置、電力変換装置、及び半導体装置の製造方法 |
JP7086204B2 (ja) | 2018-09-26 | 2022-06-17 | 三菱電機株式会社 | 半導体装置、電力変換装置、及び半導体装置の製造方法 |
US11424203B2 (en) | 2019-05-13 | 2022-08-23 | Fuji Electric Co., Ltd. | Semiconductor module and method of manufacturing semiconductor module |
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JP6038280B2 (ja) | 2016-12-07 |
CN105009266B (zh) | 2018-05-08 |
DE112013006790T5 (de) | 2015-12-17 |
JPWO2014136303A1 (ja) | 2017-02-09 |
US10157865B2 (en) | 2018-12-18 |
CN105009266A (zh) | 2015-10-28 |
US20160005703A1 (en) | 2016-01-07 |
DE112013006790B8 (de) | 2022-08-18 |
DE112013006790B4 (de) | 2022-05-25 |
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