CN105009266A - 半导体装置及半导体装置的制造方法 - Google Patents
半导体装置及半导体装置的制造方法 Download PDFInfo
- Publication number
- CN105009266A CN105009266A CN201380074382.6A CN201380074382A CN105009266A CN 105009266 A CN105009266 A CN 105009266A CN 201380074382 A CN201380074382 A CN 201380074382A CN 105009266 A CN105009266 A CN 105009266A
- Authority
- CN
- China
- Prior art keywords
- metal film
- semiconductor device
- inside region
- solder
- exterior lateral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05007—Structure comprising a core and a coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05563—Only on parts of the surface of the internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05563—Only on parts of the surface of the internal layer
- H01L2224/05565—Only outside the bonding interface of the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
- H01L2224/05583—Three-layer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/0568—Molybdenum [Mo] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/26145—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/29027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the layer connector being offset with respect to the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/404—Connecting portions
- H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
- H01L2224/40499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48724—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48739—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48744—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48755—Nickel (Ni) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48763—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/48766—Titanium (Ti) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48763—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/4878—Molybdenum (Mo) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
元件电极(103)设置于半导体元件(101)的表面。金属膜(105)设置于元件电极(103)上,并具有内侧区域(105a)和位于内侧区域(105a)周围的外侧区域(105b1)。在金属膜(105)中设置有在内侧区域(105a)及外侧区域(105b1)之间将元件电极(103)露出的开口(TR)。元件电极(103)具有比金属膜(105)的焊料浸润性低的焊料浸润性。外部电极(117)与金属膜(105)的内侧区域(105a)进行焊料接合。
Description
技术领域
本发明涉及半导体装置及半导体装置的制造方法,特别是涉及具有与大电流容量相对应的配线连接构造的半导体装置和该半导体装置的制造方法。
背景技术
在对大电流进行通断(switching)的半导体装置中,半导体元件的元件电极与外部电极的连接需要与大电流相适应。在该连接中使用通过导线键合法而实现的固相接合的情况下,由铝等制成的、线径较大的多个金属导线并联地进行导线键合。为了应对更大的电流、更高的电压,需要使并联连接的金属导线的数量增多,或者使金属导线的线径增大。在进行这种应对的情况下,由于接合所需的电极面积变大,因此半导体装置的大小会变大。另外,从构造及安装方面考虑,这种应对的困难性提高。因此,也提出有除了导线键合法以外的技术。
根据日本特开2008-182074号公报(专利文献1),公开有下述技术,即,将铜板即外部电极、和半导体元件的元件电极利用焊料进行直接接合。由此,能够实现减小电阻并能够进行大电流通电的连接。
根据日本特开2010-272711号公报(专利文献2),公开有下述技术,即,形成适当厚度的Ni层作为焊料接合用的金属膜,由此提高焊料接合时的可靠性。通过优化Ni厚度,从而能够更加良好地兼顾工艺可行性和接合可靠性。
专利文献1:日本特开2008-182074号公报
专利文献2:日本特开2010-272711号公报
发明内容
在具有半导体元件的半导体装置中,半导体元件的电流流过的部分承受由温度循环引起的热应力。在这种热应力环境下,在具有如专利文献1所公开的接合构造的半导体装置中,为了如专利文献2那样提高接合可靠性,需要将焊料接合用的金属膜形成为适当的厚度。
对于上述金属膜,为了控制在其上对外部电极进行接合时的焊料的展宽形状,而被图案化为适当的形状。对于该图案化,适合采用简便的图案化法即剥离法。对于剥离法中的去除不必要部分的容易度、即剥离性,金属膜的厚度越大,剥离性越低。因此,在金属膜的厚度较大的情况下,有时应当被剥离的部分残存,或者对因剥离而露出的表面造成损伤。这样,在金属膜的厚度较大的情况下,剥离工艺的成品率下降。因此,以较高的生产率形成对焊料的展宽形状进行控制的金属膜很难。
本发明就是为了解决上述问题而提出的,其提供一种半导体装置及半导体装置的制造方法,能够以较高的生产率形成对将外部电极进行接合时的焊料的展宽形状进行控制的金属膜。
本发明的一个方案所涉及的半导体装置具有半导体元件、元件电极、金属膜及外部电极。元件电极设置于半导体元件的表面。金属膜设置于元件电极上,具有内侧区域和位于内侧区域周围的外侧区域。在金属膜中设置有在内侧区域及外侧区域之间将元件电极露出的开口。元件电极具有比金属膜的焊料浸润性低的焊料浸润性。外部电极与金属膜的内侧区域进行焊料接合。
本发明的其他方案所涉及的半导体装置,具有半导体元件、元件电极、金属膜、包覆膜及外部电极。元件电极设置于半导体元件的表面。金属膜设置于元件电极上。包覆膜局部地设置于金属膜上,将金属膜区分为内侧区域和包围内侧区域的外侧区域。包覆膜具有比金属膜的焊料浸润性低的焊料浸润性。外部电极与金属膜的内侧区域进行焊料接合。
本发明的半导体装置的制造方法是上述半导体装置的制造方法,具有下述工序。形成设置有主面的衬底,该主面具有:有效区域,其配置了设置有元件电极的半导体元件;以及有效区域外侧的无效区域。在元件电极上形成金属膜。金属膜包含位于无效区域上的部分。在形成金属膜之后,通过沿无效区域的切割线的切割,切出半导体元件。将外部电极向金属膜的内侧区域进行焊料接合。
发明的效果
根据该发明,能够以较高的生产率,形成对将外部电极进行接合时的焊料的展宽形状进行控制的金属膜。
利用以下的详细说明和附图,使本发明的目的、特征、方案以及优点变得更为明确。
附图说明
图1是表示本发明的实施方式1中的半导体装置的结构的概略剖面图。
图2是表示图1的半导体装置所具有的金属膜的图案的概略俯视图。
图3是沿图2的线III-III的概略局部剖面图。
图4是概略地表示本发明的实施方式1中的半导体装置的制造方法的流程图。
图5是表示本发明的实施方式1中的半导体装置的制造方法的第1工序的概略局部剖面图。
图6是表示本发明的实施方式1中的半导体装置的制造方法的第2工序的概略局部剖面图。
图7是表示本发明的实施方式1中的半导体装置的制造方法的第3工序的概略局部剖面图。
图8是表示本发明的实施方式1中的半导体装置的制造方法的第4工序的概略局部剖面图。
图9是表示图7的工序中的光致抗蚀剂的图案的概略俯视图(A)及其IXB部的放大图(B)。
图10是表示本发明的实施方式2中的半导体装置所具有的金属膜的图案的概略俯视图。
图11是沿图10的线XIA-XIA的概略局部剖面图(A)及沿线XIB-XIB的概略局部剖面图(B)。
图12是表示本发明的实施方式3中的半导体装置所具有的金属膜的图案的概略俯视图。
图13是沿图12的线XIIIA-XIIIA的概略局部剖面图(A)及沿线XIIIB-XIIIB的概略局部剖面图(B)。
图14是表示本发明的实施方式4中的半导体装置所具有的金属膜的图案的概略俯视图。
图15是沿图14的线XV-XV的概略局部剖面图。
图16是表示本发明的实施方式5中的半导体装置所具有的金属膜的图案的概略俯视图。
图17是沿图14的线XVII-XVII的概略局部剖面图。
具体实施方式
(实施方式1)
首先,说明半导体装置200的结构的概要。图1是表示本实施方式所涉及的半导体装置200的构造的剖面图。另外,图2是针对本实施方式的半导体元件101的金属膜105的图案而示出的俯视图。此外,图2中,为了便于观察图,对金属膜105的开口部添加了阴影线。
半导体装置200包含半导体元件101、发射极电极103(元件电极)、金属膜105及外部电极117。发射极电极103设置于半导体元件101的表面。金属膜105设置于发射极电极103上,具有内侧区域105a、和位于内侧区域105a周围的外侧区域105b1。在金属膜105中设置有在内侧区域105a及外侧区域105b1之间将发射极电极103露出的沟槽状开口TR。沟槽状开口TR在内侧区域105a及外侧区域105b1之间以沟槽状设置。由沟槽状开口TR将金属膜105的内侧区域105a及外侧区域105b1分离。发射极电极103具有比金属膜105的焊料浸润性低的焊料浸润性。发射极电极103通过焊料部121在金属膜105的内侧区域105a进行焊料接合。内侧区域105a及外侧区域105b1由相同材料形成。因此,内侧区域105a及外侧区域105b1能够利用相同工序形成,具体地说是能够利用剥离工艺形成。
根据以上的结构,由于在金属膜105的通过剥离工艺实现的图案化时,使外侧区域105b1残存,因此,通过剥离而去除的部分的面积变小。由此,即使金属膜105的厚度比较厚,也能够维持剥离的较高的生产率。此处,对于金属膜105的厚度,为了在软钎焊时充分地保护发射极电极103,优选为大于或等于1μm。
此外,半导体装置200在上述结构的基础上,如图1所示,还可以具有绝缘片111、基座板113、焊料层115、外部另一个电极118、焊料部122、封装材料123、栅极焊盘203(控制用电极)、金属导线213及外部控制电极223。
下面,对更详细的内容进行说明。
半导体元件101例如是在表面侧和背面侧具有电极的纵向型IGBT(Insulated Gate Bipolar Transistor)。在半导体元件101的顶面侧设置有作为第1主电极的发射极电极103。在发射极电极103上形成有金属膜105,金属膜105经由露出部而分离成作为焊料接合用金属膜的内侧区域105a和作为哑金属膜的外侧区域105b1,该露出部以使发射极电极103以沟槽状露出的方式形成开口。以包围发射极电极103的形状形成栅极配线(未图示),与栅极焊盘203电连接。在栅极配线的外侧形成有终端区域205。半导体元件101在金属膜105周围的除了栅极焊盘203以外的区域具有保护膜209。另外,半导体元件101在其底面侧具有作为第2主电极的集电极电极109。集电极电极109经由焊料层115与绝缘片111上的基座板113连接。
发射极电极103由金属形成,优选以Al为主要成分,具体地说,优选由包含大于或等于95%的Al的材料制成。栅极焊盘203可以由与发射极电极103的材料相同的材料制成。另外,通常利用与发射极电极103相同的制造工艺形成栅极焊盘203。通过将主要包含A1的材料用作发射极电极103和栅极焊盘203,从而作为使用了Si衬底等各种衬底而形成的半导体元件的电极,能够利用已有的方法容易地形成、加工。另外,通过以上述方式利用Al,在向栅极焊盘203将金属导线213通过导线键合而进行接合时,能够确保连接可靠性优异的接合。如果Al的含量下降,则电阻增加,因此作为用于处理大电流的半导体装置的电极来说并不优选。通过包含大于或等于95%的Al,从而能够使与Al导线键合的兼容性优异,另外提高导电率。
图3是针对沿图2中的线III-III的构造而示出的概略局部剖面图。在发射极电极103上形成的金属膜105例如是从发射极电极103侧起按顺序层叠有确保密接性用金属膜105c、焊料接合用金属膜105d及防止氧化用金属膜105e的层叠金属膜。作为各金属膜的具体材料,能够将Ti用作确保密接性用金属膜105c,将Ni用作焊料接合用金属膜105d,将Au用作防止氧化用金属膜105e。在发射极电极103上堆积Ti的原因在于,确保使用了主要包含Al的材料的发射极电极103、和由Ni形成的焊料接合用金属膜105d之间的密接性,同时防止焊料接合用金属膜105d的Ni向半导体元件101扩散。用于确保与发射极电极103之间的密接性的确保密接性用金属膜105c可以为除了Ti以外的材料,例如可以为Mo。使用了主要包含Al的材料的发射极电极103很难接合例如SnAgCu类的无Pb焊料,因此,通过隔着Ti来堆积Ni,从而确保与焊料之间的接合性及焊料浸润性。另外,如果Ni膜被氧化,则焊料浸润性下降,因此,出于防止Ni被氧化的目的,堆积Au而作为防止氧化用金属膜105e。防止氧化用金属膜105e可以为除了Au以外的材料,例如可以为Ag。根据如上所述的原因,优选在发射极电极103上,将Ti/Ni/Au膜作为金属膜105而进行堆积,该Ti/Ni/Au膜能够接合SnAgCu类的无Pb焊料且确保了与发射极电极103之间的密接性。
图4表示半导体装置200的制造方法的流程图。首先,参照图5,在步骤S10(图4)中,除了金属膜105的形成以外,大致完成了所谓的晶片级的处理。即,形成设置有主面的晶片(衬底),该主面具有:有效区域,其配置了设置有发射极电极103(元件电极)的半导体元件101;以及有效区域外侧的无效区域。发射极电极103是通过溅射法形成的Al、AlSi或者AlCu膜。该电极可以在氢或者氮气氛内在400~470℃下进行热处理。通过该热处理使得晶体尺寸扩大,另外平坦性提高。由此,能够提高在此后形成的金属膜105的覆盖性。
然后,形成金属膜105(图4:步骤S20)。具体地说,参照图6,首先,涂敷光致抗蚀剂501。参照图7,针对光致抗蚀剂501进行曝光及显影,从而对光致抗蚀剂501进行图案化。这样,光致抗蚀剂501的图案化能够通过光刻法进行。该图案化以下述方式进行,即,使最终不残存有金属膜105的区域被光致抗蚀剂501覆盖。
参照图8,对构成金属膜105的金属膜105c、105d及105e进行成膜。具体地说,利用溅射法等使Ti、Ni及Au按顺序层叠。为了提高对热应力的耐性,优选与Ti及Au相比,使Ni作为金属膜105的主要金属堆积得较厚。通过至少局部地(例如,金属膜105的一部分即金属膜105d的部分)使用如Ni这样硬度较高的材料,从而使金属膜105至少局部地具有比发射极电极103的硬度高的硬度。由此,在后述的向金属膜105进行焊料接合时,能够保护发射极电极103,能够抑制发射极电极103的破坏。另外,如果进行软钎焊,则金属膜105的厚度由于焊料侵蚀而减小,因此,优选使金属膜105的Ni的厚度大于或等于1μm。另外,软钎焊后的Ni剩余厚度优选大于或等于0.5μm,由此,能够充分地保护电极。
再次参照图3,将光致抗蚀剂501及其上的金属膜105f通过剥离工艺而去除。作为剥离工艺的一个例子,存在下面的工艺。首先,将稀释剂用作有机溶剂,使光致抗蚀剂501溶解。接下来,使稀释剂或者纯水以高压力冲至晶片上而以物理方法将光致抗蚀剂501及成膜于其上的金属膜105f去除。这样,在金属膜105中形成具有内侧区域105a及外侧区域105b1的图案。
此处,进一步说明在上述剥离工艺中使用的光致抗蚀剂501(图7)的图案。图9(A)针对晶片100(衬底)的主面整体而示出光致抗蚀剂501(图7)的图案,图9(B)将该IXB部放大而示出。此外,图9(A)及(B)中添加了阴影线的部分表示俯视观察时配置有光致抗蚀剂501的区域。
光致抗蚀剂501具有格子状区域401及沟槽状区域403。沟槽状区域403是用于在金属膜105中形成沟槽状开口TR(图3)的区域。格子状区域401是用于在沿着切割线DL进行晶片100的切割时使切割线DL位于金属膜105的开口的区域。切割线DL上的金属膜105通过剥离至少被部分去除,从而在切割线DL上在金属膜105中形成开口,由此,能够进行其后的更容易的切割。
另外,在光致抗蚀剂501中通过光刻设置开口区域509。在与内侧区域105a(图2)相对应的区域405、与外侧区域105b1相对应的区域407的基础上,开口区域509还具有区域409。区域409配置于用于配置半导体元件101的有效区域ER的外侧。换言之,区域409配置于最终不成为半导体元件101的、晶片100的无效区域IR。无效区域IR包含晶片100的外周区域及切割线DL附近的区域。通过附加区域409,金属膜105中的要进行剥离的部分变得更少。由此,能够更可靠地进行剥离工艺,因此能够提高生产率。
作为光致抗蚀剂501的图案,通过使用图9(A)及(B)所示的图案,从而能够保证金属膜105对焊料形状进行控制的功能,并能够尽可能减少作为多余的金属膜区域而必须去除的区域。
然后,在步骤S30(图4)中,进行沿无效区域IR中的切割线DL的切割。由此,切出半导体元件101。通过将切出的半导体元件101封装而得到半导体装置200(图1)。在该封装工序中,将外部电极117向金属膜105的内侧区域105a进行焊料接合(图4:步骤S40)。下面对该焊料接合工序进行说明。
外部电极117与金属膜105的内侧区域105a之间的、利用焊料部121进行的焊料接合,例如是通过从设置于外部电极117的贯通口119(图1)滴下熔融焊料而进行的。滴下的焊料在内侧区域105a上浸润展宽。该焊料的展宽达到沟槽状开口TR而停止。其原因在于,通过沟槽状开口TR而露出的发射极电极103具有比内侧区域105a的焊料浸润性低的焊料浸润性。在发射极电极103的主要材料为Al的情况下,由于在其表面形成自然氧化膜,因此,发射极电极103露出部的焊料浸润性变差,焊料的浸润展宽在金属膜端部的发射极电极103露出部处停止。由于按照上述方式利用发射极电极103阻碍焊料的浸润展宽,因此,焊料不向与发射极电极103露出部相比位于外侧的外侧区域105b1延展,焊料形状被约束于内侧区域105a内,由此,得到希望形状的焊料部121。
最后,将半导体元件101由封装材料123等封装(图4:步骤S50)。由此,完成安装有外部电极117等的模块即半导体装置200。
根据本实施方式,除了用于焊料接合的内侧区域105a以外,金属膜105还具有外侧区域105b1。即,没有通过剥离将外侧区域105b 1去除。由此,与将外侧区域105b1去除的情况相比,能够减小金属膜105中的通过剥离而去除的比例。由此,能够更容易且可靠地进行剥离。另外,通过剥离而去除的金属膜105f的量少,另外,与其对应地,露出的发射极电极103的面积也小,因此,抑制因剥离时去除的金属膜105f与发射极电极103抵接而引起的损伤的产生。由此,能够提高剥离工艺的成品率。按照上述方式能够更容易且可靠地进行金属膜105的剥离。由此,即便使金属膜105堆积得较厚,也能够维持剥离工艺的成品率,抑制生产率的下降。
(实施方式2)
图10是针对本实施方式所涉及的半导体元件的金属膜105的图案而示出的俯视图。在图10中,为了便于观察图,对金属膜105的开口部添加了阴影线。另外,图11(A)及(B)分别是针对沿图10中的线XIA-XIA及XIB-XIB的构造而示出的概略局部剖面图。
在本实施方式,金属膜105具有内侧区域105a、和位于内侧区域105a周围的外侧区域105b2。外侧区域105b2与外侧区域105b1(图2)相同,是对于焊料接合而言并非必需的哑金属膜。外侧区域105b2具有离散地位于内侧区域105a周边的多个部分。换言之,以这些部分彼此分离的方式,在外侧区域105b2中设置有格子状开口SP。本实施方式的其他结构与实施方式1相同。在内侧区域105a浸润展宽的焊料,不向充分小的外侧区域105b2进行浸润展宽,而是被约束于内侧区域105a内,因此,能够对焊料部121(图1)的形状即焊料接合后的焊料形状进行控制。
根据本实施方式,与实施方式1相比,虽然会增加必须利用剥离工艺去除的金属膜105的区域,但具有在金属膜105的剥离中使用的光致抗蚀剂的总边缘长度增加的优点。由此,在剥离工艺中,稀释剂进入并将光致抗蚀剂溶解的机会增加,因此,能够更容易且可靠地进行剥离。
(实施方式3)
图12是针对本实施方式所涉及的半导体元件上的金属膜105的图案而示出的俯视图。在图12中,为了便于观察图,对金属膜105的开口部添加了阴影线。图13(A)及(B)分别是针对沿图12中的线XIIIA-XIIIA及XIIIB-XIIIB的构造而示出的概略局部剖面图。
在本实施方式中,金属膜105具有内侧区域105a、和位于内侧区域105a周围的外侧区域105b3。在外侧区域105b3中设置有将发射极电极103露出的多个离散开口IL。通过设置离散开口IL,从而如图12所示,内侧区域105a及外侧区域105b3仅以小于或等于尺寸WD(一个尺寸)彼此相连。尺寸WD小到下述程度,即,能够在将熔融的焊料配置于内侧区域105a上的情况下,阻碍从内侧区域105a向外侧区域105b3的焊料的展宽。
利用上述结构,在软钎焊时在金属膜105的内侧区域105a浸润展宽的焊料,受到在离散开口IL中露出的发射极电极103阻挡。具体地说,由于在内侧区域105a周边露出的发射极电极103之间的外侧区域105b3的线宽(图中,尺寸WD)充分地小,因此,焊料并不向内侧区域105a的外侧浸润展宽,而是被约束于内侧区域105a内,因此,能够对焊料部121(图1)的形状即焊料接合后的焊料形状进行控制。本实施方式的其他结构与实施方式1相同。
此外,如图13(A)所示,外侧区域105b3也可以在通过离散开口IL而与内侧区域105a隔开的部分处,具有小于或等于尺寸WD的尺寸。由此,更可靠地防止焊料的浸润展宽。
根据本实施方式,与实施方式1相比,虽然会增加必须利用剥离工艺去除的金属膜105的区域,但具有在金属膜105的剥离中使用的光致抗蚀剂的总边缘长度增加的优点。由此,在剥离工艺中,稀释剂进入并将光致抗蚀剂溶解的机会增加,因此,能够更容易且可靠地进行剥离。
(实施方式4)
图14是针对本实施方式所涉及的半导体元件的金属膜105的图案而示出的俯视图。图14中,为了便于观察图,对金属膜105上的包覆膜1101添加了阴影线。图15是针对沿图14中的线XV-XV的构造而示出的概略局部剖面图。
在本实施方式中,金属膜105具有内侧区域105a、和位于内侧区域105a周围的外侧区域105b4。内侧区域105a及外侧区域105b4构成不具有开口的一体的金属膜。换言之,在内侧区域105a与外侧区域105b4的边界的整体范围内,两者彼此相连。即,金属膜105在发射极电极103上形成于整个面。
在金属膜105上形成有用于在外部电极117(图1)的软钎焊时防止焊料延展的包覆膜1101。包覆膜1101在金属膜105上局部地设置,将金属膜105区分为内侧区域105a和将内侧区域105a包围的外侧区域105b4。外部电极117和金属膜105之间的焊料接合在内侧区域105a上进行。包覆膜1101将内侧区域105a包围。本实施方式的其他结构与实施方式1相同。
包覆膜1101具有比金属膜105的焊料浸润性低的焊料浸润性。从该方面考虑,包覆膜1101优选为由聚酰亚胺构成的绝缘膜。另外,其厚度优选大于或等于2μm左右且小于或等于20μm左右。如果聚酰亚胺的膜厚超过20μm,则因在对聚酰亚胺进行烧结时产生的聚酰亚胺的收缩应力引起的晶片的翘曲容易变得过大。另外,如果试图将聚酰亚胺堆积超过20μm,则容易损坏晶片面内的均匀性。另外,在与包覆膜1101一起集中地形成保护膜209的情况下,该聚酰亚胺还兼用于终端区域205等的包覆保护,如果聚酰亚胺的膜厚小于2μm,则容易在这些终端区域205的台阶部等处产生形成缺陷。
在内侧区域105a上浸润展宽的焊料受到包覆膜1101阻挡,不向与包覆膜1101相比位于外侧的金属膜105即外侧区域105b4浸润展宽,而是被约束于内侧区域105a内,因此,能够对焊料部121(图1)的形状即焊料接合后的焊料形状进行控制。通过将包覆膜1101采用耐热性优异的聚酰亚胺、且使厚度处于2~20μm厚度的范围,从而能够确保工艺的匹配性,并更可靠地阻止焊料的浸润展宽。
通过将包覆膜1101以与设置于半导体元件101的钝化膜(未图示)相同的材料形成,从而能够简化工序。另外,如果集中地形成两者,则能够削减工序数。作为钝化膜的材料,除了聚酰亚胺以外,具有聚苯并恶唑、其他的硅酮类树脂材料等。通过使用这些材料,能够在切割前的晶片工艺中完成包覆膜1101的形成工序。另外,作为在晶片工艺中使用的其他材料,除了以聚酰亚胺、聚苯并恶唑为代表的有机类材料以外,还能够使用以CVD(Chemical Vapor Deposition)法形成的氧化硅膜、氮化硅膜而形成包覆膜1101。在以CVD法形成氮化膜、氧化膜的情况下,由于CVD时的热负载,焊料接合用金属膜105d在防止氧化用金属膜105e上析出,该析出物氧化,从而有可能损害焊料浸润性。为了抑制105e的析出,需要将105e形成得较厚,但在利用Au或Ag形成防止氧化用金属膜105e的情况下,如果增厚该防止氧化用金属膜105e,则成本上升。由此,在利用Au或Ag形成防止氧化用金属膜105e的情况下,包覆膜1101的材料优选为以聚酰亚胺、聚苯并恶唑为代表的有机类材料。
根据本实施方式,与上述的实施方式1~3不同,并不特别需要发射极电极103上的金属膜105的剥离,金属膜105的剥离仅在终端区域205、切割线DL、栅极焊盘203上等上进行即可。由此,能够简化剥离工艺,因此,生产率提高。
(实施方式5)
图16是针对本实施方式所涉及的半导体元件的金属膜105的图案而示出的俯视图。图16中,为了便于观察图,对包覆膜1101添加了阴影线。图17是针对沿图16中的线XVII-XVII的构造而示出的概略局部剖面图。
在本实施方式中,金属膜105具有内侧区域105a、和位于内侧区域105a周围的外侧区域105b5。外侧区域105b5与外侧区域105b1(图2)大致相同。换言之,金属膜105在内侧区域105a和外侧区域105b5之间具有将发射极电极103露出的沟槽状开口TR(图17)。沟槽状开口TR将用于进行焊料接合的区域即内侧区域105a包围。在沟槽状开口TR上形成有用于防止焊料延展的包覆膜1301。如图17所示,包覆膜1301以比沟槽状开口TR的开口宽度宽的宽度,与沟槽状开口TR相同地,将用于进行焊料接合的区域包围。包覆膜1301的材料及形成方法与包覆膜1101(实施方式4)相同。此外,对于除了上述以外的结构,由于与上述的实施方式4的结构大致相同,因此,对相同或者相对应的要素标注相同的标号,省略其说明。
例如,在金属膜105的最表层使用Au、包覆膜1301为聚酰亚胺膜的情况下,如果在金属膜105上形成聚酰亚胺的图案,则由于Au与聚酰亚胺的密接性较低而存在聚酰亚胺在晶片工艺中、焊料接合中脱落的可能性。在本实施方式,由于聚酰亚胺膜和发射极电极103通过金属膜105的沟槽状开口TR而密接,因此,能够防止聚酰亚胺的脱落。在将与金属膜105相比Al含量较多的材料用于发射极电极103的情况下,该效果明显。特别是以包含大于或等于95%的Al的材料形成的发射极电极103与聚酰亚胺的密接性良好,因此,能够进一步降低聚酰亚胺膜脱落的风险。在金属膜105的最表层使用包含Au或者Ag的材料、发射极电极103使用与金属膜105的最表层相比Au或者Ag的含量更少的材料的情况下,也能够得到同样的效果。
根据本实施方式,能够形成与实施方式4的包覆膜1101相比更难脱落的包覆膜1301。因此,能够利用包覆膜1301更可靠地进行焊料部121(图1)的形状的控制。
此外,在本实施方式中,在金属膜105中形成的开口是与实施方式1相同的沟槽状开口TR,但开口的形状并不限定与此。例如,也可以使用与格子状开口SP(图10:实施方式2)或者离散开口IL(图12:实施方式3)相同的形状。
上述各实施方式中的剥离工艺并不限定于通过以高压力使稀释剂、纯水冲向光致抗蚀剂而进行的工艺。剥离例如可以通过对金属膜粘贴胶带、并将该胶带剥下而进行。在该情况下,利用胶带的粘接力将光致抗蚀剂上的金属膜去除。
此外,本发明在其发明的范围内,能够将前述的各实施方式自由地组合,另外,能够对各实施方式的任意的结构要素进行适当的变形或省略。
对本发明进行了详细说明,但上述的说明全部仅为例示,本发明并不限定于此。可以理解为能够在不脱离本发明的范围的情况下假想出未例示出的许多的变形例。
(附记)
本说明书包含以下(i)~(ix)的公开内容。
(i)一种半导体装置(200),其特征在于,具有:
半导体元件(101);
电极(103),其设置于所述半导体元件的表面;
第1金属膜(105a),其以对焊料接合后的焊料形状进行控制的形状设置在所述电极的表面;
第2金属膜(105b1),其以下述形状配置,即,以形成露出部的方式将所述电极的除了所述第1金属膜以外的区域覆盖,该露出部形成沿着所述第1金属膜的外周而以沟槽状将所述电极露出的开口(TR);以及
外部电极(117),其与所述第1金属膜进行焊料接合。
该半导体装置的结构例如能够从上述实施方式1读出。
(ii)一种半导体装置(200),其特征在于,具有:
半导体元件(101);
电极(103),其设置于半导体元件表面;
第1金属膜(105a),其以对焊料接合后的焊料形状进行控制的形状设置在所述电极的表面;
多个第2金属膜(105b2),它们以比所述第1金属膜小的形状离散地配置于露出了所述第1金属膜周边的所述电极的露出部;以及
外部电极(117),其与所述第1金属膜进行焊料接合。
该半导体装置的结构例如能够从上述实施方式2读出。
(iii)一种半导体装置(200),其特征在于,具有:
半导体元件(101);
电极(103),其设置于半导体元件表面;
第1金属膜(105),其设置于所述电极的表面;以及
外部电极(117),其与所述第1金属膜进行焊料接合,
所述第1金属膜具有:
焊料接合区域(105a),其用于与所述外部电极进行焊料接合;以及
露出部(IL),其以成为阻碍焊料延展的细线宽(WD)的方式在除了所述焊料接合区域以外的区域使所述电极露出。
该半导体装置的结构例如能够从上述实施方式3读出。
(iv)根据上述(i)~(iii)中任一项所述的半导体装置(200),其特征在于,
具有包覆膜(1301),该包覆膜(1301)以对焊料接合时的焊料形状进行控制的形状而设置在所述露出部上。
该半导体装置的结构例如能够从上述实施方式5读出。
(v)一种半导体装置(200),其特征在于,具有:
半导体元件(101);
电极(103),其设置于半导体元件表面;
金属膜(105),其设置于所述电极的表面;以及
包覆膜(1101),其以对焊料接合时的焊料形状进行控制的形状设置在所述金属膜上。
该半导体装置的结构例如能够从上述实施方式4读出。
(vi)根据上述(iv)或者(v)所述的半导体装置,其特征在于,所述包覆膜由厚度为2~20μm的聚酰亚胺形成。
(vii)根据上述(i)~(vi)中任一项所述的半导体装置,其特征在于,所述电极由包含大于或等于95%的铝的材料构成。
(viii)一种半导体装置的制造方法,其用于制造上述(i)~(vii)中任一项所述的半导体装置,
该制造方法的特征在于,在所述第1金属膜的形成工序中,在晶片(100)面内整个区域中,在不作为半导体装置使用的无效区域(IR)上也形成与所述第1金属膜等同的金属膜。
(ix)根据上述(viii)所述的半导体装置的制造方法,其特征在于,在所述无效区域上的金属膜中形成开口,所述开口位于切割线(DL)上。
标号的说明
100晶片(衬底),101半导体元件,103发射极电极(元件电极),105金属膜,105a内侧区域,105b1~105b5外侧区域,117外部电极,121焊料部,200半导体装置,1101、1301包覆膜,DL切割线,ER有效区域,IL离散开口(开口),IR无效区域,SP格子状开口(开口),TR沟槽状开口(开口)。
Claims (16)
1.一种半导体装置,其具有:
半导体元件(101);
元件电极(103),其设置于所述半导体元件的表面;以及
金属膜(105),其设置于所述元件电极上,具有内侧区域(105a)和位于所述内侧区域周围的外侧区域(105b1~105b3),
在所述金属膜中设置有在所述内侧区域及所述外侧区域之间将所述元件电极露出的开口(TR、SP、IL),所述元件电极具有比所述金属膜的焊料浸润性低的焊料浸润性,
该半导体装置还具有外部电极(117),该外部电极(117)与所述金属膜的所述内侧区域进行焊料接合。
2.根据权利要求1所述的半导体装置,其中,
所述金属膜的所述内侧区域及所述外侧区域(105b1、105b2)通过所述开口(TR、SP)而分离。
3.根据权利要求2所述的半导体装置,其中,
所述开口(TR)在所述金属膜的所述内侧区域及所述外侧区域(105b1)之间以沟槽状设置。
4.根据权利要求2所述的半导体装置,其中,
所述金属膜的所述外侧区域(105b2)具有离散地配置的多个部分。
5.根据权利要求1所述的半导体装置,其中,
所述金属膜的所述内侧区域及所述外侧区域(105b3)仅以小于或等于一个尺寸(WD)彼此相连,所述一个尺寸小到下述程度,即,在将熔融的焊料配置于所述金属膜的所述内侧区域上的情况下,阻碍从所述内侧区域向所述外侧区域的焊料的展宽。
6.根据权利要求1至5中任一项所述的半导体装置,其中,
所述金属膜的所述内侧区域及所述外侧区域由相同材料形成。
7.根据权利要求1至5中任一项所述的半导体装置,其中,
所述金属膜的所述内侧区域及所述外侧区域在相同工序中形成。
8.根据权利要求1至5中任一项所述的半导体装置,其中,
所述金属膜至少局部地具有比所述元件电极的硬度高的硬度。
9.根据权利要求1至5中任一项所述的半导体装置,其中,
所述金属膜具有大于或等于1μm的厚度。
10.一种半导体装置,其具有:
半导体元件(101);
元件电极(103),其设置于所述半导体元件的表面;
金属膜(105),其设置于所述元件电极上;
包覆膜(1101、1301),其局部地设置于所述金属膜上,将所述金属膜区分为内侧区域(105a)和将所述内侧区域包围的外侧区域(105b4、105b5),具有比所述金属膜的焊料浸润性低的焊料浸润性;以及
外部电极(117),其与所述金属膜的所述内侧区域进行焊料接合。
11.根据权利要求10所述的半导体装置,其中,
所述金属膜的所述内侧区域及所述外侧区域(105b4)在所述内侧区域和所述外侧区域的边界的整体范围内彼此相连。
12.根据权利要求10所述的半导体装置,其中,
在所述金属膜中设置有在所述内侧区域及所述外侧区域之间将所述元件电极露出的开口,所述包覆膜(1301)配置于所述开口。
13.根据权利要求10至12中任一项所述的半导体装置,其中,
所述包覆膜包含厚度大于或等于2μm而小于或等于20μm的聚酰亚胺膜。
14.根据权利要求10至12中任一项所述的半导体装置,其中,
所述元件电极由包含大于或等于95%的铝的材料制成。
15.一种半导体装置的制造方法,其用于制造权利要求1至5及10至12中任一项所述的半导体装置,
该制造方法具有下述工序:
形成设置有主面的衬底(100),其中,该主面具有有效区域(ER)以及所述有效区域外侧的无效区域(IR),在该有效区域(ER)配置了设置有所述元件电极的所述半导体元件;以及
在所述元件电极上形成所述金属膜,
所述金属膜包含位于所述无效区域上的部分,并且,
该制造方法具有下述工序:
在形成所述金属膜之后,通过沿所述无效区域中的切割线(DL)的切割,切出所述半导体元件;以及
将所述外部电极向所述金属膜的所述内侧区域进行焊料接合。
16.根据权利要求15所述的半导体装置的制造方法,其中,
形成所述金属膜的工序包含在所述切割线上在所述金属膜中形成开口的工序。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013-046905 | 2013-03-08 | ||
JP2013046905 | 2013-03-08 | ||
PCT/JP2013/077115 WO2014136303A1 (ja) | 2013-03-08 | 2013-10-04 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105009266A true CN105009266A (zh) | 2015-10-28 |
CN105009266B CN105009266B (zh) | 2018-05-08 |
Family
ID=51490849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380074382.6A Active CN105009266B (zh) | 2013-03-08 | 2013-10-04 | 半导体装置及半导体装置的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10157865B2 (zh) |
JP (1) | JP6038280B2 (zh) |
CN (1) | CN105009266B (zh) |
DE (1) | DE112013006790B8 (zh) |
WO (1) | WO2014136303A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112703584A (zh) * | 2018-09-26 | 2021-04-23 | 三菱电机株式会社 | 半导体装置、电力变换装置以及半导体装置的制造方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109923647B (zh) | 2016-11-08 | 2023-06-20 | 三菱电机株式会社 | 半导体装置 |
CN110476235B (zh) * | 2017-03-27 | 2024-02-23 | 三菱电机株式会社 | 半导体装置、电力变换装置 |
DE112017007960B4 (de) * | 2017-09-04 | 2023-06-29 | Mitsubishi Electric Corporation | Halbleitermodul und Leistungsumwandlungsvorrichtung |
DE102018125300A1 (de) * | 2018-10-12 | 2020-04-16 | Osram Opto Semiconductors Gmbh | Elektronisches Bauteil und Verfahren zum Aufbringen von zumindest einem Lötpad auf ein elektronisches Bauteil |
JP7472435B2 (ja) | 2019-05-13 | 2024-04-23 | 富士電機株式会社 | 半導体モジュールの製造方法 |
JP2022144711A (ja) * | 2021-03-19 | 2022-10-03 | 三菱電機株式会社 | 半導体装置の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006210519A (ja) * | 2005-01-26 | 2006-08-10 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
US20100123240A1 (en) * | 2008-11-18 | 2010-05-20 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
US20110312134A1 (en) * | 2009-10-07 | 2011-12-22 | Renesas Electronics Corporation | Manufacturing method for semiconductor devices |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4078993B2 (ja) | 2003-01-27 | 2008-04-23 | 三菱電機株式会社 | 半導体装置 |
JP2005183782A (ja) | 2003-12-22 | 2005-07-07 | Sony Corp | リフトオフ法に基づくパターン形成方法 |
US7569422B2 (en) * | 2006-08-11 | 2009-08-04 | Megica Corporation | Chip package and method for fabricating the same |
JP4640345B2 (ja) | 2007-01-25 | 2011-03-02 | 三菱電機株式会社 | 電力用半導体装置 |
DE102008042777A1 (de) | 2008-10-13 | 2010-04-15 | Robert Bosch Gmbh | Selektiver Lötstop |
JP2010232230A (ja) * | 2009-03-25 | 2010-10-14 | Casio Computer Co Ltd | 半導体装置およびその製造方法 |
JP2010272711A (ja) | 2009-05-22 | 2010-12-02 | Mitsubishi Electric Corp | 半導体デバイスとその製造方法 |
-
2013
- 2013-10-04 WO PCT/JP2013/077115 patent/WO2014136303A1/ja active Application Filing
- 2013-10-04 CN CN201380074382.6A patent/CN105009266B/zh active Active
- 2013-10-04 DE DE112013006790.0T patent/DE112013006790B8/de active Active
- 2013-10-04 US US14/769,387 patent/US10157865B2/en active Active
- 2013-10-04 JP JP2015504118A patent/JP6038280B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006210519A (ja) * | 2005-01-26 | 2006-08-10 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
US20100123240A1 (en) * | 2008-11-18 | 2010-05-20 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
US20110312134A1 (en) * | 2009-10-07 | 2011-12-22 | Renesas Electronics Corporation | Manufacturing method for semiconductor devices |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112703584A (zh) * | 2018-09-26 | 2021-04-23 | 三菱电机株式会社 | 半导体装置、电力变换装置以及半导体装置的制造方法 |
CN112703584B (zh) * | 2018-09-26 | 2024-05-14 | 三菱电机株式会社 | 半导体装置、电力变换装置以及半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP6038280B2 (ja) | 2016-12-07 |
DE112013006790B8 (de) | 2022-08-18 |
CN105009266B (zh) | 2018-05-08 |
WO2014136303A1 (ja) | 2014-09-12 |
DE112013006790B4 (de) | 2022-05-25 |
US10157865B2 (en) | 2018-12-18 |
JPWO2014136303A1 (ja) | 2017-02-09 |
US20160005703A1 (en) | 2016-01-07 |
DE112013006790T5 (de) | 2015-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105009266A (zh) | 半导体装置及半导体装置的制造方法 | |
JP2833996B2 (ja) | フレキシブルフィルム及びこれを有する半導体装置 | |
US20070246808A1 (en) | Power semiconductor module having surface-mountable flat external contacts and method for producing the same | |
US9911705B2 (en) | Semiconductor device and semiconductor device manufacturing method | |
KR20020030258A (ko) | 반도체 장치 및 그 제조 방법 | |
US20110115092A1 (en) | Semiconductor device and method of manufacturing same | |
US20220238481A1 (en) | Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate | |
CN103620762A (zh) | 半导体装置 | |
CN103855122B (zh) | 包括压缩应力的封装垂直功率器件及其制造方法 | |
JP2007157844A (ja) | 半導体装置、および半導体装置の製造方法 | |
US20080001244A1 (en) | System Comprising an Electrical Component and an Electrical Connecting Lead for Said Component, and Method for the Production of Said System | |
JPH10326806A (ja) | 半導体装置およびその製造方法 | |
WO2018131144A1 (ja) | 半導体装置及びその製造方法 | |
US7339267B2 (en) | Semiconductor package and method for forming the same | |
KR20180090200A (ko) | 혹독한 매체 적용에 있어서의 본드 패드 보호 | |
JP2009516369A (ja) | チップアセンブリ及びそのチップアセンブリの製造方法 | |
KR100572565B1 (ko) | 탄성 표면파 장치의 제조방법 | |
CN107615463A (zh) | 半导体装置的制造方法 | |
US6548386B1 (en) | Method for forming and patterning film | |
CN106206540B (zh) | 半导体装置及其制造方法 | |
JP5003418B2 (ja) | 半導体装置とその製造方法 | |
CN103050460B (zh) | 半导体装置及其制造方法 | |
JP2011091087A (ja) | 半導体装置とその製造方法 | |
JP5098204B2 (ja) | 半導体装置及びその製造方法、並びに、電子機器 | |
JP5847363B1 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |