JP2010123686A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2010123686A JP2010123686A JP2008294816A JP2008294816A JP2010123686A JP 2010123686 A JP2010123686 A JP 2010123686A JP 2008294816 A JP2008294816 A JP 2008294816A JP 2008294816 A JP2008294816 A JP 2008294816A JP 2010123686 A JP2010123686 A JP 2010123686A
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- metal plate
- solder
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Abstract
【解決手段】リードフレーム41のチップ搭載部2上に半導体チップ3を半田11aを介して搭載し、半導体チップ3のソースパッド電極3sおよびリードフレーム41のリード部4a上に半田11b、11cを介して金属板6を配置し、半田リフロー処理を行うことで、半導体チップ3をチップ搭載部2に半田11aで接合し、金属板6をソースパッド電極3sおよびリード部4に半田11b,11cで接合する。リードフレーム41は、銅合金で形成して軟化温度を半田リフローの温度よりも高くしておき、金属板6は、無酸素銅で形成して軟化温度を半田リフローの温度よりも低くしておくことで、半田リフロー時に金属板6を軟化させる。その後、半導体チップ3のゲートパッド電極3gとリード部5aをワイヤ7で接続し、封止樹脂部8を形成してから、リードフレーム41を切断する。
【選択図】図24
Description
α1=(H4−H3)/H4
で表される。百分率表示の場合は、これを100倍すればよいので、
α1=[(H4−H3)/H4]×100(単位は%)
と表される。なお、前式中のH4は、ステップS4の半田リフロー工程前の金属板6の硬度(室温での硬度)であり、ステップS3の搭載工程から、ステップS4の半田リフローで加熱する前まで、金属板6の硬度はほとんど変化しないため、H4は初期硬度H1とほぼ同じ値(H4=H1)である。このため、
α1=[(H1−H3)/H1]×100(単位は%)
と表すこともできる。また、H3は、上述のように、ステップS4の半田リフロー工程後の金属板6の硬度である。ステップS4の半田リフロー工程の前後で、金属板6の硬度が、H4からH3に低下するのである。
α2=(H6−H5)/H6
で表される。百分率表示の場合は、これを100倍すればよいので、
α2=[(H6−H5)/H6]×100(単位は%)
と表される。なお、前式中のH6は、ステップS4の半田リフロー工程前のリードフレーム41の硬度(室温での硬度)であり、H5は、ステップS4の半田リフロー工程後のリードフレーム41の硬度(室温での硬度)である。ステップS4の半田リフロー工程の前後で、リードフレーム41の硬度が、H6からH5に低下するのである。
2 チップ搭載部
2a 上面
2b 下面
2c1,2c2,2d1,2d2 側面
3 半導体チップ
3a 表面
3b 裏面
3d 裏面ドレイン電極
3g ゲートパッド電極
3s ソースパッド電極
4,5,15 リード部
4a,5a インナリード部
4b,5b アウタリード部
6 金属板
6A1 第1部分
6A2 第2部分
6A3 第3部分
7 ワイヤ
8 封止樹脂部
8a 上面
8b 裏面
8c1,8c2,8d1,8d2 側面
11a,11b,11c,11d 半田
11e,11f 半田ペースト
12 吊りリード
14 メッキ層
16,17 開口部
18 スリット
21 半導体基板
21a 基板本体
21b エピタキシャル層
22 フィールド絶縁膜
23 半導体領域
24 半導体領域
25 溝
26 ゲート絶縁膜
27 ゲート電極
27a ゲート引き出し用の配線部
28 絶縁膜
29a,29b コンタクトホール
30G ゲート配線
30S ソース配線
31 半導体領域
32 保護膜
33 開口部
34,34a,34b 金属層
41 リードフレーム
42 フレーム枠
43 タイバー
44 開口部
51 実装基板
51a 上面
52,52d,52g,52s 基板側端子
53 半田
H0,H1,H2 初期硬度
H3,H4,H5,H6 硬度
PWL1 p型ウエル
T0,T1,T2 軟化温度
T3 温度
α1,α2 低下率
Claims (25)
- チップ搭載部と、
第1主面、前記第1主面に形成された第1電極、および前記第1主面とは反対側の第2主面を有し、前記第2主面が前記チップ搭載部と対向するように前記チップ搭載部上に搭載された半導体チップと、
前記チップ搭載部から離間して配置された第1リード部と、
前記半導体チップの前記第1電極と前記第1リード部とを電気的に接続する金属板と、
前記チップ搭載部の一部、前記第1リード部の一部、前記半導体チップ、および前記金属板を覆う封止体と、
を有し、
前記金属板の硬度が、前記チップ搭載部および前記第1リード部の硬度よりも低いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記金属板は、前記半導体チップの前記第1電極と前記第1リード部とに、それぞれ半田接続されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記金属板は、無酸素銅からなり、
前記チップ搭載部および前記第1リード部は、銅合金からなることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記チップ搭載部および前記第1リード部の軟化温度は、前記金属板を前記半導体チップの前記第1電極と接続する第1半田の融点、および前記金属板を前記第1リード部と接続する第2半田の融点よりも高いことを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記半導体チップは、前記チップ搭載部に半田接続されており、
前記チップ搭載部および前記第1リード部の軟化温度は、前記半導体チップを前記チップ搭載部に接続する第3半田の融点よりも高いことを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記チップ搭載部および前記第1リード部の軟化温度は、前記第1半田の融点、前記第2半田の融点および前記第3半田の融点よりも、50℃以上高いことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記半導体チップの前記第2主面には、前記半導体チップの裏面電極が形成されており、
前記半導体チップの前記裏面電極は、前記チップ搭載部に前記第3半田を介して電気的に接続されていることを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記半導体チップの前記第1主面に形成された第2電極と、
前記チップ搭載部および前記第1リード部から離間して配置された第2リード部と、
前記半導体チップの前記第2電極と、前記第2リード部とを電気的に接続する導電性ワイヤと、
を更に有し、
前記封止体は、前記第2リード部の一部と前記導電性ワイヤも覆っていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記半導体チップには、MISFETが形成されており、
前記第1電極は、前記MISFETのソース用の電極パッドであり、
前記第2電極は、前記MISFETのゲート電極用の電極パッドであり、
前記裏面電極は、前記MISFETのドレイン用の裏面電極であることを特徴とする半導体装置。 - (a)チップ搭載部および第1リード部を有するリードフレームを用意する工程、
(b)前記(a)工程後、第1主面、前記第1主面に形成された第1電極、および前記第1主面とは反対側の第2主面を有する半導体チップを、前記第2主面が前記チップ搭載部と対向するように、前記リードフレームの前記チップ搭載部上に接合材を介して搭載する工程、
(c)前記(b)工程後、前記半導体チップの前記第1電極上に第1半田を介し、前記第1リード部上に第2半田を介して、金属板を配置する工程、
(d)前記(c)工程後、前記第1半田および前記第2半田を溶融する熱処理を行って、前記金属板を、前記第1半田を介して前記半導体チップの前記第1電極に接合し、前記第2半田を介して前記第1リード部に接合する工程、
(e)前記(d)工程後、前記チップ搭載部の一部、前記第1リード部の一部、前記半導体チップ、および前記金属板を覆う封止体を形成する工程、
を有し、
前記(c)工程で用いられた前記金属板の軟化温度が、前記(a)工程で準備された前記リードフレームの軟化温度よりも低いことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(a)工程で用意された前記リードフレームの軟化温度は、前記(d)工程の前記熱処理の温度よりも高く、
前記(c)工程で用いられた前記金属板の軟化温度は、前記(d)工程の前記熱処理の温度よりも低いことを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(d)工程の前記熱処理後の前記金属板の硬度は、前記(d)工程の前記熱処理後の前記リードフレームの硬度よりも低いことを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記金属板は、無酸素銅からなり、
前記リードフレームは、銅合金からなることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(e)工程後、
(f)前記封止体の外部の前記リードフレームを切断する工程、
を更に有し、
前記(a)工程の後、前記(f)工程で前記リードフレームを切断するまで、前記リードフレームは、前記リードフレームの軟化温度以上の温度にはならないことを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記(c)工程で用いられた前記金属板の軟化温度が、前記(d)工程の前記熱処理の熱処理温度よりも50℃以上低いことを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記(a)工程で準備された前記リードフレームの軟化温度が、前記(d)工程の前記熱処理の熱処理温度よりも50℃以上高いことを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記(c)工程で用いられた前記金属板の軟化温度が、150℃以上であることを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記接合材は、第3半田からなり、
前記(d)工程の前記熱処理では、前記第3半田も溶融されることを特徴とする半導体装置の製造方法。 - 請求項18記載の半導体装置の製造方法において、
前記半導体チップの前記第2主面には、前記半導体チップの裏面電極が形成されており、
前記(d)工程では、前記半導体チップの前記裏面電極が、前記第3半田を介して前記チップ搭載部に接合されることを特徴とする半導体装置の製造方法。 - 請求項19記載の半導体装置の製造方法において、
前記リードフレームは第2リード部を更に有し、
前記半導体チップは、前記第1主面に形成された第2電極を更に有し、
前記(d)工程後で、前記(e)工程前に、
前記半導体チップの前記第2電極と前記第2リード部とを導電性ワイヤを介して電気的に接続する工程、
を更に有し、
前記(e)工程では、
前記封止体は、前記チップ搭載部の一部、前記第1リード部の一部、前記第2リード部の一部、前記半導体チップ、前記金属板、および前記導電性ワイヤを覆うように形成されることを特徴とする半導体装置の製造方法。 - 請求項20記載の半導体装置の製造方法において、
前記半導体チップには、MISFETが形成されており、
前記第1電極は、前記MISFETのソース用の電極パッドであり、
前記第2電極は、前記MISFETのゲート電極用の電極パッドであり、
前記裏面電極は、前記MISFETのドレイン用の裏面電極であることを特徴とする半導体装置の製造方法。 - (a)チップ搭載部および第1リード部を有するリードフレームを用意する工程、
(b)前記(a)工程後、第1主面、前記第1主面に形成された第1電極、および前記第1主面とは反対側の第2主面を有する半導体チップを、前記第2主面が前記チップ搭載部と対向するように、前記リードフレームの前記チップ搭載部上に接合材を介して搭載する工程、
(c)前記(b)工程後、前記半導体チップの前記第1電極上に第1半田を介し、前記第1リード部上に第2半田を介して、金属板を配置する工程、
(d)前記(c)工程後、前記第1半田および前記第2半田を溶融する熱処理を行って、前記金属板を、前記第1半田を介して前記半導体チップの前記第1電極に接合し、前記第2半田を介して前記第1リード部に接合する工程、
(e)前記(d)工程後、前記チップ搭載部の一部、前記第1リード部の一部、前記半導体チップ、および前記金属板を覆う封止体を形成する工程、
を有し、
前記(d)工程の前記熱処理による前記金属板の硬度の低下率が、前記(d)工程の前記熱処理による前記リードフレームの硬度の低下率よりも大きいことを特徴とする半導体装置の製造方法。 - 請求項22記載の半導体装置の製造方法において、
前記(d)工程の前記熱処理後の前記金属板の硬度は、前記(d)工程の前記熱処理後の前記リードフレームの硬度よりも低いことを特徴とする半導体装置の製造方法。 - 請求項23記載の半導体装置の製造方法において、
前記金属板は、無酸素銅からなり、
前記リードフレームは、銅合金からなることを特徴とする半導体装置の製造方法。 - 請求項24記載の半導体装置の製造方法において、
前記(d)工程の前記熱処理によって、前記金属板の硬度が、前記熱処理前の硬度の80%未満となることを特徴とする半導体装置の製造方法。
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US8299600B2 (en) | 2012-10-30 |
US20100123240A1 (en) | 2010-05-20 |
JP5384913B2 (ja) | 2014-01-08 |
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