CN103887188A - 大电流半导体器件的封装工艺 - Google Patents

大电流半导体器件的封装工艺 Download PDF

Info

Publication number
CN103887188A
CN103887188A CN201410119228.2A CN201410119228A CN103887188A CN 103887188 A CN103887188 A CN 103887188A CN 201410119228 A CN201410119228 A CN 201410119228A CN 103887188 A CN103887188 A CN 103887188A
Authority
CN
China
Prior art keywords
chip
bearing frame
semiconductor device
packaging technology
current semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410119228.2A
Other languages
English (en)
Inventor
江炳煌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Fushun Semiconductor Manufacturing Co Ltd
Original Assignee
Fujian Fushun Semiconductor Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Fushun Semiconductor Manufacturing Co Ltd filed Critical Fujian Fushun Semiconductor Manufacturing Co Ltd
Priority to CN201410119228.2A priority Critical patent/CN103887188A/zh
Publication of CN103887188A publication Critical patent/CN103887188A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明涉及一种大电流半导体器件的封装工艺,包括以下步骤:S01:设计一承载框架和一与所述承载框架对应的接触导电框架;S02:在所述承载框架上先点锡膏,再上芯片,以利于将芯片黏贴于所述承载框架上;S03:在芯片的铝垫上点锡膏,再将所述接触导电框架对位后压平;S04:进行高温回流焊;S05:进行塑封。本发明是利用预先设计好的一对上下对位的铜框架,没有超声波和挤压的力道施加于芯片,因此不会伤到芯片里层的电路,不会有可靠性的问题,同时互连是用铜框架上的铜片,其宽度可依电流的大小设计,可耐大电流,工艺技术也不需昂贵的机台设备,既可靠又经济。

Description

大电流半导体器件的封装工艺
技术领域
本发明涉及一种大电流半导体器件的封装工艺。
背景技术
现今大电流的半导体封装互连还是利用打线机将铝线或铝带以超声波打线方式将芯片的接触铝垫与铜框架的引脚压黏形成导电通路,此法提供的导电电流需视铝线的直径大小或是铝带的宽窄来决定,但因铝线/带的打线工艺技术有其最大线径与线宽的限制,有些产品需要并排的打上2~10条的铝线/带才能达到数十安培的大电流需求,在打线工艺上需要用到价格昂贵的超声波打线/带机,打线成本高,同时芯片本体也容易因芯片打点多而造成芯片内部电路的挤压破坏而产生产品的最终可靠性问题。原工艺流程:框架点导电胶à上芯片à烘烤à超声波焊铝线/带à塑封。
发明内容
有鉴于此,本发明的目的是提供一种大电流半导体器件的封装工艺。
本发明采用以下方案实现:一种大电流半导体器件的封装工艺,其特征在于,包括以下步骤:
S01:设计一承载框架和一与所述承载框架对应的接触导电框架;
S02:在所述承载框架上先点锡膏,再上芯片,以利于将芯片黏贴于所述承载框架上;
S03:在芯片的铝垫上点锡膏,再将所述接触导电框架对位后压平;
S04:将所述步骤S03中对位后的承载框架和接触导电框架进行高温回流焊;
S05:将所述步骤S04中过高温回流焊的承载框架和接触导电框架进行塑封。
在本发明一实施例中,所述承载框架包括一用于承载芯片的承载位。
在本发明一实施例中,所述承载框架还包括一个或多个有利于大电流通过的引脚。
在本发明一实施例中,所述引脚个数为2个。
在本发明一实施例中,所述接触导电框架包括一用于与芯片的铝垫接触的触片。
在本发明一实施例中,所述接触导电框架还包括一个或多个有利于大电流通过的引脚。
在本发明一实施例中,所述引脚个数为2个。
本发明是利用预先设计好的一对上下对位的铜框架,互连是利用锡膏,没有超声波和挤压的力道施加于芯片,因此不会伤到芯片里层的电路,不会有可靠性的问题,同时互连是用铜框架上的铜片,其宽度可依电流的大小设计,可耐大电流,工艺技术也不需昂贵的机台设备,既可靠又经济。
为使本发明的目的、技术方案及优点更加清楚明白,以下将通过具体实施例和相关附图,对本发明作进一步详细说明。
附图说明
图1是本发明的工艺流程图。
图2是本发明的结构示意图。
具体实施方式
如图1所示,本发明提供一种大电流半导体器件的封装工艺,包括以下步骤:
S01:设计一承载框架和一与所述承载框架对应的接触导电框架;
S02:在所述承载框架上先点锡膏,再上芯片,以利于将芯片黏贴于所述承载框架上;
S03:在芯片的铝垫上点锡膏,再将所述接触导电框架对位后压平;
S04:将所述步骤S03中对位后的承载框架和接触导电框架进行高温回流焊;
S05:将所述步骤S04中过高温回流焊的承载框架和接触导电框架进行塑封,得到大电流半导体器件封装结构。后工序与现有技术中的工序一样。
优选的,所述承载框架包括一用于承载芯片的承载位;所述承载框架还包括一个或多个(优选为两个)有利于大电流通过的引脚;所述接触导电框架包括一用于与芯片的铝垫接触的触片;所述接触导电框架还包括一个或多个(优选为两个)有利于大电流通过的引脚。如图2所示,所述大电流半导体器件包括一封装外壳(图中未示出),所述封装外壳内设有承载片1,所述承载片1包括承载位11和承载引脚12,所述承载位11通过下层锡膏4与芯片3紧密接触,所述芯片3的铝垫通过上层锡膏5与接触导电片2紧密接触,所述接触导电片2包括用于与所述芯片的铝垫接触的触片21和接触导电引脚22。
上列较佳实施例,对本发明的目的、技术方案和优点进行了进一步详细说明,所应理解的是,以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (7)

1.一种大电流半导体器件的封装工艺,其特征在于,包括以下步骤:
S01:设计一承载框架和一与所述承载框架对应的接触导电框架;
S02:在所述承载框架上先点锡膏,再上芯片,以利于将芯片黏贴于所述承载框架上;
S03:在芯片的铝垫上点锡膏,再将所述接触导电框架对位后压平;
S04:将所述步骤S03中对位后的承载框架和接触导电框架进行高温回流焊;
S05:将所述步骤S04中过高温回流焊的承载框架和接触导电框架进行塑封。
2.根据权利要求1所述的大电流半导体器件的封装工艺,其特征在于:所述承载框架包括一用于承载芯片的承载位。
3.根据权利要求2所述的大电流半导体器件的封装工艺,其特征在于:所述承载框架还包括一个或多个有利于大电流通过的引脚。
4.根据权利要求3所述的大电流半导体器件的封装工艺,其特征在于:所述引脚个数为2个。
5.根据权利要求1所述的大电流半导体器件的封装工艺,其特征在于:所述接触导电框架包括一用于与芯片的铝垫接触的触片。
6.根据权利要求5所述的大电流半导体器件的封装工艺,其特征在于:所述接触导电框架还包括一个或多个有利于大电流通过的引脚。
7.根据权利要求6所述的大电流半导体器件的封装工艺,其特征在于:所述引脚个数为2个。
CN201410119228.2A 2014-03-28 2014-03-28 大电流半导体器件的封装工艺 Pending CN103887188A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410119228.2A CN103887188A (zh) 2014-03-28 2014-03-28 大电流半导体器件的封装工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410119228.2A CN103887188A (zh) 2014-03-28 2014-03-28 大电流半导体器件的封装工艺

Publications (1)

Publication Number Publication Date
CN103887188A true CN103887188A (zh) 2014-06-25

Family

ID=50956024

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410119228.2A Pending CN103887188A (zh) 2014-03-28 2014-03-28 大电流半导体器件的封装工艺

Country Status (1)

Country Link
CN (1) CN103887188A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449480A (zh) * 2016-10-20 2017-02-22 广东美的制冷设备有限公司 回流工装、半导体封装方法、半导体封装件及空调器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100123240A1 (en) * 2008-11-18 2010-05-20 Renesas Technology Corp. Semiconductor device and manufacturing method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100123240A1 (en) * 2008-11-18 2010-05-20 Renesas Technology Corp. Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449480A (zh) * 2016-10-20 2017-02-22 广东美的制冷设备有限公司 回流工装、半导体封装方法、半导体封装件及空调器
CN106449480B (zh) * 2016-10-20 2019-12-06 广东美的制冷设备有限公司 回流工装、半导体封装方法、半导体封装件及空调器

Similar Documents

Publication Publication Date Title
CN106298722B (zh) 一种大电流功率半导体器件的封装结构及制造方法
CN211150513U (zh) 封装体
CN103926430B (zh) 一种硅通孔转接板测试方法
CN105489571A (zh) 一种带散热片的半导体封装及其封装方法
CN212113710U (zh) 一种引线框架及焊接铝箔的芯片封装结构
CN103887188A (zh) 大电流半导体器件的封装工艺
CN106098649A (zh) 大功率贴片元件及其加工工装、制作方法
CN206774530U (zh) 用于双基岛封装电路的引线框架
CN203760459U (zh) 大电流半导体器件结构
CN104617002A (zh) 一种半导体封装方法及结构
CN201829490U (zh) 芯片区打孔集成电路引线框架
CN102157480A (zh) 桥式整流器
CN103730441A (zh) 引线框架以及使用该引线框架的半导体器件的封装方法
CN210040259U (zh) 一种大功率霍尔器件用引线框架及其封装结构
US20160093556A1 (en) Quad-flat non-lead package structure and method of packaging the same
CN207818566U (zh) 预塑封导线框架条
CN104538378A (zh) 一种圆片级封装结构及其工艺方法
CN105633051A (zh) 部分框架外露多芯片多搭平铺夹芯封装结构及其工艺方法
CN206451702U (zh) 一种dfn大功率集成器件引线框架
CN203481191U (zh) 一种基于框架采用预塑封优化技术的aaqfn封装件
CN203536418U (zh) 一种双边开放式无引脚导线架框架焊铝箔用新型垫块
CN104600047A (zh) 功率模块及其封装方法
CN210984736U (zh) Igbt模块
CN204375738U (zh) 圆片级封装结构
TWI583282B (zh) 高效能封裝體及其封裝方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20140625