WO2022014300A1 - 半導体装置、および半導体装置の製造方法 - Google Patents

半導体装置、および半導体装置の製造方法 Download PDF

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Publication number
WO2022014300A1
WO2022014300A1 PCT/JP2021/024139 JP2021024139W WO2022014300A1 WO 2022014300 A1 WO2022014300 A1 WO 2022014300A1 JP 2021024139 W JP2021024139 W JP 2021024139W WO 2022014300 A1 WO2022014300 A1 WO 2022014300A1
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Prior art keywords
electrode
semiconductor device
bonding layer
bonding
conductive member
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PCT/JP2021/024139
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English (en)
French (fr)
Inventor
光俊 齊藤
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ローム株式会社
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Priority to US18/004,643 priority Critical patent/US20230245954A1/en
Priority to JP2022536221A priority patent/JPWO2022014300A1/ja
Priority to DE112021002694.1T priority patent/DE112021002694T5/de
Priority to DE212021000205.6U priority patent/DE212021000205U1/de
Priority to CN202180047781.8A priority patent/CN115769351A/zh
Publication of WO2022014300A1 publication Critical patent/WO2022014300A1/ja

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Definitions

  • the present disclosure relates to a semiconductor device including a semiconductor element such as a MOSFET and a method for manufacturing the semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor device including a MOSFET.
  • a drain terminal to which a power supply voltage is applied, a gate terminal for inputting an electric signal to the MOSFET, and a current corresponding to the power supply voltage are converted based on the electric signal, and then the converted current is used. Equipped with a flowing source terminal.
  • the MOSFET has a drain electrode conducting to the drain terminal and a source electrode conducting to the source terminal.
  • the drain electrode is electrically bonded to the die pad connected to the drain terminal by the first conductive bonding material (solder).
  • the source electrode is bonded to a conductive member (metal clip in Patent Document 1) by a second conductive bonding material (solder). Further, the conductive member is also joined to the source terminal. With such a configuration, it is possible to pass a large current through the semiconductor device.
  • Such a compound semiconductor substrate is formed of, for example, silicon carbide as a material.
  • the MOSFET can further improve the current conversion efficiency while reducing the size of the element as compared with the conventional MOSFET.
  • the drain electrode is electrically bonded to the die pad by the first conductive bonding material, and the second conductive bonding material is used. If the conductive member is electrically bonded to the source electrode in the same process, the position of the MOSFET may shift with respect to the die pad. This is due to the fact that the first conductive bonding material and the second conductive bonding material are simultaneously melted by reflow.
  • the bonding area of the conductive member with respect to the source electrode may be reduced due to the relatively small size of the MOSFET, etc., to the source terminal. Current may be hindered.
  • one object of the present disclosure is to provide a semiconductor device capable of suppressing a reduction in the bonding area of a conductive member with respect to an electrode of a semiconductor element while dealing with a large current.
  • Another subject of the present disclosure is to provide a method for manufacturing such a semiconductor device.
  • the semiconductor device provided by the first aspect of the present disclosure includes a die pad having a main surface facing the thickness direction; a first electrode provided facing the main surface, and the first electrode in the thickness direction. It has a second electrode provided on the opposite side of the electrode, and a semiconductor element in which the first electrode is electrically bonded to the main surface; the first electrode and the main surface are electrically bonded to each other. It is provided with a first bonding layer to be electrically bonded; a first conductive member electrically bonded to the second electrode; and a second bonding layer to electrically bond the first conductive member and the second electrode.
  • the melting point of the first bonding layer is higher than the melting point of the second bonding layer.
  • the method of manufacturing a semiconductor device places a conductive first bonding material on the main surface of the die pad; first and second electrodes located on opposite sides of each other.
  • the semiconductor element having the above is arranged on the first bonding material so that the first electrode faces the first bonding material; the first electrode is formed by melting and solidifying the first bonding material. Electrically bonded to the main surface; a conductive second bonding material is placed on the second electrode; a conductive member is placed on the second bonding material, and the second bonding material is placed.
  • Each step comprises electrically joining the conductive member to the second electrode by melting and solidifying.
  • the melting point of the first bonding material is higher than the melting point of the second bonding material.
  • FIG. 3 is a cross-sectional view taken along the line VII-VII of FIG.
  • FIG. 3 is a cross-sectional view taken along the line VIII-VIII of FIG.
  • FIG. 3 is a cross-sectional view taken along the line IX-IX of FIG. It is a partially enlarged view of FIG. FIG.
  • FIG. 7 is a partially enlarged view of FIG. 7.
  • FIG. 7 is another partially enlarged view of FIG. 7.
  • It is a partially enlarged sectional view of the semiconductor device which concerns on the modification of 1st Embodiment.
  • It is a top view explaining the manufacturing process of the semiconductor device shown in FIG.
  • It is a top view explaining the manufacturing process of the semiconductor device shown in FIG.
  • It is a top view explaining the manufacturing process of the semiconductor device shown in FIG.
  • FIG. is a partially enlarged sectional view explaining the manufacturing process of the semiconductor device shown in FIG. 1.
  • It is a top view explaining the manufacturing process of the semiconductor device shown in FIG.
  • It is a partially enlarged sectional view explaining the manufacturing process of the semiconductor device shown in FIG. 1.
  • FIG. 22 is a cross-sectional view taken along the line XXIII-XXIII of FIG. 22.
  • FIG. 23 is a partially enlarged view. It is another partially enlarged view of FIG. 23.
  • the semiconductor device A10 according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 13.
  • the semiconductor device A10 is used for an electronic device including a power conversion circuit (for example, a DC-DC converter).
  • the semiconductor device A10 includes a die pad 10, a first lead 11, a second lead 12, a third lead 13, a semiconductor element 20, a first bonding layer 21, a second bonding layer 22, a third bonding layer 23, and a first conductive member 31. , A wire 33 and a sealing resin 40.
  • FIG. 3 is shown by an imaginary line (dashed-dotted line) that has passed through the sealing resin 40 for convenience of understanding.
  • the thickness direction of the die pad 10 is referred to as "thickness direction z".
  • the direction orthogonal to the thickness direction z is called “first direction x”.
  • the direction orthogonal to both the thickness direction z and the first direction x is referred to as a "second direction y”.
  • the semiconductor device A10 is elongated along the first direction x, but the present disclosure is not limited thereto.
  • the die pad 10 is a conductive member on which the semiconductor element 20 is mounted.
  • the die pad 10 is composed of the same lead frame together with the first lead 11, the second lead 12, and the third lead 13.
  • the lead frame is copper (Cu) or a copper alloy. Therefore, each composition of the die pad 10, the first lead 11, the second lead 12, and the third lead 13 contains copper (that is, each member contains copper).
  • the die pad 10 has a main surface 101, a back surface 102, and a through hole 103.
  • the main surface 101 faces the thickness direction z.
  • the semiconductor element 20 is mounted on the main surface 101.
  • the back surface 102 faces the side opposite to the main surface 101 in the thickness direction z.
  • the back surface 102 is, for example, tin (Sn) plated.
  • the through hole 103 penetrates the die pad 10 from the main surface 101 to the back surface 102 in the thickness direction z.
  • the through hole 103 has a circular shape when viewed along the thickness direction z. As shown in FIG. 7, the thickness T of the die pad 10 is larger than the maximum thickness t max of the first lead 11.
  • the semiconductor element 20 is mounted on the main surface 101 of the die pad 10.
  • the semiconductor element 20 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the semiconductor element 20 is an n-channel type MOSFET having a vertical structure.
  • the semiconductor element 20 includes a compound semiconductor substrate.
  • the main material of the compound semiconductor substrate is silicon carbide (SiC).
  • gallium nitride (GaN) may be used as the main material of the compound semiconductor substrate.
  • the area of the semiconductor element 20 is 40% or less of the area of the main surface 101 of the die pad 10 when viewed along the thickness direction z.
  • the area of the semiconductor element 20 When viewed along the thickness direction z, the area of the semiconductor element 20 may be 20% or less of the area of the main surface 101, and further may be 10% or less. This ratio can be changed by appropriately changing the area of the semiconductor element 20 and the area of the main surface 101. As shown in FIGS. 10 and 11, the semiconductor device 20 has a first electrode 201, a second electrode 202, and a third electrode 203.
  • the first electrode 201 is provided so as to face the main surface 101 of the die pad 10.
  • a DC power supply voltage to be converted into power is applied to the first electrode 201.
  • the first electrode 201 corresponds to a drain electrode.
  • the second electrode 202 is provided on the side opposite to the first electrode 201 in the thickness direction z. A current converted by the semiconductor element 20 flows through the second electrode 202.
  • the second electrode 202 corresponds to the source electrode.
  • the third electrode 203 is provided on the side opposite to the first electrode 201 in the thickness direction z, and is located away from the second electrode 202.
  • a gate voltage for driving the semiconductor element 20 is applied to the third electrode 203. That is, the third electrode 203 corresponds to the gate electrode.
  • the semiconductor element 20 converts a current corresponding to the power supply voltage applied to the first electrode 201.
  • the area of the third electrode 203 is smaller than the area of the second electrode 202 when viewed along the thickness direction z.
  • the first bonding layer 21 includes a portion interposed between the main surface 101 of the die pad 10 and the first electrode 201 of the semiconductor element 20.
  • the first bonding layer 21 has conductivity.
  • the first bonding layer 21 electrically bonds the first electrode 201 and the main surface 101.
  • the first electrode 201 is electrically bonded to the main surface 101, and the first electrode 201 is electrically connected to the die pad 10.
  • the first bonding layer 21 contains tin.
  • the first bonding layer 21 is, for example, lead-free solder.
  • the melting point of the first bonding layer 21 is 290 ° C. or higher and 300 ° C. or lower.
  • the first bonding layer 21 may be lead solder.
  • the first lead 11 is located away from the die pad 10 as shown in FIGS. 3 and 7.
  • the first lead 11 extends along the first direction x.
  • the first lead 11 is conducting to the second electrode 202 of the semiconductor element 20. Therefore, the first lead 11 corresponds to the source terminal of the semiconductor device A10.
  • the first lead 11 has a covering portion 111, an exposed portion 112, and a first joint surface 113.
  • the covering portion 111 is covered with the sealing resin 40.
  • the exposed portion 112 is connected to the covering portion 111 and is exposed from the sealing resin 40.
  • the exposed portion 112 extends away from the die pad 10 in the first direction x.
  • the surface of the exposed portion 112 is, for example, tin-plated.
  • the first joint surface 113 faces the same side as the main surface 101 of the die pad 10 in the thickness direction z.
  • the first joint surface 113 is included in a part of the covering portion 111. In the thickness direction z, the first junction surface 113 is located closer to the semiconductor element 20 with respect to the main surface 101.
  • the second lead 12 is located away from both the die pad 10 and the first lead 11.
  • the second lead 12 extends along the first direction x.
  • the second lead 12 is located on the side opposite to the first lead 11 with respect to the third lead 13 in the second direction y.
  • the second lead 12 is conducting to the third electrode 203 of the semiconductor element 20. Therefore, the second lead 12 corresponds to the gate terminal of the semiconductor device A10.
  • the second lead 12 has a covering portion 121, an exposed portion 122, and a second joint surface 123.
  • the covering portion 121 is covered with the sealing resin 40.
  • the exposed portion 122 is connected to the covering portion 121 and is exposed from the sealing resin 40.
  • the exposed portion 122 extends away from the die pad 10 in the first direction x.
  • the surface of the exposed portion 122 is, for example, tin-plated.
  • the second joint surface 123 faces the same side as the main surface 101 of the die pad 10 in the thickness direction z.
  • the second joint surface 123 is included in a part of the covering portion 121.
  • the second junction surface 123 is located closer to the semiconductor element 20 with respect to the main surface 101. As shown in FIG. 9, the position of the second joint surface 123 in the thickness direction z is the same as the position of the first joint surface 113 of the first lead 11.
  • the third lead 13 includes a portion extending along the first direction x and is connected to the die pad 10.
  • the material of the third lead 13 is the same as the material of the die pad 10.
  • the third lead 13 has a covering portion 131 and an exposed portion 132.
  • the covering portion 131 is connected to the die pad 10 and is covered with the sealing resin 40.
  • the covering portion 131 is bent when viewed along the second direction y.
  • the exposed portion 132 is connected to the covering portion 131 and is exposed from the sealing resin 40.
  • the exposed portion 132 extends away from the die pad 10 in the first direction x.
  • the surface of the exposed portion 132 is, for example, tin-plated.
  • the height h of each of the exposed portion 112 of the first lead 11, the exposed portion 122 of the second lead 12, and the exposed portion 132 of the third lead 13 is the same. Is. Therefore, when viewed along the second direction y, at least a part (exposed portion 132) of the third lead 13 overlaps each of the first lead 11 and the second lead 12 (see FIG. 6).
  • the first conductive member 31 is electrically bonded to the second electrode 202 of the semiconductor element 20 and the first bonding surface 113 of the first lead 11. As a result, the first lead 11 is conducting to the second electrode 202.
  • the first conductive member 31 contains copper.
  • the first conductive member 31 is a metal clip.
  • the first conductive member 31 has a first joint portion 311 and a second joint portion 312.
  • the first joint portion 311 is a portion located at one end of the first conductive member 31 and electrically joins the first conductive member 31 to the second electrode 202.
  • the second joint portion 312 is located at the other end of the first conductive member 31, and is a portion for electrically joining the first conductive member 31 to the first joint surface 113.
  • the second bonding layer 22 includes a portion interposed between the second electrode 202 of the semiconductor element 20 and the first bonding portion 311 of the first conductive member 31.
  • the second bonding layer 22 has conductivity.
  • the second bonding layer 22 electrically bonds the first bonding portion 311 and the second electrode 202.
  • the first conductive member 31 is electrically bonded to the second electrode 202, and the first conductive member 31 is electrically connected to the second electrode 202.
  • the second bonding layer 22 contains tin.
  • the second bonding layer 22 is, for example, lead-free solder.
  • the melting point of the second bonding layer 22 is set to 260 ° C. or higher and 270 ° C. or lower.
  • the melting point of the first bonding layer 21 is higher than the melting point of the second bonding layer 22. Further, the thickness t1 of the first bonding layer 21 is larger than the thickness t2 of the second bonding layer 22.
  • the second bonding layer 22 may be lead solder.
  • the third joint layer 23 includes a portion interposed between the first joint surface 113 of the first lead 11 and the second joint portion 312 of the first conductive member 31.
  • the third bonding layer 23 has conductivity.
  • the third joint layer 23 electrically joins the second joint portion 312 and the first joint surface 113.
  • the first conductive member 31 is electrically bonded to the first bonding surface 113, and the first conductive member 31 is electrically connected to the first lead 11.
  • the third bonding layer 23 is made of the same material as the second bonding layer 22.
  • the wire 33 is electrically bonded to the third electrode 203 of the semiconductor element 20 and the second bonding surface 123 of the second lead 12. As a result, the second lead 12 is conducting to the third electrode 203.
  • the wire 33 contains gold (Au).
  • the wire 33 may have a structure containing copper or a structure containing aluminum (Al).
  • the sealing resin 40 covers the semiconductor element 20, the first conductive member 31, and the wire 33. Further, the sealing resin 40 covers a part of each of the die pad 10, the first lead 11, the second lead 12, and the third lead 13.
  • the sealing resin 40 has electrical insulation.
  • the sealing resin 40 is made of a material containing, for example, a black epoxy resin.
  • the sealing resin 40 has a top surface 41, a bottom surface 42, a pair of first side surfaces 43, a pair of second side surfaces 44, a pair of openings 45, and a mounting hole 46.
  • the top surface 41 faces the same side as the main surface 101 of the die pad 10 in the thickness direction z.
  • the bottom surface 42 faces the side opposite to the top surface 41 in the thickness direction z.
  • the back surface 102 of the die pad 10 is exposed from the bottom surface 42.
  • the pair of first side surfaces 43 are located apart from each other in the first direction x.
  • Each of the pair of first side surfaces 43 is connected to the top surface 41 and the bottom surface 42.
  • the exposed portion 112 of the first lead 11, the exposed portion 122 of the second lead 12, and the exposed portion 132 of the third lead 13. Is exposed.
  • the pair of second side surfaces 44 are located apart from each other in the second direction y. Each of the pair of second side surfaces 44 is connected to the top surface 41 and the bottom surface 42. As shown in FIGS. 2 and 6, the pair of openings 45 are located apart from each other in the second direction y. Each of the pair of openings 45 is recessed inward of the sealing resin 40 from both the top surface 41 and either of the pair of second side surfaces 44. A part of the main surface 101 of the die pad 10 is exposed from each of the pair of openings 45. As shown in FIGS. 2, 4 and 8, the mounting hole 46 penetrates the sealing resin 40 from the top surface 41 to the bottom surface 42 in the thickness direction z.
  • the mounting hole 46 is included in the through hole 103 of the die pad 10 when viewed along the thickness direction z.
  • the peripheral surface of the die pad 10 that defines the through hole 103 is covered with the sealing resin 40.
  • the maximum dimension of the mounting hole 46 is smaller than the dimension of the through hole 103 when viewed along the thickness direction z.
  • FIG. 13 shows a semiconductor device A11 which is a modification of the semiconductor device A10.
  • the semiconductor device A11 has a different configuration of the first bonding layer 21 from the semiconductor device A10. Further, the semiconductor device A11 includes a plating layer 19.
  • the first bonding layer 21 is made of a material containing sintered metal particles.
  • the sintered metal particles contain silver (Ag). Therefore, even in the semiconductor device A11, the melting point of the first bonding layer 21 is higher than the melting point of the second bonding layer 22.
  • the plating layer 19 covers the main surface 101 of the die pad 10.
  • the plating layer 19 contains silver.
  • the first bonding layer 21 includes a portion interposed between the plating layer 19 and the first electrode 201 of the semiconductor element 20.
  • FIGS. 17 and 19 are the same as the cross-sectional positions of FIG.
  • the cross-sectional position of FIG. 20 is the same as the cross-sectional position of FIG.
  • the first bonding material 81 is arranged on the main surface 101 of the die pad 10.
  • the first lead 11, the second lead 12, and the third lead 13 are connected to each other by the tie bar 80 constituting the lead frame.
  • the tie bar 80 extends along the second direction y.
  • the first bonding material 81 has conductivity.
  • the first bonding material 81 is wire solder.
  • the melting point of the first bonding material 81 is 290 ° C. or higher and 300 ° C. or lower.
  • the first bonding material 81 is temporarily attached to the main surface 101.
  • the semiconductor element 20 is arranged on the first bonding material 81.
  • the first electrode 201 of the semiconductor element 20 is made to face the first bonding material 81.
  • the first electrode 201 is temporarily attached to the first bonding material 81.
  • the first electrode 201 of the semiconductor element 20 is electrically attached to the main surface 101 of the die pad 10 by melting the first bonding material 81 by reflow and then solidifying it by cooling. Join to. In this step, the first bonding material 81 solidified by cooling becomes the first bonding layer 21.
  • the second bonding material 82 is placed on the second electrode 202 of the semiconductor element 20, and the third bonding material 83 is placed on the first bonding surface 113 of the first lead 11. Deploy.
  • Each of the second bonding material 82 and the third bonding material 83 has conductivity.
  • Each of the second bonding material 82 and the third bonding material 83 is cream solder.
  • a dispenser or the like is used for arranging each of the second joining material 82 and the third joining material 83.
  • the melting point of the second bonding material 82 is 260 ° C. or higher and 270 ° C. or lower. Therefore, the melting point of the first bonding material 81 is higher than the melting point of the second bonding material 82.
  • the third joining material 83 is made of the same material as the second joining material 82. After that, the first joint portion 311 of the first conductive member 31 is arranged on the second joint material 82. At the same time, the second joint portion 312 of the first conductive member 31 is arranged on the third joint material 83. After that, the second bonding material 82 and the third bonding material 83 are melted by reflow and then solidified by cooling to electrically bond the first bonding portion 311 to the second electrode 202. At the same time, the second joint portion 312 is electrically joined to the first joint surface 113. At this time, the reflow temperature is set to be lower than the melting point of the first bonding material 81.
  • the second bonding material 82 solidified by cooling becomes the second bonding layer 22.
  • the third bonding material 83 solidified by cooling becomes the third bonding layer 23.
  • the wire 33 is electrically bonded to the third electrode 203 of the semiconductor element 20 and the second bonding surface 123 of the second lead 12 by wire bonding.
  • the sealing resin 84 is formed.
  • the sealing resin 84 is formed by transfer molding.
  • the resin burr 841 is formed.
  • the resin burr 841 is blocked by the exposed portion 112 of the first lead 11, the exposed portion 122 of the second lead 12, the exposed portion 132 of the third lead 13, and the tie bar 80. After that, the resin burr 841 is removed with high-pressure water or the like.
  • the surface of each of the exposed portion 112 of the first lead 11, the exposed portion 122 of the second lead 12, and the exposed portion 132 of the third lead 13 and the die pad 10 are subjected to electrolytic plating using the tie bar 80 as a conductive path. Tin plating is applied to cover the back surface 102. Finally, by cutting the tie bar 80, the semiconductor device A10 is obtained.
  • the semiconductor device A10 includes a first bonding layer 21 and a second bonding layer 22.
  • the first bonding layer 21 has conductivity and electrically bonds the first electrode 201 of the semiconductor element 20 and the main surface 101 of the die pad 10.
  • the second bonding layer 22 has conductivity and electrically bonds the first conductive member 31 and the second electrode 202 of the semiconductor element 20.
  • the melting point of the first bonding layer 21 is higher than the melting point of the second bonding layer 22. Therefore, in the manufacturing process of the semiconductor device A10 shown in FIG. 19, when the second bonding material 82 to be the second bonding layer 22 is melted, the first bonding layer 21 is not melted. As a result, the position of the semiconductor element 20 with respect to the die pad 10 is prevented from being displaced.
  • the semiconductor device A10 further includes a third bonding layer 23.
  • the third bonding layer 23 has conductivity and electrically bonds the first conductive member 31 and the first bonding surface 113 of the first lead 11.
  • the third bonding layer 23 is made of the same material as the second bonding layer 22.
  • the manufacturing efficiency of the semiconductor device A10 can be improved.
  • the first conductive member 31 contains copper. As a result, the electrical resistance of the first conductive member 31 can be reduced as compared with the wire containing aluminum. This is suitable for passing a large current through the semiconductor element 20.
  • the thickness t1 of the first bonding layer 21 is larger than the thickness t2 of the second bonding layer 22. Therefore, when the semiconductor device A10 is used, the heat generated from the semiconductor element 20 can be more quickly conducted to the die pad 10.
  • the first bonding material 81 as wire solder in the manufacturing process of the semiconductor device A10, the first bonding layer 21 having a uniform thickness can be formed.
  • the first joint surface 113 of the first lead 11 is located closer to the semiconductor element 20 with respect to the main surface 101 of the die pad 10. As a result, the length of the first conductive member 31 is shortened, so that the inductance of the first conductive member 31 can be reduced.
  • the die pad 10 contains copper. Further, the thickness T of the die pad 10 is larger than the maximum thickness t max of the first lead 11. As a result, it is possible to improve the efficiency of heat conduction in the direction orthogonal to the thickness direction z while improving the heat conductivity of the die pad 10. This contributes to the improvement of heat dissipation of the die pad 10.
  • FIG. 22 is shown by an imaginary line through the sealing resin 40 for convenience of understanding.
  • the semiconductor device A20 is different from the semiconductor device A10 in that the second conductive member 32, the fourth bonding layer 24, and the fifth bonding layer 25 are provided in place of the wire 33.
  • the second conductive member 32 is electrically bonded to the third electrode 203 of the semiconductor element 20 and the second bonding surface 123 of the second lead 12. As a result, the second lead 12 is conducting to the third electrode 203.
  • the second conductive member 32 contains copper.
  • the second conductive member 32 is a metal clip.
  • the second conductive member 32 has a third joint portion 321 and a fourth joint portion 322.
  • the third joint portion 321 is located at one end of the second conductive member 32 and is a portion for electrically joining the second conductive member 32 to the third electrode 203.
  • the fourth joint portion 322 is a portion located at the other end of the second conductive member 32 and electrically joins the second conductive member 32 to the second joint surface 123.
  • the fourth bonding layer 24 includes a portion interposed between the third electrode 203 of the semiconductor element 20 and the third bonding portion 321 of the second conductive member 32.
  • the fourth bonding layer 24 has conductivity.
  • the fourth joint layer 24 electrically joins the third joint portion 321 and the third electrode 203.
  • the semiconductor device A20 the second conductive member 32 is electrically bonded to the third electrode 203, and the second conductive member 32 is electrically connected to the third electrode 203.
  • the fourth bonding layer 24 is made of the same material as the second bonding layer 22.
  • the fifth joint layer 25 includes a portion interposed between the second joint surface 123 of the second lead 12 and the fourth joint portion 322 of the second conductive member 32.
  • the fifth bonding layer 25 has conductivity.
  • the fifth joint layer 25 electrically joins the fourth joint portion 322 and the second joint surface 123.
  • the second conductive member 32 is electrically bonded to the second bonding surface 123, and the second conductive member 32 is electrically connected to the second lead 12.
  • the fifth bonding layer 25 is made of the same material as the second bonding layer 22.
  • the semiconductor device A20 includes a first bonding layer 21 and a second bonding layer 22.
  • the first bonding layer 21 has conductivity and electrically bonds the first electrode 201 of the semiconductor element 20 and the main surface 101 of the die pad 10.
  • the second bonding layer 22 has conductivity and electrically bonds the first conductive member 31 and the second electrode 202 of the semiconductor element 20.
  • the melting point of the first bonding layer 21 is higher than the melting point of the second bonding layer 22. Therefore, the semiconductor device A20 can also cope with a larger current and suppress the reduction of the bonding area of the conductive member with respect to the electrode of the semiconductor element 20.
  • the semiconductor device A20 includes a second conductive member 32 bonded to the third electrode 203 of the semiconductor element 20 and the second bonding surface 123 of the second lead 12. Further, the semiconductor device A20 includes a fourth bonding layer 24 and a fifth bonding layer 25.
  • the fourth bonding layer 24 has conductivity and electrically bonds the second conductive member 32 and the third electrode 203.
  • the fifth bonding layer 25 has conductivity and electrically bonds the second conductive member 32 and the second bonding surface 123.
  • Each of the 4th bonding layer 24 and the 5th bonding layer 25 is made of the same material as the 2nd bonding layer 22.
  • the second conductive member 32 contains copper. Further, in the thickness direction z, the second junction surface 123 of the second lead 12 is located closer to the semiconductor element 20 with respect to the main surface 101 of the die pad 10. As a result, the electric resistance of the second conductive member 32 becomes relatively low, and the length of the second conductive member 32 is shortened. Therefore, it is possible to reduce the on-resistance of the third electrode 203 of the semiconductor element 20. It will be possible.
  • the present disclosure is not limited to the above-mentioned embodiments and modifications.
  • the specific configuration of each part of the present disclosure can be freely redesigned.
  • the semiconductor devices and manufacturing methods of the present disclosure include the configurations described in the following appendices.
  • Appendix 1. A die pad with a main surface facing in the thickness direction, It has a first electrode provided so as to face the main surface and a second electrode provided on the side opposite to the first electrode in the thickness direction, and the first electrode is provided on the main surface. Electrically bonded semiconductor elements and A first bonding layer that electrically bonds the first electrode and the main surface, The first conductive member electrically bonded to the second electrode and A second bonding layer for electrically bonding the first conductive member and the second electrode is provided. A semiconductor device in which the melting point of the first bonding layer is higher than the melting point of the second bonding layer.
  • each of the die pad and the first conductive member contains copper.
  • Appendix 3. The semiconductor device according to Appendix 2, wherein the second bonding layer contains tin.
  • Appendix 4. The semiconductor device according to Appendix 3, wherein the first bonding layer contains tin.
  • Appendix 5. The semiconductor device according to Appendix 3 or 4, wherein the thickness of the first bonding layer is larger than the thickness of the second bonding layer.
  • the semiconductor device according to Appendix 3, wherein the first bonding layer is made of a material containing sintered metal particles.
  • Appendix 7. The semiconductor device according to Appendix 6, wherein the sintered metal particles contain silver.
  • the plating layer contains silver and is The semiconductor device according to Appendix 7, wherein the first bonding layer is interposed between the plating layer and the first electrode.
  • Appendix 9. The semiconductor device according to any one of Supplementary note 2 to 8, wherein the area of the semiconductor element is 40% or less of the area of the main surface when viewed along the thickness direction.
  • Appendix 10. The semiconductor device according to Appendix 9, wherein the semiconductor element includes a compound semiconductor substrate.
  • Appendix 11 A first lead having a first joint surface facing the same side as the main surface in the thickness direction and being located away from the die pad. Further, a third bonding layer for electrically bonding the first conductive member and the first bonding surface is provided.
  • the first lead contains copper and is The semiconductor device according to any one of Supplementary note 2 to 10, wherein the third bonding layer is made of the same material as the second bonding layer.
  • Appendix 12. The semiconductor device according to Appendix 11, wherein the first junction surface is located closer to the semiconductor element with respect to the main surface in the thickness direction.
  • Appendix 13. The semiconductor device according to Appendix 11 or 12, wherein the thickness of the die pad is larger than the maximum thickness of the first lead.
  • Appendix 14. It further comprises a second lead, a second conductive member, a fourth bonding layer and a fifth bonding layer.
  • the semiconductor element has a third electrode provided on the side opposite to the first electrode in the thickness direction and located away from the second electrode.
  • the second lead has a second joint surface facing the same side as the main surface in the thickness direction, and is located away from both the die pad and the first lead.
  • the second conductive member is electrically bonded to the third electrode and the second bonding surface.
  • the fourth bonding layer electrically bonds the second conductive member and the third electrode.
  • the fifth bonding layer electrically bonds the second conductive member and the second bonding surface.
  • the second conductive member and the second lead contain copper and contain copper.
  • Appendix 15 The semiconductor device according to Appendix 14, wherein the second junction surface is located closer to the semiconductor element with respect to the main surface in the thickness direction.
  • Appendix 16 It includes a portion extending along a first direction orthogonal to the thickness direction and further comprises a third lead leading to the die pad. Each of the first lead and the second lead extends along the first direction. The material of the third lead is the same as the material of the die pad. Addendum, when viewed along the thickness direction and the second direction orthogonal to the first direction, at least a part of the third lead overlaps each of the first lead and the second lead. 14.
  • Appendix 17. The semiconductor device according to any one of Supplementary note 1 to 16, further comprising a sealing resin that covers the semiconductor element, the first conductive member, and a part of the die pad.
  • the die pad has a back surface facing away from the main surface in the thickness direction.
  • a conductive first bonding material is placed on the main surface of the die pad, A semiconductor device having a first electrode and a second electrode located on opposite sides of each other is arranged on the first bonding material so that the first electrode faces the first bonding material. By melting and solidifying the first bonding material, the first electrode is electrically bonded to the main surface. A second bonding material having conductivity is placed on the second electrode, and the second bonding material is placed on the second electrode. Each step comprises placing the conductive member on the second bonding material and electrically joining the conductive member to the second electrode by melting and solidifying the second bonding material.
  • a method for manufacturing a semiconductor device wherein the melting point of the first bonding material is higher than the melting point of the second bonding material.
  • Appendix 20 The method for manufacturing a semiconductor device according to Appendix 19, wherein the first bonding material is wire solder.
  • A10, A11, A20 Semiconductor device 10: Die pad 101: Main surface 102: Back surface 103: Through hole 11: First lead 111: Covered part 112: Exposed part 113: First joint surface 12: Second lead 121: Covered part 122: Exposed part 123: Second joint surface 13: Third lead 131: Coating part 132: Exposed part 19: Plating layer 20: Semiconductor element 201: First electrode 202: Second electrode 203: Third electrode 21: First Bonding layer 22: 2nd joining layer 23: 3rd joining layer 24: 4th joining layer 25: 5th joining layer 31: 1st conductive member 311: 1st joining part 312: 2nd joining part 32: 2nd conductive member 3211: Third joint 322: Fourth joint 33: Wire 40: Sealing resin 41: Top surface 42: Bottom surface 43: First side surface 44: Second side surface 45: Opening 46: Mounting hole 80: Tie bar 81: First 1 joint material 82: 2nd joint material 83: 3rd joint material

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Abstract

半導体装置は、ダイパッドと、半導体素子と、第１接合層と、第１導電部材と、第２接合層とを備える。前記第パッドは、厚さ方向を向く主面を有する。前記半導体素子は、前記主面に対向して設けられた第１電極と、前記厚さ方向において前記第１電極とは反対側に設けられた第２電極とを有する。前記第１電極は前記主面に電気的に接合されている。前記第１接合層は、前記第１電極と前記主面とを電気的に接合する。前記第１導電部材は、前記第２電極に電気的に接合されている。前記第２接合層は、前記第１導電部材と前記第２電極とを電気的に接合する。前記第１接合層の融点は、前記第２接合層の融点よりも高い構成とされている。

Description

半導体装置、および半導体装置の製造方法
　本開示は、ＭＯＳＦＥＴなどの半導体素子を備えた半導体装置と、当該半導体装置の製造方法とに関する。
　従来、ＭＯＳＦＥＴなどの半導体素子を備えた半導体装置が広く知られている。このような半導体装置は、電力変換回路（たとえばＤＣ－ＤＣコンバータ）を備える電子機器などに使用されている。特許文献１には、ＭＯＳＦＥＴを備える半導体装置の一例が開示されている。当該半導体装置は、電源電圧が印加されるドレイン端子と、ＭＯＳＦＥＴに電気信号を入力するためのゲート端子と、電源電圧に対応した電流が当該電気信号に基づき変換された後、変換された電流が流れるソース端子とを備える。ＭＯＳＦＥＴは、ドレイン端子に導通するドレイン電極と、ソース端子に導通するソース電極とを有する。ドレイン電極は、第１導電性接合材（ハンダ）によりドレイン端子につながるダイパッドに電気的に接合されている。ソース電極は、第２導電性接合材（ハンダ）により導電部材（特許文献１では金属クリップ）に接合されている。さらに導電部材は、ソース端子にも接合されている。このような構成により、当該半導体装置に、大きな電流を流すことが可能となっている。
　近年、化合物半導体基板を有するＭＯＳＦＥＴを備えた半導体装置が普及しつつある。このような化合物半導体基板は、たとえば炭化ケイ素を材料として形成される。当該ＭＯＳＦＥＴは、従来のＭＯＳＦＥＴと比較して、素子の大きさをより小さくしつつ、電流の変換効率をより向上させることが可能である。特許文献１に開示されている半導体装置において、このような小型のＭＯＳＦＥＴを採用する場合、第１導電性接合材によりドレイン電極をダイパッドに電気的に接合させることと、第２導電性接合材により導電部材をソース電極に電気的に接合させることを同一工程で行うと、ダイパッドに対してＭＯＳＦＥＴの位置がずれることがある。これは、第１導電性接合材および第２導電性接合材をリフローにより同時に溶融させることに起因する。この場合において、ダイパッドに対するＭＯＳＦＥＴの位置ずれ量が僅かであっても、ＭＯＳＦＥＴの寸法が比較的小であることなどから、ソース電極に対する導電部材の接合面積が縮小されることがあり、ソース端子への電流が阻害されるおそれがある。
特開２０１６－１９２４５０号公報
　上記事情に鑑み、本開示は、大きな電流に対応しつつ、半導体素子の電極に対する導電部材の接合面積の縮小を抑制することが可能な半導体装置を提供することを一の課題とする。また本開示は、そのような半導体装置の製造方法を提供することを別の課題とする。
　本開示の第１の側面によって提供される半導体装置は、厚さ方向を向く主面を有するダイパッドと；前記主面に対向して設けられた第１電極と、前記厚さ方向において前記第１電極とは反対側に設けられた第２電極とを有するとともに、前記第１電極が前記主面に電気的に接合された半導体素子と；前記第１電極と前記主面とを電気的に接合する第１接合層と；前記第２電極に電気的に接合された第１導電部材と；前記第１導電部材と前記第２電極とを電気的に接合する第２接合層と、を備える。前記第１接合層の融点は、前記第２接合層の融点よりも高い構成とされている。
　本開示の第２の側面によって提供される半導体装置の製造方法は、ダイパッドの主面の上に導電性を有する第１接合材を配置し；互いに反対側に位置する第１電極および第２電極を有する半導体素子を、前記第１電極が前記第１接合材に対向するように前記第１接合材の上に配置し；前記第１接合材を溶融および固化させることにより、前記第１電極を前記主面に電気的に接合させ；導電性を有する第２接合材を前記第２電極の上に配置し；導電部材を前記第２接合材の上に配置し、かつ前記第２接合材を溶融および固化させることにより、前記導電部材を前記第２電極に電気的に接合させる、各工程を備える。前記第１接合材の融点は、前記第２接合材の融点よりも高い構成とされている。
　上記の半導体装置および製造方法によれば、より大きな電流に対応しつつ、半導体素子の電極に対する導電部材の接合面積の縮小を抑制することが可能となる。
　本開示のその他の特徴および利点は、添付図面に基づき以下に行う詳細な説明によって、より明らかとなろう。
本開示の第１実施形態にかかる半導体装置の斜視図である。 図１に示す半導体装置の平面図である。 図２に対応する平面図であり、封止樹脂を透過している。 図１に示す半導体装置の底面図である。 図１に示す半導体装置の正面図である。 図１に示す半導体装置の右側面図である。 図３のＶＩＩ－ＶＩＩ線に沿う断面図である。 図３のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。 図３のＩＸ－ＩＸ線に沿う断面図である。 図３の部分拡大図である。 図７の部分拡大図である。 図７の別の部分拡大図である。 第１実施形態の変形例にかかる半導体装置の部分拡大断面図である。 図１に示す半導体装置の製造工程を説明する平面図である。 図１に示す半導体装置の製造工程を説明する平面図である。 図１に示す半導体装置の製造工程を説明する平面図である。 図１に示す半導体装置の製造工程を説明する部分拡大断面図である。 図１に示す半導体装置の製造工程を説明する平面図である。 図１に示す半導体装置の製造工程を説明する部分拡大断面図である。 図１に示す半導体装置の製造工程を説明する部分拡大断面図である。 図１に示す半導体装置の製造工程を説明する平面図である。 本開示の第２実施形態にかかる半導体装置の平面図であり、封止樹脂を透過している。 図２２のＸＸＩＩＩ－ＸＸＩＩＩ線に沿う断面図である。 図２３の部分拡大図である。 図２３の別の部分拡大図である。
　本開示の実施形態について、添付図面に基づき、以下において説明する。
　図１～図１３に基づき、本開示の第１実施形態にかかる半導体装置Ａ１０について説明する。半導体装置Ａ１０は、電力変換回路(たとえばＤＣ－ＤＣコンバータ)を備える電子機器などに使用される。半導体装置Ａ１０は、ダイパッド１０、第１リード１１、第２リード１２、第３リード１３、半導体素子２０、第１接合層２１、第２接合層２２、第３接合層２３、第１導電部材３１、ワイヤ３３および封止樹脂４０を備える。図３は、理解の便宜上、封止樹脂４０を透過し想像線（二点鎖線）で示している。
　説明の便宜上、ダイパッド１０の厚さ方向を「厚さ方向ｚ」と呼ぶ。厚さ方向ｚに対して直交する方向を「第１方向ｘ」と呼ぶ。厚さ方向ｚおよび第１方向ｘの双方に対して直交する方向を「第２方向ｙ」と呼ぶ。図示の例では、半導体装置Ａ１０は第１方向ｘに沿って長状であるが、本開示がこれに限定されるわけではない。
　ダイパッド１０は、図３、図７および図８に示すように、半導体素子２０を搭載する導電部材である。ダイパッド１０は、第１リード１１、第２リード１２および第３リード１３とともに、同一のリードフレームから構成されている。当該リードフレームは、銅（Ｃｕ）、または銅合金である。このため、ダイパッド１０、第１リード１１、第２リード１２および第３リード１３の各々の組成は銅を含む（すなわち、各部材は銅を含有する）。図８に示すように、ダイパッド１０は、主面１０１、裏面１０２および貫通孔１０３を有する。主面１０１は、厚さ方向ｚを向く。主面１０１の上に、半導体素子２０が搭載される。裏面１０２は、厚さ方向ｚにおいて主面１０１とは反対側を向く。裏面１０２には、たとえば錫（Ｓｎ）めっきが施されている。貫通孔１０３は、厚さ方向ｚにおいて主面１０１から裏面１０２に至ってダイパッド１０を貫通している。貫通孔１０３は、厚さ方向ｚに沿って視て円形状である。図７に示すように、ダイパッド１０の厚さＴは、第１リード１１の最大厚さｔmaxよりも大である。
　半導体素子２０は、図３、図７および図８に示すように、ダイパッド１０の主面１０１の上に搭載されている。半導体素子２０は、たとえばＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）である。半導体装置Ａ１０の説明においては、半導体素子２０は、ｎチャンネル型であり、かつ縦型構造のＭＯＳＦＥＴを対象とする。半導体素子２０は、化合物半導体基板を含む。当該化合物半導体基板の主材料は、炭化ケイ素（ＳｉＣ）である。この他、当該化合物半導体基板の主材料として、窒化ガリウム（ＧａＮ）を用いてもよい。半導体装置Ａ１０においては、厚さ方向ｚに沿って視て、半導体素子２０の面積は、ダイパッド１０の主面１０１の面積の４０％以下である。厚さ方向ｚに沿って視て、半導体素子２０の面積は、主面１０１の面積の２０％以下であってもよく、さらには１０％以下であってもよい。この比率は、半導体素子２０の当該面積と、主面１０１の当該面積とを適宜変えることによって変わり得る。図１０および図１１に示すように、半導体素子２０は、第１電極２０１、第２電極２０２および第３電極２０３を有する。
　図１１に示すように、第１電極２０１は、ダイパッド１０の主面１０１に対向して設けられている。第１電極２０１には、電力変換対象となる直流の電源電圧が印加される。第１電極２０１は、ドレイン電極に相当する。
　図１０および図１１に示すように、第２電極２０２は、厚さ方向ｚにおいて第１電極２０１とは反対側に設けられている。第２電極２０２には、半導体素子２０により変換された電流が流れる。第２電極２０２は、ソース電極に相当する。
　図１０および図１１に示すように、第３電極２０３は、厚さ方向ｚにおいて第１電極２０１とは反対側に設けられ、かつ第２電極２０２から離れて位置する。第３電極２０３には、半導体素子２０が駆動するためのゲート電圧が印加される。すなわち、第３電極２０３は、ゲート電極に相当する。当該ゲート電圧に基づき、半導体素子２０は、第１電極２０１に印加された電源電圧に対応する電流を変換する。厚さ方向ｚに沿って視て、第３電極２０３の面積は、第２電極２０２の面積よりも小である。
　第１接合層２１は、図１１に示すように、ダイパッド１０の主面１０１と、半導体素子２０の第１電極２０１との間に介在する部分を含む。第１接合層２１は、導電性を有する。第１接合層２１は、第１電極２０１と主面１０１とを電気的に接合する。これにより、半導体装置Ａ１０においては、第１電極２０１が主面１０１に電気的に接合され、かつ第１電極２０１がダイパッド１０に導通する構成となっている。第１接合層２１は、錫を含有する。第１接合層２１は、たとえば鉛フリーハンダである。第１接合層２１の融点は、２９０℃以上３００℃以下とされている。第１接合層２１は、鉛ハンダでもよい。
　第１リード１１は、図３および図７に示すように、ダイパッド１０から離れて位置する。第１リード１１は、第１方向ｘに沿って延びている。第１リード１１は、半導体素子２０の第２電極２０２に導通している。このため、第１リード１１は、半導体装置Ａ１０のソース端子に相当する。第１リード１１は、被覆部１１１、露出部１１２、第１接合面１１３を有する。被覆部１１１は、封止樹脂４０に覆われている。露出部１１２は、被覆部１１１につながり、かつ封止樹脂４０から露出している。露出部１１２は、第１方向ｘにおいてダイパッド１０から遠ざかる側に延びている。露出部１１２の表面には、たとえば錫めっきが施されている。第１接合面１１３は、厚さ方向ｚにおいてダイパッド１０の主面１０１と同じ側を向く。第１接合面１１３は、被覆部１１１の一部に含まれる。厚さ方向ｚにおいて、第１接合面１１３は、主面１０１に対して半導体素子２０寄りに位置する。
　第２リード１２は、図３に示すように、ダイパッド１０および第１リード１１の双方から離れて位置する。第２リード１２は、第１方向ｘに沿って延びている。半導体装置Ａ１０においては、第２リード１２は、第２方向ｙにおいて第３リード１３に対して第１リード１１とは反対側に位置する。第２リード１２は、半導体素子２０の第３電極２０３に導通している。このため、第２リード１２は、半導体装置Ａ１０のゲート端子に相当する。第２リード１２は、被覆部１２１、露出部１２２、第２接合面１２３を有する。被覆部１２１は、封止樹脂４０に覆われている。露出部１２２は、被覆部１２１につながり、かつ封止樹脂４０から露出している。露出部１２２は、第１方向ｘにおいてダイパッド１０から遠ざかる側に延びている。露出部１２２の表面には、たとえば錫めっきが施されている。第２接合面１２３は、厚さ方向ｚにおいてダイパッド１０の主面１０１と同じ側を向く。第２接合面１２３は、被覆部１２１の一部に含まれる。厚さ方向ｚにおいて、第２接合面１２３は、主面１０１に対して半導体素子２０寄りに位置する。図９に示すように、厚さ方向ｚにおいて、第２接合面１２３の位置は、第１リード１１の第１接合面１１３の位置と同一である。
　第３リード１３は、図３および図８に示すように、第１方向ｘに沿って延びる部分を含むとともに、ダイパッド１０につながっている。第３リード１３の材料は、ダイパッド１０の材料と同一である。第３リード１３は、被覆部１３１および露出部１３２を有する。被覆部１３１は、ダイパッド１０につながり、かつ封止樹脂４０に覆われている。第２方向ｙに沿って視て、被覆部１３１は、屈曲している。露出部１３２は、被覆部１３１につながり、かつ封止樹脂４０から露出している。露出部１３２は、第１方向ｘにおいてダイパッド１０から遠ざかる側に延びている。露出部１３２の表面には、たとえば錫めっきが施されている。
　図５に示すように、半導体装置Ａ１０において、第１リード１１の露出部１１２、第２リード１２の露出部１２２、および第３リード１３の露出部１３２の各々の高さｈは、いずれも同一である。このため、第２方向ｙに沿って視て、第３リード１３の少なくとも一部（露出部１３２）が、第１リード１１および第２リード１２の各々に重なっている（図６参照）。
　第１導電部材３１は、図３および図７に示すように、半導体素子２０の第２電極２０２と、第１リード１１の第１接合面１１３とに電気的に接合されている。これにより、第１リード１１は、第２電極２０２に導通している。第１導電部材３１は、銅を含有する。半導体装置Ａ１０においては、第１導電部材３１は、金属クリップである。図１１および図１２に示すように、第１導電部材３１は、第１接合部３１１および第２接合部３１２を有する。第１接合部３１１は、第１導電部材３１の一端に位置し、かつ第１導電部材３１を第２電極２０２に電気的に接合させる部分である。第２接合部３１２は、第１導電部材３１の他端に位置し、かつ第１導電部材３１を第１接合面１１３に電気的に接合させる部分である。
　第２接合層２２は、図１１に示すように、半導体素子２０の第２電極２０２と、第１導電部材３１の第１接合部３１１との間に介在する部分を含む。第２接合層２２は、導電性を有する。第２接合層２２は、第１接合部３１１と第２電極２０２とを電気的に接合する。これにより、半導体装置Ａ１０においては、第１導電部材３１が第２電極２０２に電気的に接合され、かつ第１導電部材３１が第２電極２０２に導通する構成となっている。第２接合層２２は、錫を含有する。第２接合層２２は、たとえば鉛フリーハンダである。第２接合層２２の融点は、２６０℃以上２７０℃以下とされている。このため、第１接合層２１の融点は、第２接合層２２の融点よりも高いものとなっている。さらに、第１接合層２１の厚さｔ１は、第２接合層２２の厚さｔ２よりも大となっている。第２接合層２２は、鉛ハンダでもよい。
　第３接合層２３は、図１２に示すように、第１リード１１の第１接合面１１３と、第１導電部材３１の第２接合部３１２との間に介在する部分を含む。第３接合層２３は、導電性を有する。第３接合層２３は、第２接合部３１２と第１接合面１１３とを電気的に接合する。これにより、半導体装置Ａ１０においては、第１導電部材３１が第１接合面１１３に電気的に接合され、かつ第１導電部材３１が第１リード１１に導通する構成となっている。第３接合層２３は、第２接合層２２と同一の材料からなる。
　ワイヤ３３は、図３および図１０に示すように、半導体素子２０の第３電極２０３と、第２リード１２の第２接合面１２３とに電気的に接合されている。これにより、第２リード１２は、第３電極２０３に導通している。ワイヤ３３は、金（Ａｕ）を含有する。この他、ワイヤ３３は、銅を含有する構成や、アルミニウム（Ａｌ）を含有する構成でもよい。
　封止樹脂４０は、図３、および図７～図９に示すように、半導体素子２０、第１導電部材３１およびワイヤ３３を覆っている。また、封止樹脂４０は、ダイパッド１０、第１リード１１、第２リード１２および第３リード１３の各々の一部を覆っている。封止樹脂４０は、電気絶縁性を有する。封止樹脂４０は、たとえば黒色のエポキシ樹脂を含む材料からなる。封止樹脂４０は、頂面４１、底面４２、一対の第１側面４３、一対の第２側面４４、一対の開口４５、および取付け孔４６を有する。
　図７～図９に示すように、頂面４１は、厚さ方向ｚにおいてダイパッド１０の主面１０１と同じ側を向く。図７～図９に示すように、底面４２は、厚さ方向ｚにおいて頂面４１とは反対側を向く。図４に示すように、底面４２からダイパッド１０の裏面１０２が露出している。
　図２、図４および図６に示すように、一対の第１側面４３は、第１方向ｘにおいて互いに離れて位置する。一対の第１側面４３の各々は、頂面４１および底面４２につながっている。図５に示すように、一対の第１側面４３のうち一方の第１側面４３から、第１リード１１の露出部１１２、第２リード１２の露出部１２２、および第３リード１３の露出部１３２が露出している。
　図２、図４および図５に示すように、一対の第２側面４４は、第２方向ｙにおいて互いに離れて位置する。一対の第２側面４４の各々は、頂面４１および底面４２につながっている。図２および図６に示すように、一対の開口４５は、第２方向ｙにおいて互いに離れて位置する。一対の開口４５の各々は、頂面４１と、一対の第２側面４４のいずれかとの双方から封止樹脂４０の内方に向けて凹んでいる。一対の開口４５の各々から、ダイパッド１０の主面１０１の一部が露出している。図２、図４および図８に示すように、取付け孔４６は、厚さ方向ｚにおいて頂面４１から底面４２に至って封止樹脂４０を貫通している。厚さ方向ｚに沿って視て、取付け孔４６は、ダイパッド１０の貫通孔１０３に内包されている。貫通孔１０３を規定するダイパッド１０の周面は、封止樹脂４０に覆われている。これにより、厚さ方向ｚに沿って視て、取付け孔４６の最大寸法は、貫通孔１０３の寸法よりも小となっている。
　図１３は、半導体装置Ａ１０の変形例である半導体装置Ａ１１を示している。半導体装置Ａ１１は、第１接合層２１の構成が、半導体装置Ａ１０と異なる。また、半導体装置Ａ１１は、めっき層１９を備える。
　半導体装置Ａ１１においては、第１接合層２１は、焼結金属粒子を含む材料からなる。当該焼結金属粒子は、銀（Ａｇ）を含有する。このため、半導体装置Ａ１１においても、第１接合層２１の融点は、第２接合層２２の融点よりも高いものとなっている。
　図１９に示すように、めっき層１９は、ダイパッド１０の主面１０１を覆っている。めっき層１９は、銀を含有する。第１接合層２１は、めっき層１９と、半導体素子２０の第１電極２０１との間に介在する部分を含む。
　次に、図１４～図２１に基づき、半導体装置Ａ１０の製造方法の一例について説明する。図１７および図１９の断面位置は、図１１の断面位置と同一である。図２０の断面位置は、図１２の断面位置と同一である。
　最初に、図１４に示すように、ダイパッド１０の主面１０１の上に第１接合材８１を配置する。第１リード１１、第２リード１２および第３リード１３は、リードフレームを構成するタイバー８０により互いに連結されている。タイバー８０は、第２方向ｙに沿って延びている。第１接合材８１は、導電性を有する。第１接合材８１は、線ハンダである。第１接合材８１の融点は、２９０℃以上３００℃以下である。第１接合材８１は、主面１０１に仮付けされている。
　次いで、図１５に示すように、第１接合材８１の上に半導体素子２０を配置する。この際、半導体素子２０の第１電極２０１が第１接合材８１に対向するようにする。第１電極２０１は、第１接合材８１に仮付けされている。
　次いで、図１６および図１７に示すように、リフローにより第１接合材８１を溶融させた後、冷却により固化させることにより、半導体素子２０の第１電極２０１をダイパッド１０の主面１０１に電気的に接合させる。本工程において、冷却により固化された第１接合材８１が第１接合層２１となる。
　次いで、図１９および図２０に示すように、半導体素子２０の第２電極２０２の上に第２接合材８２と、第１リード１１の第１接合面１１３の上に第３接合材８３とを配置する。第２接合材８２および第３接合材８３の各々は、導電性を有する。第２接合材８２および第３接合材８３の各々は、クリームハンダである。第２接合材８２および第３接合材８３の各々の配置にあたっては、ディスペンサなどを用いる。第２接合材８２の融点は、２６０℃以上２７０℃以下である。このため、第１接合材８１の融点は、第２接合材８２の融点よりも高い。第３接合材８３は、第２接合材８２と同一の材料からなる。その後、第１導電部材３１の第１接合部３１１を第２接合材８２の上に配置する。あわせて、第１導電部材３１の第２接合部３１２を第３接合材８３の上に配置する。さらにその後、リフローにより第２接合材８２および第３接合材８３を溶融させた後、冷却によりこれらを固化させることにより、第１接合部３１１を第２電極２０２に電気的に接合させる。あわせて、第２接合部３１２を第１接合面１１３に電気的に接合させる。この際、リフローの温度が、第１接合材８１の融点よりも低くなるように設定する。本工程において、冷却により固化された第２接合材８２が第２接合層２２となる。また、冷却により固化された第３接合材８３が第３接合層２３となる。図１８に示すように、ワイヤボンディングによりワイヤ３３を半導体素子２０の第３電極２０３と、第２リード１２の第２接合面１２３とに電気的に接合させる。
　次いで、図２１に示すように、半導体素子２０、第１導電部材３１およびワイヤ３３を覆い、かつ、ダイパッド１０、第１リード１１、第２リード１２および第３リード１３の各々の一部を覆う封止樹脂８４を形成する。封止樹脂８４は、トランスファモールド成形により形成される。封止樹脂８４の形成に伴って、樹脂バリ８４１が形成される。樹脂バリ８４１は、第１リード１１の露出部１１２、第２リード１２の露出部１２２、第３リード１３の露出部１３２、およびタイバー８０により堰き止められる。その後、樹脂バリ８４１を高圧水などにより除去する。さらにその後、タイバー８０を導電経路とした電解めっきにより、第１リード１１の露出部１１２、第２リード１２の露出部１２２、および第３リード１３の露出部１３２の各々の表面と、ダイパッド１０の裏面１０２とを覆う錫めっきを施す。最後にタイバー８０を切断することにより、半導体装置Ａ１０が得られる。
　次に、半導体装置Ａ１０の作用効果について説明する。
　半導体装置Ａ１０は、第１接合層２１および第２接合層２２を備える。第１接合層２１は、導電性を有するとともに、半導体素子２０の第１電極２０１と、ダイパッド１０の主面１０１とを電気的に接合する。第２接合層２２は、導電性を有するとともに、第１導電部材３１と、半導体素子２０の第２電極２０２とを電気的に接合する。第１接合層２１の融点は、第２接合層２２の融点よりも高い。このため、図１９に示す半導体装置Ａ１０の製造工程において、第２接合層２２となる第２接合材８２を溶融させた際、第１接合層２１は溶融されない。これにより、ダイパッド１０に対する半導体素子２０の位置ずれが防止されるため、図１９に示す製造工程において第１導電部材３１を第２接合層２２により第２電極２０２に電気的に接合させる際、第２電極２０２に対する第１導電部材３１の接合面積をより大きく確保することができる。したがって、半導体装置Ａ１０によれば、より大きな電流に対応しつつ、半導体素子２０の電極（第２電極２０２）に対する導電部材（第１導電部材３１）の接合面積の縮小を抑制することが可能となる。
　半導体装置Ａ１０は、第３接合層２３をさらに備える。第３接合層２３は、導電性を有するとともに、第１導電部材３１と、第１リード１１の第１接合面１１３とを電気的に接合する。第３接合層２３は、第２接合層２２と同一の材料からなる。これにより、図１９および図２０に示す半導体装置Ａ１０の製造工程において、第２接合層２２となる第２接合材８２を溶融させた際、第３接合層２３となる第３接合材８３が同時に溶融される。したがって、半導体装置Ａ１０の製造において、第１導電部材３１を半導体素子２０の第２電極２０２に電気的に接合される際、第１導電部材３１を第１接合面１１３に同時に電気的に接合させることができるため、半導体装置Ａ１０の製造効率の向上が図られる。
　第１導電部材３１は、銅を含有する。これにより、アルミニウムを含有するワイヤと比較して、第１導電部材３１の電気抵抗を低減させることができる。このことは、半導体素子２０により大きな電流を流すことに好適である。
　第１接合層２１の厚さｔ１は、第２接合層２２の厚さｔ２よりも大である。これにより、半導体装置Ａ１０の使用時において、半導体素子２０から発した熱を、より速やかにダイパッド１０に伝導させることができる。半導体装置Ａ１０の製造工程において、第１接合材８１を線ハンダとすることにより、厚さが一様に確保された第１接合層２１を形成することができる。
　厚さ方向ｚにおいて、第１リード１１の第１接合面１１３は、ダイパッド１０の主面１０１に対して半導体素子２０寄りに位置する。これにより、第１導電部材３１の長さが短縮されるため、第１導電部材３１におけるインダクタンスの低減を図ることができる。
　ダイパッド１０は、銅を含有する。さらに、ダイパッド１０の厚さＴは、第１リード１１の最大厚さｔmaxよりも大である。これにより、ダイパッド１０の熱伝導率の向上を図りつつ、厚さ方向ｚに対して直交する方向の熱伝導の効率を高めることができる。このことは、ダイパッド１０の放熱性の向上に寄与する。
　図２２～図２５に基づき、本開示の第２実施形態にかかる半導体装置Ａ２０について説明する。これらの図において、先述した半導体装置Ａ１０と同一、または類似の要素には同一の符号を付して、重複する説明を省略する。図２２は、理解の便宜上、封止樹脂４０を透過し、想像線で示している。
　半導体装置Ａ２０においては、ワイヤ３３に代えて、第２導電部材３２、第４接合層２４および第５接合層２５を備えることが、半導体装置Ａ１０と異なる。
　第２導電部材３２は、図２２および図２３に示すように、半導体素子２０の第３電極２０３と、第２リード１２の第２接合面１２３とに電気的に接合されている。これにより、第２リード１２は、第３電極２０３に導通している。第２導電部材３２は、銅を含有する。半導体装置Ａ２０においては、第２導電部材３２は、金属クリップである。図２４および図２５に示すように、第２導電部材３２は、第３接合部３２１および第４接合部３２２を有する。第３接合部３２１は、第２導電部材３２の一端に位置し、かつ第２導電部材３２を第３電極２０３に電気的に接合させる部分である。第４接合部３２２は、第２導電部材３２の他端に位置し、かつ第２導電部材３２を第２接合面１２３に電気的に接合させる部分である。
　第４接合層２４は、図２４に示すように、半導体素子２０の第３電極２０３と、第２導電部材３２の第３接合部３２１との間に介在する部分を含む。第４接合層２４は、導電性を有する。第４接合層２４は、第３接合部３２１と第３電極２０３とを電気的に接合する。これにより、半導体装置Ａ２０においては、第２導電部材３２が第３電極２０３に電気的に接合され、かつ第２導電部材３２が第３電極２０３に導通する構成となっている。第４接合層２４は、第２接合層２２と同一の材料からなる。
　第５接合層２５は、図２５に示すように、第２リード１２の第２接合面１２３と、第２導電部材３２の第４接合部３２２との間に介在する部分を含む。第５接合層２５は、導電性を有する。第５接合層２５は、第４接合部３２２と第２接合面１２３とを電気的に接合する。これにより、半導体装置Ａ２０においては、第２導電部材３２が第２接合面１２３に電気的に接合され、かつ第２導電部材３２が第２リード１２に導通する構成となっている。第５接合層２５は、第２接合層２２と同一の材料からなる。
　次に、半導体装置Ａ２０の作用効果について説明する。
　半導体装置Ａ２０は、第１接合層２１および第２接合層２２を備える。第１接合層２１は、導電性を有するとともに、半導体素子２０の第１電極２０１と、ダイパッド１０の主面１０１とを電気的に接合する。第２接合層２２は、導電性を有するとともに、第１導電部材３１と、半導体素子２０の第２電極２０２とを電気的に接合する。第１接合層２１の融点は、第２接合層２２の融点よりも高い。したがって、半導体装置Ａ２０によっても、より大きな電流に対応しつつ、半導体素子２０の電極に対する導電部材の接合面積の縮小を抑制することが可能となる。
　半導体装置Ａ２０は、半導体素子２０の第３電極２０３と、第２リード１２の第２接合面１２３とに接合された第２導電部材３２を備える。さらに半導体装置Ａ２０は、第４接合層２４および第５接合層２５を備える。第４接合層２４は、導電性を有するとともに、第２導電部材３２と第３電極２０３とを電気的に接合する。第５接合層２５は、導電性を有するとともに、第２導電部材３２と第２接合面１２３とを電気的に接合する。第４接合層２４および第５接合層２５の各々は、第２接合層２２と同一の材料からなる。これにより、半導体装置Ａ２０の製造において、第２導電部材３２の接合を第１導電部材３１の接合と同時に行うことができる。さらに、第２導電部材３２の接合の際、ダイパッド１０に対する半導体素子２０の位置ずれが防止されるため、第３電極２０３に対する第２導電部材３２の接合面積が確保されたものとなる。
　第２導電部材３２は、銅を含有する。さらに、厚さ方向ｚにおいて、第２リード１２の第２接合面１２３は、ダイパッド１０の主面１０１に対して半導体素子２０寄りに位置する。これにより、第２導電部材３２の電気抵抗は比較的低いものとなり、かつ第２導電部材３２の長さが短縮されるため、半導体素子２０の第３電極２０３におけるオン抵抗の低減を図ることが可能となる。
　本開示は、先述した実施形態や変形例に限定されるものではない。本開示の各部の具体的な構成は、種々に設計変更自在である。
　本開示の半導体装置および製造方法は、以下の付記に記載された構成を含む。
　付記１．
　厚さ方向を向く主面を有するダイパッドと、
　前記主面に対向して設けられた第１電極と、前記厚さ方向において前記第１電極とは反対側に設けられた第２電極と、を有するとともに、前記第１電極が前記主面に電気的に接合された半導体素子と、
　前記第１電極と前記主面とを電気的に接合する第１接合層と、
　前記第２電極に電気的に接合された第１導電部材と、
　前記第１導電部材と前記第２電極とを電気的に接合する第２接合層と、を備え、
　前記第１接合層の融点は、前記第２接合層の融点よりも高い、半導体装置。
　付記２．
　前記ダイパッドおよび前記第１導電部材の各々は、銅を含有する、付記１に記載の半導体装置。
　付記３．
　前記第２接合層は、錫を含有する、付記２に記載の半導体装置。
　付記４．
　前記第１接合層は、錫を含有する、付記３に記載の半導体装置。
　付記５．
　前記第１接合層の厚さは、前記第２接合層の厚さよりも大である、付記３または４に記載の半導体装置。
　付記６．
　前記第１接合層は、焼結金属粒子を含む材料からなる、付記３に記載の半導体装置。
　付記７．
　前記焼結金属粒子は、銀を含有する、付記６に記載の半導体装置。
　付記８．
　前記主面を覆うめっき層をさらに備え、
　前記めっき層は、銀を含有し、
　前記第１接合層は、前記めっき層と前記第１電極との間に介在している、付記７に記載の半導体装置。
　付記９．
　前記厚さ方向に沿って視て、前記半導体素子の面積は、前記主面の面積の４０％以下である、付記２ないし８のいずれかに記載の半導体装置。
　付記１０．
　前記半導体素子は、化合物半導体基板を含む、付記９に記載の半導体装置。
　付記１１．
　前記厚さ方向において前記主面と同じ側を向く第１接合面を有するとともに、前記ダイパッドから離れて位置する第１リードと、
　前記第１導電部材と前記第１接合面とを電気的に接合する第３接合層と、をさらに備え、
　前記第１リードは、銅を含有し、
　前記第３接合層は、前記第２接合層と同一の材料からなる、付記２ないし１０のいずれかに記載の半導体装置。
　付記１２．
　前記厚さ方向において、前記第１接合面は、前記主面に対して前記半導体素子寄りに位置する、付記１１に記載の半導体装置。
　付記１３．
　前記ダイパッドの厚さは、前記第１リードの最大厚さよりも大である、付記１１または１２に記載の半導体装置。
　付記１４．
　第２リード、第２導電部材、第４接合層および第５接合層をさらに備えており、
　前記半導体素子は、前記厚さ方向において前記第１電極とは反対側に設けられ、かつ前記第２電極から離れて位置する第３電極を有し、
　前記第２リードは、前記厚さ方向において前記主面と同じ側を向く第２接合面を有するとともに、前記ダイパッドおよび前記第１リードの双方から離れて位置しており、
　前記第２導電部材は、前記第３電極および前記第２接合面に電気的に接合されており、
　前記第４接合層は、前記第２導電部材と前記第３電極とを電気的に接合しており、
　前記第５接合層は、前記第２導電部材と前記第２接合面とを電気的に接合しており、
　前記第２導電部材および前記第２リードは、銅を含有し、
　前記第４接合層および前記第５接合層の各々は、前記第２接合層と同一の材料からなる、付記１１ないし１３のいずれかに記載の半導体装置。
　付記１５．
　前記厚さ方向において、前記第２接合面は、前記主面に対して前記半導体素子寄りに位置する、付記１４に記載の半導体装置。
　付記１６．
　前記厚さ方向に対して直交する第１方向に沿って延びる部分を含むとともに、前記ダイパッドにつながる第３リードをさらに備え、
　前記第１リードおよび前記第２リードの各々は、前記第１方向に沿って延び、
　前記第３リードの材料は、前記ダイパッドの材料と同一であり、
　前記厚さ方向および前記第１方向に対して直交する第２方向に沿って視て、前記第３リードの少なくとも一部が、前記第１リードおよび前記第２リードの各々に重なっている、付記１４または１５に記載の半導体装置。
　付記１７．
　前記半導体素子および前記第１導電部材と、前記ダイパッドの一部と、を覆う封止樹脂をさらに備える、付記１ないし１６のいずれかに記載の半導体装置。
　付記１８．
　前記ダイパッドは、前記厚さ方向において前記主面とは反対側を向く裏面を有し、
　前記封止樹脂から前記裏面が露出している、付記１７に記載の半導体装置。
　付記１９．
　ダイパッドの主面の上に導電性を有する第１接合材を配置し、
　互いに反対側に位置する第１電極および第２電極を有する半導体素子を、前記第１電極が前記第１接合材に対向するように前記第１接合材の上に配置し、
　前記第１接合材を溶融および固化させることにより、前記第１電極を前記主面に電気的に接合させ、
　導電性を有する第２接合材を前記第２電極の上に配置し、
　導電部材を前記第２接合材の上に配置し、かつ前記第２接合材を溶融および固化させることにより、前記導電部材を前記第２電極に電気的に接合させる、各工程を備え、
　前記第１接合材の融点は、前記第２接合材の融点よりも高い構成とされている、半導体装置の製造方法。
　付記２０．
　前記第１接合材は、線ハンダである、付記１９に記載の半導体装置の製造方法。
Ａ１０，Ａ１１，Ａ２０：半導体装置　　　１０：ダイパッド
１０１：主面　　　１０２：裏面　　　１０３：貫通孔
１１：第１リード　　　１１１：被覆部　　　１１２：露出部
１１３：第１接合面　　　１２：第２リード　　　１２１：被覆部
１２２：露出部　　　１２３：第２接合面　　　１３：第３リード
１３１：被覆部　　　１３２：露出部　　　１９：めっき層
２０：半導体素子　　　２０１：第１電極　　　２０２：第２電極
２０３：第３電極　　　２１：第１接合層　　　２２：第２接合層
２３：第３接合層　　　２４：第４接合層　　　２５：第５接合層
３１：第１導電部材　　　３１１：第１接合部　　　３１２：第２接合部
３２：第２導電部材　　　３２１：第３接合部　　　３２２：第４接合部
３３：ワイヤ　　　４０：封止樹脂　　　４１：頂面
４２：底面　　　４３：第１側面　　　４４：第２側面
４５：開口　　　４６：取付け孔　　　８０：タイバー
８１：第１接合材　　　８２：第２接合材　　　８３：第３接合材
ｚ：厚さ方向　　　ｘ：第１方向　　　ｙ：第２方向

Claims (15)

  1. 　厚さ方向を向く主面を有するダイパッドと、
    　前記主面に対向して設けられた第１電極と、前記厚さ方向において前記第１電極とは反対側に設けられた第２電極と、を有するとともに、前記第１電極が前記主面に電気的に接合された半導体素子と、
    　前記第１電極と前記主面とを電気的に接合する第１接合層と、
    　前記第２電極に電気的に接合された第１導電部材と、
    　前記第１導電部材と前記第２電極とを電気的に接合する第２接合層と、を備え、
    　前記第１接合層の融点は、前記第２接合層の融点よりも高い、半導体装置。
  2. 　前記ダイパッドおよび前記第１導電部材の各々は、銅を含有する、請求項１に記載の半導体装置。
  3. 　前記第２接合層は、錫を含有する、請求項２に記載の半導体装置。
  4. 　前記第１接合層は、錫を含有する、請求項３に記載の半導体装置。
  5. 　前記第１接合層の厚さは、前記第２接合層の厚さよりも大である、請求項３または４に記載の半導体装置。
  6. 　前記厚さ方向に沿って視て、前記半導体素子の面積は、前記主面の面積の４０％以下である、請求項２ないし５のいずれかに記載の半導体装置。
  7. 　前記厚さ方向において前記主面と同じ側を向く第１接合面を有するとともに、前記ダイパッドから離れて位置する第１リードと、
    　前記第１導電部材と前記第１接合面とを電気的に接合する第３接合層と、をさらに備え、
    　前記第１リードは、銅を含有し、
    　前記第３接合層は、前記第２接合層と同一の材料からなる、請求項２ないし６のいずれかに記載の半導体装置。
  8. 　前記厚さ方向において、前記第１接合面は、前記主面に対して前記半導体素子寄りに位置する、請求項７に記載の半導体装置。
  9. 　前記ダイパッドの厚さは、前記第１リードの最大厚さよりも大である、請求項７または８に記載の半導体装置。
  10. 　第２リード、第２導電部材、第４接合層および第５接合層をさらに備え、
    　前記半導体素子は、前記厚さ方向において前記第１電極とは反対側に設けられ、かつ前記第２電極から離れて位置する第３電極を有し、
    　前記第２リードは、前記厚さ方向において前記主面と同じ側を向く第２接合面を有するとともに、前記ダイパッドおよび前記第１リードから離れて位置しており、
    　前記第２導電部材は、前記第３電極および前記第２接合面に電気的に接合されており、
    　前記第４接合層は、前記第２導電部材と前記第３電極とを電気的に接合しており、
    　前記第５接合層は、前記第２導電部材と前記第２接合面とを電気的に接合しており、
    　前記第２導電部材および前記第２リードは、銅を含有し、
    　前記第４接合層および前記第５接合層の各々は、前記第２接合層と同一の材料からなる、請求項７ないし９のいずれかに記載の半導体装置。
  11. 　前記厚さ方向において、前記第２接合面は、前記主面に対して前記半導体素子寄りに位置する、請求項１０に記載の半導体装置。
  12. 　前記半導体素子および前記第１導電部材と、前記ダイパッドの一部と、を覆う封止樹脂をさらに備える、請求項１ないし１１のいずれかに記載の半導体装置。
  13. 　前記ダイパッドは、前記厚さ方向において前記主面とは反対側を向く裏面を有し、
    　前記封止樹脂から前記裏面が露出している、請求項１２に記載の半導体装置。
  14. 　ダイパッドの主面の上に導電性を有する第１接合材を配置し、
    　互いに反対側に位置する第１電極および第２電極を有する半導体素子を、前記第１電極が前記第１接合材に対向するように前記第１接合材の上に配置し、
    　前記第１接合材を溶融および固化させることにより、前記第１電極を前記主面に電気的に接合させ、
    　導電性を有する第２接合材を前記第２電極の上に配置し、
    　導電部材を前記第２接合材の上に配置し、かつ前記第２接合材を溶融および固化させることにより、前記導電部材を前記第２電極に電気的に接合させる、各工程を備え、
    　前記第１接合材の融点は、前記第２接合材の融点よりも高い構成とされている、半導体装置の製造方法。
  15. 　前記第１接合材は、線ハンダである、請求項１４に記載の半導体装置の製造方法。
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