CN1316581C - 用于改良晶片可靠性的密封针脚结构 - Google Patents
用于改良晶片可靠性的密封针脚结构 Download PDFInfo
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Abstract
一种焊料凸块,用于将电子器件键合到衬底或另一结构上,如下形成:在支撑结构上电镀高纵横比的铜针脚,将针脚密封在阻挡材料中,在阻挡材料上电镀焊料,然后回流焊料。
Description
技术领域
本发明的领域为集成电路封装,尤其是倒装片技术。
背景技术
印刷电路板(也称作印刷布线板)——下文简称作“PCB”——已经无处不在。PCB通常是一面或两面包覆导体(例如铜)的介电衬底(例如纤维增强的有机树脂)的形式。介电衬底具有预定图形的孔眼,用于与布线和电器件相连,其中导体被构图以给出孔眼之间的预定电路线,从而布线和电器件在功能上互连。
在1960年代,IBM公司开发了一种交错技术来硬连线所有界面,一般称作“受控折叠芯片连接”或简称为“C4”。根据这一技术,芯片通过芯片上的凸块和PCB上的界面焊垫之间的匹配接触而连接到PCB的电子器件上。具有一系列凸块用于C4的芯片称作“倒装片”。凸块通常为焊料合金(例如97%铅,3%锡),由凸块掩模沉积在可沾湿的凸块焊垫上,PCB上的界面焊垫也是可沾湿的,从而通过凸块的回流同时形成了电学和机械互连。这一技术的优点包括用于芯片-衬底偏移——发生在芯片放置期间——以及使凸块吸收应力的回流补偿。
使用随后要除去的凸块掩模将凸块沉积在凸块焊垫上。在这一步,凸块就像截角圆锥,在凸块焊垫处最宽。之后,对凸块进行无氧化回流处理,随后凸块变成凸圆形,就像截去顶端的鸡蛋形状。
虽然如上所述那样C4技术可用于在芯片上给出凸块,但是要注意的是C4技术同样也可以很好地用于在PCB上给出凸块,其中芯片具有界面焊垫。此外,C4技术还可用于连接除了芯片之外的其它电子结构,例如将小PCB连接到更大的PCB上,等等。
随着尺寸的收缩,需要减小间距并在给定面积中封装更多触点。这反过来又减小了C4凸块之间所容许的间隔并增大了相邻凸块之间短路的机会。已进行了各种尝试以增大触点密度。
US2002-0179689 A1:用于半导体芯片的柱形连接及制造方法(Pillar Connections for Semiconductor Chips and Method ofManufacture)(发明者:F.Tung)示出被低共熔焊料覆盖的铜柱。该结构由顺序电镀的冶金(metallurgy)堆叠形成。铜针脚暴露向焊料并与之接触,从而使得会形成不必要的Cu-Sn金属间化合物。
US 5,773,889:用于将集成电路与衬底相连的线互连结构(WireInterconnect Structures for Connecting an Integrated Circuit to aSubstrate)(发明者D.Love等)示出部分覆盖有镍壳的针状铜结构的制作。器件由针脚结构的两个底部处的焊料片连接到衬底上。这一结构复杂,需要使用三个掩模。
发明内容
本发明提供一种在电结构上形成电连接部件的方法,包含下列步骤:给出具有一组触点的电结构;形成至少一个界面层,附着在所述触点组上;构图所述界面层以形成置于所述触点组之上的一组焊垫;沉积并光刻构图一层光刻胶,它在所述焊垫组之上具有一组小孔;形成一组导电针脚,直接附着在所述焊垫上;去除所述光刻胶层;形成阻挡层,附着在所述针脚组的所有暴露表面上;形成一层焊料,环绕阻挡层;以及回流焊料层。
本发明提供一种电结构,含有适用于将其与另一电结构相连的电连接部分,包含:在电结构中的第一组触点;至少一个界面层,附着在所述触点组上;一组焊垫,置于所述触点组之上,包括所述界面层;一组导电针脚,直接附着在所述焊垫上;阻挡层,附着在所述针脚组的所有暴露表面上;一层焊料,环绕该阻挡层。
本发明涉及制作用于倒装片键合的小间距导电焊垫(也称作凸块)的方法。
本发明的特征在于直接电镀在种子层上的支撑针脚。
本发明的另一特征在于在一层光刻胶中由光刻而确定的小孔中电镀针脚。
本发明的另一特征在于相对焊料的种子堆叠选择腐蚀,除去种子堆叠而不触及到焊料。
附图说明
图1示出具有未构图层的集成电路的顶部区域。
图2示出构图一层光刻胶之后的同一区域。
图3示出腐蚀穿种子层的结果。
图4示出剥去光刻胶之后的结构。
图5示出电镀铜针脚的结果。
图6示出在铜上电镀阻挡金属的结果。
图7示出在回流之前电镀一层焊料的结果。
图8示出腐蚀附着层的结果。
图9示出回流焊料的结果。
图10示出替代实施方案中的步骤。
具体实施方式
图1示出具有未构图层的集成电路的顶部区域。在底部,框200表示电子结构,例如要由要形成的触点来附加的集成电路。层30为介电层,例如密封该结构以使互连绝缘并阻挡水分和其它不受欢迎的化学物质的渗透的聚酰亚胺。
框35示意性表示从未示出的互连穿过聚酰亚胺向上延伸的通孔。结构顶部上的触点将与这些通孔接触。
层20为阻挡和/或附着冶金层(metallurgy layer)。例如,使用本领域技术人员所知的TiW、Ti、TaN和其它材料来阻挡触点材料——例如铜——的渗透和/或提高触点材料和互连材料(通常为铝合金)之间的附着性。
层10为种子层,促进用于要形成的针脚的材料的沉积和电镀。随着触点变得更小,触点材料的电流容量变得更重要,从而铜是优选的材料。
图2示出构图一层光刻胶40之后的同一区域。光刻胶40用传统方法沉积并进行构图以确定触点35之上的焊垫区域。
图3示出使用不腐蚀下层阻挡层20的腐蚀剂腐蚀穿种子层的结果。示例性地,利用Pourbaix表所设定的合适电流和电解液的电腐蚀适用于这一步骤。
图4示出剥去光刻胶之后的结构,留下将用作以后结构的基底的焊垫12。焊垫12与触点35电接触,将能量和信号传入包含在框200中的器件中。
图5示出一系列步骤的结果,其中一厚层光刻胶70——例如厚至100微米——被涂上并构图从而光刻胶在要形成针脚的区域之外聚合并在传统显影步骤中溶解。随后形成的小孔具有针脚60的尺寸。通常,针脚的直径由括弧62指出,大约为25微米。小孔在光刻胶中的厚度由括弧72指出。小孔的纵横比优选地在三至一的范围。针脚60通过在小孔中电镀铜而形成,使用连接在触点35上的互连结构作为电流路径来形成针脚60。
有利地,针脚60中的铜直接键合到种子层10中的铜上。在现有技术的结构中,针脚由焊料片连接,其缺点在于铜和焊料之间的直接接触。
图6示出在铜上电镀阻挡金属的结果。示例性地,阻挡金属为镍,它有效地限制了铜并防止铜与焊料成分——例如锡——反应形成不需要的化合物。电镀过程天然能够在所有暴露表面——焊垫12的垂直边、焊垫的顶部以及铜针脚60的顶部和侧面——上形成阻挡层。
图7示出回流之前电镀一层焊料的结果。焊料90示出在镍阻挡层上延伸并向下直到附着层20。有利地,选择焊料的组分以使其优先电镀到阻挡层上而不是附着层的材料上,从而焊料不附着在层20上。这具有有益的结果,那就是相邻焊料结构之间的完全分离。如果焊料良好地附着在层20上,那么将会在层20的整个表面上形成覆盖,必须除去以防止使触点短路。
图8示出腐蚀附着层20的结果。示例性地,腐蚀剂不会对焊料有任何明显的腐蚀,但是会腐蚀并除去相对较薄《一般小于5000埃)的层20。在图中可以看出腐蚀过程有些过腐蚀,下切焊料90并到达阻挡层。
图9示出在传统烘箱中回流焊料的结果。焊料的表面张力使结构形成适于C4工艺的光滑曲面。箭头82示出阻挡层最近部分之间典型的——但并非唯一的——容许距离,为50微米;箭头94示出焊料90的最接近处的相应容差,为50微米。顶部的箭头95示出设计间距,示例性的100微米,这规定了要获得容差82和94各层的厚度。
随着尺寸的收缩,各层的厚度也要因此而调整。
图10示出替代实施方案中的步骤,其中电镀润湿层85——示出为例如0.5微米的Cu或Au——来改善镍阻挡层和焊料之间的附着性。由于置于镍之下的铜相对较厚并且镍之上的铜用于减小阻挡层中的化学势梯度,因而在这一实施方案中外铜层可看作牺牲层。
在形成阻挡层的步骤之后和沉积焊料的步骤之前将电镀或沉积层85。
下面总结了工艺步骤的顺序。
工艺顺序
1.起始结构:在绝缘体(聚酰亚胺)中的小孔下具有终端的集成电路;种子金属堆叠。
2.构图光刻胶以确定针脚基底。
3.腐蚀种子层,留下焊垫。
4.为针脚构图厚光刻胶。
5.在小孔中电镀针脚。
6.剥去光刻胶。
7.在针脚和焊垫上电镀阻挡材料。
8.对于焊料选择性电镀阻挡层。
9.腐蚀相对于焊料和阻挡层选择性的种子堆叠。
10.回流焊料。
本领域技术人员将能容易地将前述实施例修改用于其它环境。例如,这里使用的术语形成、沉积和电镀并非排它性的,而是要包括能获得相同或类似结果的替代方法,例如溅射、化学气相沉积等。
虽然以单个优选实施方案的形式描述了本发明,但是本领域技术人员将会承认,只要处于下述权利要求的精神和范围之内,本发明能用于各种形式中。
Claims (20)
1.在电结构上形成电连接部件的方法,包含下列步骤:
给出具有一组触点的电结构;
形成至少一个界面层,附着在所述触点组上;
构图所述界面层以形成置于所述触点组之上的一组焊垫;
沉积并光刻构图一层光刻胶,它在所述焊垫组之上具有一组小孔;
形成一组导电针脚,直接附着在所述焊垫上;
去除所述光刻胶层;
形成阻挡层,附着在所述针脚组的所有暴露表面上;
形成一层焊料,环绕阻挡层;以及
回流焊料层。
2.根据权利要求1的方法,其中阻挡层的材料阻挡来自针脚的材料通过,从而防止所述来自针脚的材料与焊料成分反应。
3.根据权利要求1的方法,其中界面层包含一层附着材料和一种子层。
4.根据权利要求2的方法,其中界面层包含一层附着材料和一种子层。
5.根据权利要求1的方法,其中界面层包括选自下列的材料:TiW、Ti、Ta、Cr和TaN。
6.根据权利要求2的方法,其中界面层包括选自下列的材料:TiW、Ti、Ta、Cr和TaN。
7.根据权利要求3的方法,其中界面层包括选自下列的材料:TiW、Ti、Ta、Cr和TaN。
8.根据权利要求4的方法,其中界面层包括选自下列的材料:TiW、Ti、Ta、Cr和TaN。
9.根据权利要求1的方法,其中通过将材料电镀进光刻胶中的小孔中而形成针脚。
10.根据权利要求1的方法,其中在形成一层焊料的步骤之前利用湿润层电镀针脚。
11.根据权利要求10的方法,其中阻挡层的材料阻挡来自针脚的材料通过,从而防止所述来自针脚的材料与焊料成分反应。
12.根据权利要求10的方法,其中界面层包含一层附着材料和一种子层。
13.根据权利要求11的方法,其中界面层包含一层附着材料和一种子层。
14.电结构,含有适用于将其与另一电结构相连的电连接部分,包含:
在电结构中的第一组触点;
至少一个界面层,附着在所述触点组上;
一组焊垫,置于所述触点组之上,包括所述界面层;
一组导电针脚,直接附着在所述焊垫上;
阻挡层,附着在所述针脚组的所有暴露表面上;
一层焊料,环绕该阻挡层。
15.根据权利要求14的结构,其中阻挡层的材料阻挡来自针脚的材料通过,从而防止来自所述针脚的材料与焊料成分反应。
16根据权利要求14的结构,其中界面层包含一层附着材料和一种子层。
17.根据权利要求15的结构,其中界面层包含一层附着材料和一种子层。
18.根据权利要求14的结构,其中界面层包括选自下列的材料:TiW、Ti、Ta、Cr和TaN。
19.根据权利要求15的结构,其中界面层包括选自下列的材料:TiW、Ti、Ta、Cr和TaN。
20.根据权利要求14的结构,其中从Cu和Au组成的组中选择的湿润层形成在阻挡层上。
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US7820543B2 (en) * | 2007-05-29 | 2010-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced copper posts for wafer level chip scale packaging |
US8492263B2 (en) * | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
US20100032194A1 (en) * | 2008-08-08 | 2010-02-11 | Ibiden Co., Ltd. | Printed wiring board, manufacturing method for printed wiring board and electronic device |
US8299616B2 (en) * | 2010-01-29 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | T-shaped post for semiconductor devices |
US8803319B2 (en) | 2010-02-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8318596B2 (en) | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8241963B2 (en) | 2010-07-13 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed pillar structure |
US9230932B2 (en) | 2012-02-09 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect crack arrestor structure and methods |
US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
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