CN1096110C - 含有钛阻挡层的焊料凸点结构及其形成方法 - Google Patents

含有钛阻挡层的焊料凸点结构及其形成方法 Download PDF

Info

Publication number
CN1096110C
CN1096110C CN96193314A CN96193314A CN1096110C CN 1096110 C CN1096110 C CN 1096110C CN 96193314 A CN96193314 A CN 96193314A CN 96193314 A CN96193314 A CN 96193314A CN 1096110 C CN1096110 C CN 1096110C
Authority
CN
China
Prior art keywords
layer
salient point
point metal
solder bump
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96193314A
Other languages
English (en)
Other versions
CN1181841A (zh
Inventor
约瑟夫·丹尼尔·米斯
格雷钦·马耶尔克·阿德马
马克·D·克拉姆
W·鲍伊德·罗格尔斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unitive Internat Ltd.
Original Assignee
UNITIVE INTERNAT Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UNITIVE INTERNAT Ltd filed Critical UNITIVE INTERNAT Ltd
Publication of CN1181841A publication Critical patent/CN1181841A/zh
Application granted granted Critical
Publication of CN1096110C publication Critical patent/CN1096110C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Vehicle Interior And Exterior Ornaments, Soundproofing, And Insulation (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

一种在具有接触焊盘的微电子器件上形成焊料凸点的方法，包括以下步骤：在器件上淀积钛阻挡层，在钛阻挡层上形成下凸点金属化层，和在下凸点金属化层上形成一个或多个焊料凸点。焊料凸点限定了被除去的下凸点金属化层暴露的部分，然后钛阻挡层的暴露的部分被除去。钛阻挡层保护下面的微电子器件不受除去下凸点金属化层的腐蚀剂的影响。钛阻挡层也可以防止下凸点金属化层在下面的微电子器件上形成残留物。因此，钛阻挡层使得下凸点金属化层很快被除去，而不会留下残留物，因而减小了焊料凸点间电短路的可能性。

Description

含有钛阻挡层的焊料凸点结构及其形成方法
本发明涉及微电子器件的制造方法和结构，特别涉及形成微电子器件的电气和机械连接的方法，以及由此方法形成的连接。
高性能的微电子器件通常使用焊料球或焊料凸点与其它微电子器件进行电互连。例如，超大规模集成电路(VLSI)芯片可以使用焊料球或焊料凸点电连接到电路板或其它下一级封装衬底上。这种连接技术也称作“控制熔塌芯片连接-C4”或“倒装芯片”技术，在这里称作焊料凸点。
在IBM开发的最初的焊料凸点技术中，焊料凸点通过夹到集成电路硅片上的阴模中的开口由蒸发形成。例如，Katz等人的U.S.专利5,234,149“Debondable Metallic Bonding Method”公开了一种带芯片接线端和金属化层的电子器件。接线端一般为铝，金属化层包括钛或铬局部粘附层，共淀积的局部铬铜层，局部可湿润铜层，和局部金和锡帽盖层。蒸发的局部铅-锡焊料层位于帽盖层上。
以电镀法为基础的焊料凸点技术也被积极地开发。电镀法对较大衬底和较小焊料凸点特别有用。在该方法中，一般通过蒸发或溅射将“下凸点金属化(under bump metallurgy)”(UBM)层淀积在具有接触焊盘的微电子衬底上。连续下凸点金属化层一般在焊盘和焊盘间的衬底上，以便焊料电镀期间允许电流通过。
带下凸点金属化层的电镀法的例子公开于Yung的U.S.专利5,162,257“焊料凸点制造方法”中，并转让给本申请的受让人。在该专利中，下凸点金属化层包含紧邻衬底和焊盘的铬层，作为可焊金属的帽盖铜层，以及铬层和铜层之间的相控的铬/铜层。焊料凸点的基层通过将焊料凸点和焊盘间的下凸点金属化层转换为下凸点金属化层的焊料和可焊组分构成的中间金属来保持。然而需要多个腐蚀周期除去相控的铬/铜层和底部的铬层。即使进行多个腐蚀周期，也很难完全除去下凸点金属化层，并可能使焊料凸点间电短路。
尽管已有以上提到的专利，但本领域仍然需要一种形成焊料凸点的方法和因此形成的焊料凸点的结构，其中在电镀焊料凸点之后，可以很容易并完全地除去下凸点金属化层的暴露部分，因而减少焊料凸点间电短路的可能性。本领域也需要一种形成焊料凸点的方法，其中当除去下凸点金属化层的暴露部分时，不必大量地钻蚀(Undercut)焊料凸点，因而减少了发生机械或电气故障的可能性。
因此本发明的目的在于提供一种改进的制造微电子器件接触焊盘的焊料凸点的方法，以及因此形成的改进的焊料凸点。
本发明的另一目的在于减少电镀焊料凸点后除去下凸点金属化层的暴露部分所需的时间。
本发明的再一目的在于减少焊料凸点间电短路。
本发明的又一目的在于减少电镀后除去下凸点金属化层的暴露部分时焊料凸点的钻蚀。
本发明的这些和其它目的通过形成下凸点金属化层之前在微电子器件上淀积连续的钛阻挡层实现。因此，下凸点金属化层可以从钛层上被选择性地除去，然后将钛层从微电子器件上除去。钛层可防止下凸点金属化层在微电子器件上形成残留物造成焊料凸点间电短路。此外，钛层可保护下面的微电子器件不受除去下凸点金属化层的腐蚀剂的影响。
根椐本发明的一个方面，形成焊料凸点的方法包括以下步骤：在带有焊盘的微电子器件上淀积钛阻挡层，在钛阻挡层上形成下凸点金属化层，然后在下凸点金属化层上形成焊料凸点。焊料凸点限定出将选择性地除去的下凸点金属化层和钛阻挡层的暴露部分。因此，电镀焊料凸点后，下凸点金属化层的暴露部分可以很快并完全地除去，而不必大量钻蚀焊料凸点或留下导致焊料凸点间电短路的残留物。
可以使用相对于焊料凸点和钛阻挡层优先腐蚀下凸点金属化层的腐蚀剂选择性地除去下凸点金属化层的暴露部分。可以使用相对于焊料凸点和留在焊料凸点下的那部分下凸点金属化层的优先腐蚀钛阻挡层的腐蚀剂选择性地除去钛阻挡层。
下凸点金属化层最好包括钛阻挡层上的铬层，铬层上的铬层和铜层的相控层，以及相控层上的铜层。在这个实施例中，氢氧化铵和过氧化氢的混合物可以用于选择性地腐蚀下凸点金属化层的铜部分；盐酸可以用于腐蚀下凸点金属化层的铬部分；以及用氟化铵缓冲的氢氟酸选择性地腐蚀钛层。
也可以在下凸点金属化层未被焊料凸点覆盖的区域上形成焊料阻挡层(dam)，最好在除去下凸点金属化层的暴露部分之前除去该焊料阻挡层。焊料阻挡层最好包括如铬或钛层等焊料不可湿润层。焊料阻挡层也可以包括焊料不可湿润层上的如铜等的焊料可湿润材料。
形成后，可以对焊料凸点进行回流焊。回流焊焊料凸点的步骤使焊料凸点和紧邻焊料凸点的下凸点金属化层的未暴露部分之间发生反应，从而产生金属间区域，其中除去下凸点金属化层的铜部分的腐蚀剂相对于金属间区域优先腐蚀铜。
图1-6为根据本发明形成焊料凸点的第一个方法的不同步骤期间，带焊盘的微电子器件的剖面图。
图7-12为根据本发明形成焊料凸点的第二个方法的不同步骤期间，带焊盘的微电子器件的剖面图。
下面结合附图更详细地介绍本发明，其中显示了本发明的优选实施例。然而，本发明可以体现为许多不同形式，不应仅局限在以下介绍的实施例中；而且，提供这些实施例是为了公开充分，使本领域的普通技术人员完全明确本发明的范围。为清楚起见，层的厚度进行了夸大。同样的元件采用了相同的数字。
如图1所示，微电子器件20包括衬底22，多个接触焊盘24，以及钝化层26。衬底22可以包括一层半导体材料，该半导体材料可以为硅、砷化镓、碳化硅、金刚石、印刷电路板或多层衬底、或本领域的普通技术人员公知的其它衬底材料。接触焊盘24可以包括铝、铜、钛、以上提到的金属的结合如AlCu和AlTi3的中间金属、或本领域的普通技术人员公知的其它材料。钝化层26最好为聚酰亚胺层，但也可以是二氧化硅层、氮化硅层、或本领域的普通技术人员公知的其它钝化材料。如图所示，钝化层最好覆盖与衬底相对的每个接触焊盘的上部边缘部分，暴露每个接触焊盘的中间的表面部分。
在微电子器件20上需要有焊料凸点以便器件可以电气地和机械地连接到如电路板等的另一个微电子器件或其它下一级封装衬底上。接触焊盘要预先处理除去任何自然氧化物，这对本领域的普通技术人员是公知的。连续的钛阻挡层28(大约500埃厚)跨越钝化层26和接触焊盘24暴露的表面形成。不必大量腐蚀钝化层就可以很容易地从钝化层26上腐蚀掉钛阻挡层28。如果使用钛接触焊盘，由于钛阻挡层可以将氧气从钛接触焊盘中吸除，所以可以省掉预处理步骤。
然后在钛阻挡层28上形成连续的下凸点金属化层。下凸点金属化层由能使焊料凸点和接触焊盘之间充分粘接的材料形成，而不必大量腐蚀钛阻挡层就可以很容易地从钛阻挡层28上腐蚀掉该材料。因此，下凸点金属化层最好包括铬层30(大约1000埃厚)，铬层上的铬层和铜层相控层32(大约1000埃厚)，以及相控层上的铜层34(大约1微米厚)。包括铬层，铬层上的铬层和铜层相控层，以及相控层上的铜层的下凸点金属化层已在，例如，Yung的U.S.专利5,162,257“焊料凸点制造方法”中讨论过，在这里作为参考引入。
形成下凸点金属化层之后，形成焊料阻挡层。在优选实施例中，焊料阻挡层包括一层不可湿润层36(大约1500埃厚)，最好为一层铬或钛。焊料阻挡层也可以包括焊料可湿润层38(大约125埃厚)，例如焊料不可湿润层36上的铜层。例如，铜层在铬层上的焊料阻挡层允许焊料镀在其上，而后来的回流焊步骤将熔解暴露铬的铜。在这个实施例中，焊料可以均匀地电镀在焊料阻挡层的焊料可湿润层38上。然后将没有被焊料覆盖的焊料可湿润层的部分除去，因此防止了回流焊步骤期间焊料凸点的膨胀。当焊料加热到它的液化温度以上时(对含95％的铅和5％的锡的焊料大约为312℃)，焊料将回流、熔解可湿润层38剩下的部分，并与不可湿润层36接触。因此，回流的焊料凸点由于表面张力将大体上形成球形。图2显示的微电子器件20包括钛阻挡层28；具有铬层30，铬和铜的相控层32，和铜层34的下凸点金属化层；具有焊料不可湿润层36和焊料可湿润层38的焊料阻挡层。钛、铬、相控的铬和铜，和铜层中的每一层都是由蒸发、溅射、或本领域的普通技术人员公知的其它淀积技术形成。铬和铜的相控层可以由铬和铜共淀积形成。
如图3所示，选择除去接触焊盘24上需要形成焊料凸点的区域内的焊料阻挡层。可以通过标准的光刻/腐蚀技术或剥离(lift-off)技术选择除去焊料阻挡层的部分。如果使用了标准的光刻/腐蚀技术，由于不必大量地腐蚀铜层就可从下面的铜层34上选择性地除去钛，所以钛可优选地用做焊料不可湿润层36。未被焊料阻挡层(层36和38)覆盖的铜层34的区域限定了回流焊步骤后微电子器件上焊料凸点的表面区域，这将在下面讨论。
如光刻胶掩模等构图的掩模层40也形成在焊料阻挡层上，限定了焊料阻挡层和焊料要电镀的下凸点金属化层上未覆盖的区域。如图3和4所示，掩模层40未覆盖的表面区域大于焊料阻挡层(层36和38)未覆盖的各自的表面区域，因而可在更大的区域上镀焊料。如图4所示，焊料凸点42电镀在掩模层40未覆盖的区域上。
使用本领域的普通技术人员公知的电镀技术将焊料镀在焊料阻挡层和下凸点金属化层上未覆盖的区域。例如，带掩模层40的微电子器件20表面暴露在含有铅和锡的镀液中，偏置电压施加到包括铬层30，铬和铜的相控层32，和铜层34的连续的下凸点金属化层上。如图4所示，偏置电压使铅-锡焊料镀在铜层34和38的未覆盖部分上形成焊料凸点42。
通过控制掩模层40未覆盖的区域、施加的偏置电压、镀液的浓度，和电镀步骤的持续时间可以控制电镀的焊料量。由于焊料不能均匀地镀在如铬等焊料不可湿润材料上，在焊料不可湿润层36上使用带如铜层等的焊料可湿润层38的焊料阻挡层可使焊料均匀地镀在焊料阻挡层上未被掩模层覆盖的区域内。因此，焊料要电镀的区域，和所得的电镀量的决定都与焊料阻挡层未覆盖的区域无关，而焊料阻挡层未覆盖的区域决定了回流焊后微电子器件上焊料凸点的表面区域。
如图5所示，完成电镀步骤后，除去掩模层40和未被焊料凸点覆盖的焊料可湿润层38，之后将焊料凸点42加热到液化温度(对含95％的铅和5％的锡的焊料大约为312℃)以上，以使它们回流。如果焊料可湿润层为铜层，那么氢氧化铵和过氧化氢的混合物可以除去焊料可湿润层。当焊料凸点电镀到焊料阻挡层的焊料可湿润层38处，焊料可湿润层38熔解到焊料凸点中暴露焊料不可湿润层36于焊料凸点。因此，表面张力使回流的焊料凸点42在下凸点金属化层上未被焊料阻挡层覆盖的部分上大体上形成球形。当焊料凸点冷却时，固化的焊料保持大体上的球形。
此外，回流的焊料在紧邻焊料凸点的下凸点金属化层的部分形成金属间区域34′。在优选实施例中，下凸点金属化层包括铬层30，铬和铜的相控层32，和铜层34；焊料与铜层34的部分发生反应形成金属间区域34′。这个金属间区域包括不与腐蚀剂充分反应通常用于除去铜、铬，和钛的Cu3Sn。
如图5所示，回流的焊料凸点42限定了下凸点金属化层暴露和未暴露的部分。因此，焊料凸点42可用于掩蔽支持焊料凸点的下凸点金属化层的部分。如图6所示，除去由焊料凸点暴露的下凸点金属化层的部分，以便每个焊料凸点42与其它焊料凸点电隔离。
首先有必要除去焊料不可湿润层36。如果不可湿润层为铬，可使用盐酸除去焊料不可湿润层。同样，如果钛被用做不可湿润层，可使用氟化铵缓冲的氢氟酸除去。
焊料凸点42暴露的下凸点金属化层的部分可从钛阻挡层28上有效地除去，而钛阻挡层可以保护下面的钝化层26和接触焊盘24。然后使用不会严重影响将下面的钝化层的腐蚀剂除去钛阻挡层暴露的部分。
例如，使用如氢氧化铵和过氧化氢的混合物的化学腐蚀剂可以腐蚀由焊料凸点42暴露的铜层34。相对于焊料凸点、钛阻挡层28，和金属间区域34′，该混合物优先腐蚀铜层。因此，该腐蚀不会大量减少焊料凸点的焊料量或大量地钻蚀焊料凸点。该混合物也从铬和铜的相控层32上除去一些铜。
如盐酸等的化学腐蚀剂用于腐蚀焊料凸点暴露的相控层32和铬层30剩下的部分。相对于焊料凸点、钛阻挡层，和金属间区域34′，该酸优先腐蚀相控层和铬层。该酸从钛阻挡层上除去剩下的下凸点金属化层暴露的部分而不会留下大量的残余物。
使用如氟化铵缓冲的氢氟酸等的钛腐蚀剂腐蚀焊料凸点42暴露的钛阻挡层28的部分。相对于焊料凸点42、金属间区域34′、铬和铜的相控层32，铬层30，该酸优先腐蚀钛。如果使用聚酰亚胺层做钝化层26，该酸不会大量腐蚀钝化层。如果使用二氧化硅层或氮化硅层做钝化层，该酸对钝化层有一定程度的腐蚀。可通过限制除去钛阻挡层所需的持续时间将这些材料的腐蚀减到最小。因此，聚酰亚胺层为钝化层的优选材料。最终的焊料凸点结构显示在图6中。
没有钛阻挡层，回流焊步骤后很难完全除去下凸点金属化层，并且不需要的导电残留物会残留在微电子器件上。申请人理论上认为下凸点金属化层与钝化层反应在两层的界面上形成导电反应物。如不钻蚀焊料凸点或减少焊料凸点的量，该导电反应物很难腐蚀掉，因而导致存有不希望的导电残留物。这些残留物导致焊料凸点间的电短路。
使用钛阻挡层可将回流焊步骤后的下凸点金属化层有效地除去，从而减少形成焊料凸点间电短路的残留物发生。钛阻挡层可防止凸点金属化层与钝化层发生反应因而减少残留物。然后将钛阻挡层从钝化层上腐蚀掉不会留下显著的残留物。
尽管要在结构上产生附加层，但消除不希望的残留物一般会减少除去焊料凸点间的导电层所需的时间。由于钛阻挡层减少了总的腐蚀时间，因而减少了焊料凸点暴露在腐蚀剂中的时间，钻蚀减少。附加的钛阻挡层也会增加生产成品率并减少器件发生故障的可能性。根据以上介绍的方法形成的焊料凸点还具有低电阻。例如，微电子器件上直径为50μm具有圆形表面的焊料凸点显示的电阻大约为3毫欧姆。
以上相对于图1-6讨论的方法的变形显示在图7-12中。图7显示的包括衬底22，接触焊盘24，以及钝化层26的微电子器件20已在图1中介绍过。图8显示的附加的钛阻挡层，和包括铬层30、铬和铜的相控层32，和铜层34的下凸点金属化层也已在图2中介绍过。然而，在图8中，焊料阻挡层50仅包括单个焊料不可湿润层，该层最好为钛层(大约1000埃厚)。
使用钛焊料阻挡层在图9显示的焊料凸点形成期间用一次掩模法就可完成。这里，如光刻胶掩模或本领域的普通技术人员公知的其它掩模等的掩模层52在形成焊料阻挡层50的图形之前构图。然后使用掩模层52形成焊料阻挡层50的图形。因此，仅用一次光刻步骤就可以形成掩模层和焊料阻挡层的图形。最好用钛层做焊料阻挡层，是由于可使用相对于铜和焊料优先腐蚀钛的如氟化铵缓冲的氢氟酸等的腐蚀剂从铜层34上选择性地除去钛。由于焊料未镀在焊料阻挡层上，所以焊料阻挡层50不必有焊料可湿润层。这里，焊料阻挡层50仅在回流焊步骤期间防止焊料凸点的扩展。
如图10所示，掩模层52和焊料阻挡层50限定了焊料要镀在下凸点金属化层上的区域。除了焊料未镀在焊料阻挡层上以外，电镀步骤与根据图4介绍的电镀步骤一样。电镀焊料凸点之后，选择性地除去掩模层40，并且将焊料凸点加热到液化温度(对含95％的铅和5％的锡的焊料大约为312℃)以上回流焊料。焊料阻挡层50可防止回流的焊料流到要求的区域以外。如图11所示，表面张力使回流的焊料54形成大体上的球形。当焊料凸点冷却时，焊料凸点固化并保持这种形状。和以上讨论的图5一样，回流步骤也用于在铜层34中形成金属间区域34′。
和以上讨论的图5和6一样，焊料凸点限定了下凸点金属化层和钛阻挡层的暴露和未暴露的部分，除去暴露的部分，以便如图12所示使每个焊料凸点电绝缘。首先将焊料阻挡层50用如氟化铵缓冲的氢氟酸等的腐蚀剂除去。然后和以上讨论的图5和6一样，除去下凸点金属化层和钛阻挡层。
在图和说明书中，已公开了发明的一般优选实施例，虽然使用了特定的术语，但为一般的和说明性的理解，而不是为了限定，本发明的保护范围由以下权利要求限定。

Claims (10)

1.一种在微电子器件(20)上形成焊料凸点(42)的方法，微电子器件(20)具有衬底(22)和所述衬底(22)上的多个接触焊盘(24)，其中每个所述接触焊盘(24)都有暴露的表面部分，所述方法的特征在于以下步骤：
在所述接触焊盘(24)上形成连续的钛阻挡层(28)，其中所述阻挡层(28)覆盖所述接触焊盘(24)的所述暴露的表面部分，并在所述衬底上延伸；
在面对所述衬底的所述阻挡层(28)上形成下凸点金属化层(30，32，34)；
在面对所述接触焊盘(24)中的一个和所述阻挡层的所述暴露的表面部分，在所述下凸点金属化层(30，32，34)上形成焊料凸点(42)，因而限定了所述下凸点金属化层上暴露的和未暴露表面部分；
选择性地除去所述下凸点金属化层(30，32，34)的所述暴露部分，因而限定了所述阻挡层(28)的暴露部分；
选择性地除去所述阻挡层(28)的所述暴露部分；并且
其中形成下凸点金属化层的步骤包括：
在所述钛阻挡层(28)上形成铬层(30)，和
在面对所述阻挡层(28)的所述铬层(30)上形成铜层(34)。
2.根据权利要求1的方法，其中形成下凸点金属化层的所述步骤还包括：
形成所述铜层之前在面对所述阻挡层的所述铬层上形成铬和铜的相控层。
3.根据权利要求1的方法，其中在所述下凸点金属化层的所述暴露部分上形成包括焊料不可湿润层的焊料阻挡层的步骤先于所述形成焊料凸点的步骤，其中除去所述焊料阻挡层的步骤先于所述选择性地除去所述下凸点金属化层的所述暴露部分的步骤。
4.根据权利要求2的方法，其中所述选择性地除去所述下凸点金属化层(30，32，34)的所述暴露部分的步骤还包括：
对所述铜层(34)的所述暴露部分使用铜腐蚀剂，其中相对于所述焊料凸点(42)、所述铬层(30)、和所述钛阻挡层(28)，所述铜腐蚀剂优先选择性地腐蚀所述铜层(34)和所述相控层(32)的所述铜部分；以及
对所述相控层(32)的所述铬部分和所述铬层(30)使用铬腐蚀剂，其中相对于所述焊料凸点(42)、所述铜层(34)、和所述钛阻挡层(28)，所述铬腐蚀剂优先选择性地腐蚀所述相控层(32)的所述铬部分和所述铬层(30)。
5.根据权利要求3的方法，其中所述形成焊料阻挡层的步骤还包括在面对所述下凸点金属化层上的所述焊料不可湿润层(36)上形成焊料可湿润层(38)的步骤。
6.一种微电子器件(20)的焊料凸点结构，微电子器件(20)具有衬底(22)和所述衬底(22)上的多个接触焊盘(24)，其中每个所述接触焊盘(24)都有面对所述衬底的暴露的表面部分，所述焊料凸点结构的特征在于：
连续的钛阻挡层(28)在所述衬底上延伸并与所述每个接触焊盘(24)所述的暴露的表面部分接触；
在面对所述衬底的所述阻挡层(28)上形成连续的下凸点金属化层(30，32，34)；
在面对所述接触焊盘(24)中一个的所述下凸点金属化层(30，32，34)上形成焊料凸点(42)；并且
其中所述连续的下凸点金属化层包括：
在所述钛阻挡层(28)上的铬层(30)，
在相对于所述阻挡层(28)的所述铬层(30)上的铜层(34)。
7.根据权利要求6的焊料凸点结构，其中所述连续的下凸点金属化层还包括：
在所述铬层和所述铜层之间的铬和铜的相控层。
8.根据权利要求6的焊料凸点结构，其中所述焊料凸点限定了所述下凸点金属化层的暴露部分，所述结构还包括：在面对所述阻挡层的所述下凸点金属化层的所述暴露部分上的焊料阻挡层，并且其中所述焊料阻挡层包括焊料不可湿润层。
9.根据权利要求8的焊料凸点结构，其中所述焊料不可湿润层(36)选自包括钛层和铬层的组中。
10.根据权利要求8的焊料凸点结构，其中所述焊料阻挡层还包括相对于所述下凸点金属化层，在所述焊料不可湿润层(36)上的焊料可湿润层(38)。
CN96193314A 1995-03-20 1996-03-18 含有钛阻挡层的焊料凸点结构及其形成方法 Expired - Fee Related CN1096110C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40719695A 1995-03-20 1995-03-20
US08/407,196 1995-03-20

Publications (2)

Publication Number Publication Date
CN1181841A CN1181841A (zh) 1998-05-13
CN1096110C true CN1096110C (zh) 2002-12-11

Family

ID=23611033

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96193314A Expired - Fee Related CN1096110C (zh) 1995-03-20 1996-03-18 含有钛阻挡层的焊料凸点结构及其形成方法

Country Status (10)

Country Link
US (2) US5767010A (zh)
EP (3) EP1134805B1 (zh)
JP (1) JPH11505668A (zh)
KR (1) KR100367702B1 (zh)
CN (1) CN1096110C (zh)
AT (2) ATE271718T1 (zh)
AU (1) AU6376796A (zh)
DE (2) DE69632969T2 (zh)
HK (1) HK1036523A1 (zh)
WO (1) WO1996030933A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316581C (zh) * 2003-07-31 2007-05-16 国际商业机器公司 用于改良晶片可靠性的密封针脚结构

Families Citing this family (144)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08106617A (ja) * 1994-10-04 1996-04-23 Fujitsu Ltd 磁気ディスク装置
US5902686A (en) * 1996-11-21 1999-05-11 Mcnc Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
US6188120B1 (en) * 1997-02-24 2001-02-13 International Business Machines Corporation Method and materials for through-mask electroplating and selective base removal
US5990564A (en) * 1997-05-30 1999-11-23 Lucent Technologies Inc. Flip chip packaging of memory chips
JP3080047B2 (ja) * 1997-11-07 2000-08-21 日本電気株式会社 バンプ構造体及びバンプ構造体形成方法
US6875681B1 (en) * 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
JPH11340265A (ja) * 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法
US6794752B2 (en) * 1998-06-05 2004-09-21 United Microelectronics Corp. Bonding pad structure
KR100295054B1 (ko) * 1998-09-16 2001-08-07 윤종용 다층금속배선을갖는반도체소자및그제조방법
US6268114B1 (en) * 1998-09-18 2001-07-31 Taiwan Semiconductor Manufacturing Company, Ltd Method for forming fine-pitched solder bumps
US6214716B1 (en) * 1998-09-30 2001-04-10 Micron Technology, Inc. Semiconductor substrate-based BGA interconnection and methods of farication same
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
US6534340B1 (en) * 1998-11-18 2003-03-18 Analog Devices, Inc. Cover cap for semiconductor wafer devices
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6936531B2 (en) * 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US7416971B2 (en) * 2004-09-23 2008-08-26 Megica Corporation Top layers of metal for integrated circuits
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6327158B1 (en) * 1999-01-15 2001-12-04 National Semiconductor Corporation Metal pads for electrical probe testing on wafer with bump interconnects
JP4130508B2 (ja) * 1999-01-22 2008-08-06 富士通株式会社 半田接合方法及び電子装置の製造方法
US6232212B1 (en) * 1999-02-23 2001-05-15 Lucent Technologies Flip chip bump bonding
JP3667184B2 (ja) * 1999-02-26 2005-07-06 住友ベークライト株式会社 半導体装置
US20030038366A1 (en) * 1999-03-09 2003-02-27 Kabushiki Kaisha Toshiba Three-dimensional semiconductor device having plural active semiconductor components
US6543131B1 (en) * 1999-03-10 2003-04-08 Tessera, Inc. Microelectronic joining processes with temporary securement
US20020000665A1 (en) * 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
US6656750B1 (en) * 1999-04-29 2003-12-02 International Business Machines Corporation Method for testing chips on flat solder bumps
US6649533B1 (en) 1999-05-05 2003-11-18 Advanced Micro Devices, Inc. Method and apparatus for forming an under bump metallurgy layer
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6352881B1 (en) 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
JP3514670B2 (ja) * 1999-07-29 2004-03-31 松下電器産業株式会社 半田付け方法
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
JP3859403B2 (ja) * 1999-09-22 2006-12-20 株式会社東芝 半導体装置及びその製造方法
US6306751B1 (en) * 1999-09-27 2001-10-23 Lsi Logic Corporation Apparatus and method for improving ball joints in semiconductor packages
US6146984A (en) * 1999-10-08 2000-11-14 Agilent Technologies Inc. Method and structure for uniform height solder bumps on a semiconductor wafer
KR100311975B1 (ko) * 1999-12-16 2001-10-17 윤종용 반도체소자 및 그 제조방법
US6387793B1 (en) * 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
US6707153B2 (en) * 2000-03-23 2004-03-16 Seiko Epson Corporation Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
US6293457B1 (en) * 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
WO2002009237A1 (en) * 2000-07-26 2002-01-31 Advance Interconnect Solutions Method and apparatus for protecting and strengthening electrical contact interfaces
TW459362B (en) * 2000-08-01 2001-10-11 Siliconware Precision Industries Co Ltd Bump structure to improve the smoothness
US6444561B1 (en) * 2000-10-02 2002-09-03 Industrial Technology Research Institute Method for forming solder bumps for flip-chip bonding by using perpendicularly laid masking strips
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
DE60108413T2 (de) * 2000-11-10 2005-06-02 Unitive Electronics, Inc. Verfahren zum positionieren von komponenten mit hilfe flüssiger antriebsmittel und strukturen hierfür
KR100640576B1 (ko) * 2000-12-26 2006-10-31 삼성전자주식회사 유비엠의 형성방법 및 그에 의해 형성된 반도체 소자
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
TW480685B (en) * 2001-03-22 2002-03-21 Apack Technologies Inc Wafer-level package process
US6759319B2 (en) 2001-05-17 2004-07-06 Institute Of Microelectronics Residue-free solder bumping process
US6667230B2 (en) * 2001-07-12 2003-12-23 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation and planarization process for flip chip packages
US6747298B2 (en) 2001-07-23 2004-06-08 Cree, Inc. Collets for bonding of light emitting diodes having shaped substrates
US6888167B2 (en) * 2001-07-23 2005-05-03 Cree, Inc. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US6740427B2 (en) * 2001-09-21 2004-05-25 Intel Corporation Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same
US20030060041A1 (en) * 2001-09-21 2003-03-27 Intel Corporation Dual-stack, ball-limiting metallurgy and method of making same
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
US6798073B2 (en) * 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same
US6664697B2 (en) * 2001-12-13 2003-12-16 Northrop Grumman Corporation Electrical slip ring apparatus having multiple spaced apart support structures
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US6593220B1 (en) 2002-01-03 2003-07-15 Taiwan Semiconductor Manufacturing Company Elastomer plating mask sealed wafer level package method
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
TW521406B (en) * 2002-01-07 2003-02-21 Advanced Semiconductor Eng Method for forming bump
US6756294B1 (en) * 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US20030217026A1 (en) * 2002-01-31 2003-11-20 Steven Teig Structure for storing a plurality os sub-networks
US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
TW521359B (en) * 2002-02-20 2003-02-21 Advanced Semiconductor Eng Bump fabrication process
TW556293B (en) * 2002-02-21 2003-10-01 Advanced Semiconductor Eng Bump process
TWI239578B (en) * 2002-02-21 2005-09-11 Advanced Semiconductor Eng Manufacturing process of bump
TW586208B (en) * 2002-02-26 2004-05-01 Advanced Semiconductor Eng Wafer-level packaging structure
US6861762B1 (en) * 2002-05-01 2005-03-01 Marvell Semiconductor Israel Ltd. Flip chip with novel power and ground arrangement
US6596619B1 (en) 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
US6774026B1 (en) * 2002-06-20 2004-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for low-stress concentration solder bumps
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
WO2004001837A2 (en) * 2002-06-25 2003-12-31 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US7423337B1 (en) 2002-08-19 2008-09-09 National Semiconductor Corporation Integrated circuit device package having a support coating for improved reliability during temperature cycling
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
TWI281718B (en) * 2002-09-10 2007-05-21 Advanced Semiconductor Eng Bump and process thereof
KR100521081B1 (ko) * 2002-10-12 2005-10-14 삼성전자주식회사 플립 칩의 제조 및 실장 방법
US6790758B2 (en) * 2002-11-25 2004-09-14 Silicon Integrated Systems Corp. Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
US6802945B2 (en) * 2003-01-06 2004-10-12 Megic Corporation Method of metal sputtering for integrated circuit metal routing
US7301222B1 (en) 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
TWI223883B (en) * 2003-06-30 2004-11-11 Advanced Semiconductor Eng Under bump metallurgy structure
WO2005024912A2 (en) * 2003-09-09 2005-03-17 Intel Corporation Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US7410833B2 (en) * 2004-03-31 2008-08-12 International Business Machines Corporation Interconnections for flip-chip using lead-free solders and having reaction barrier layers
WO2005101499A2 (en) * 2004-04-13 2005-10-27 Unitive International Limited Methods of forming solder bumps on exposed metal pads and related structures
US7282375B1 (en) 2004-04-14 2007-10-16 National Semiconductor Corporation Wafer level package design that facilitates trimming and testing
JP4327656B2 (ja) * 2004-05-20 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8022544B2 (en) * 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US7355282B2 (en) * 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US7423346B2 (en) * 2004-09-09 2008-09-09 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US20060076677A1 (en) * 2004-10-12 2006-04-13 International Business Machines Corporation Resist sidewall spacer for C4 BLM undercut control
US7521805B2 (en) * 2004-10-12 2009-04-21 Megica Corp. Post passivation interconnection schemes on top of the IC chips
US20060160267A1 (en) * 2005-01-14 2006-07-20 Stats Chippac Ltd. Under bump metallurgy in integrated circuits
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US8384189B2 (en) * 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
TWI267155B (en) * 2005-08-23 2006-11-21 Advanced Semiconductor Eng Bumping process and structure thereof
US7323780B2 (en) * 2005-11-10 2008-01-29 International Business Machines Corporation Electrical interconnection structure formation
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
CN100468713C (zh) * 2006-05-15 2009-03-11 中芯国际集成电路制造(上海)有限公司 半导体晶片焊料凸块结构及其制造方法
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US7748116B2 (en) * 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US9610758B2 (en) * 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
TWI345816B (en) * 2007-08-28 2011-07-21 Advanced Semiconductor Eng Method for forming bumps on under bump metallurgy
TWI446843B (zh) * 2007-12-11 2014-07-21 Unimicron Technology Corp 線路板及其製程
US7993971B2 (en) * 2007-12-28 2011-08-09 Freescale Semiconductor, Inc. Forming a 3-D semiconductor die structure with an intermetallic formation
US7875519B2 (en) * 2008-05-21 2011-01-25 Intel Corporation Metal gate structure and method of manufacturing same
CN103050420A (zh) * 2008-06-05 2013-04-17 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
US8227333B2 (en) 2010-11-17 2012-07-24 International Business Machines Corporation Ni plating of a BLM edge for Pb-free C4 undercut control
JP2012114148A (ja) * 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
KR101283580B1 (ko) * 2011-12-14 2013-07-05 엠케이전자 주식회사 주석계 솔더 볼 및 이를 포함하는 반도체 패키지
US9018737B2 (en) 2013-03-06 2015-04-28 Seagate Technology Llc Submount assembly integration
KR20150057838A (ko) * 2013-11-20 2015-05-28 삼성전기주식회사 전자 부품 모듈
SG10201503988YA (en) * 2014-05-29 2015-12-30 Applied Materials Inc Reduced titanium undercut in etch process
FR3050865B1 (fr) * 2016-05-02 2018-10-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'interconnexions conductrices sur un substrat et interconnexions ainsi obtenues
US10242926B2 (en) * 2016-06-29 2019-03-26 Alpha And Omega Semiconductor (Cayman) Ltd. Wafer level chip scale package structure and manufacturing method thereof
US10120971B2 (en) * 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US10706880B1 (en) 2019-04-02 2020-07-07 Seagate Technology Llc Electrically conductive solder non-wettable bond pads in head gimbal assemblies
US11171017B2 (en) 2019-09-06 2021-11-09 Applied Materials, Inc. Shutter disk
US11990369B2 (en) 2021-08-20 2024-05-21 Applied Materials, Inc. Selective patterning with molecular layer deposition
CN115995444A (zh) * 2021-10-19 2023-04-21 群创光电股份有限公司 电子组件及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3663184A (en) * 1970-01-23 1972-05-16 Fairchild Camera Instr Co Solder bump metallization system using a titanium-nickel barrier layer
US3839727A (en) * 1973-06-25 1974-10-01 Ibm Semiconductor chip to substrate solder bond using a locally dispersed, ternary intermetallic compound
US4042954A (en) * 1975-05-19 1977-08-16 National Semiconductor Corporation Method for forming gang bonding bumps on integrated circuit semiconductor devices
US4293637A (en) * 1977-05-31 1981-10-06 Matsushita Electric Industrial Co., Ltd. Method of making metal electrode of semiconductor device
JPS53149763A (en) * 1977-06-01 1978-12-27 Citizen Watch Co Ltd Mounting method of semiconductor integrate circuit
JPS55111127A (en) * 1979-02-19 1980-08-27 Fuji Electric Co Ltd Method for forming solder bump
JPS55156339A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Forming method of bump electrode
JPS5649543A (en) * 1979-09-28 1981-05-06 Hitachi Ltd Method for forming solder bump
JPS5666057A (en) * 1979-11-02 1981-06-04 Hitachi Ltd Formation of electrode of semiconductor element
US4273859A (en) * 1979-12-31 1981-06-16 Honeywell Information Systems Inc. Method of forming solder bump terminals on semiconductor elements
JPS5711141A (en) * 1980-06-23 1982-01-20 Komatsu Ltd Outrigger operating circuit for mobile crane
JPS5773952A (en) * 1980-10-27 1982-05-08 Hitachi Ltd Chip for face down bonding and production thereof
JPS57197838A (en) * 1981-05-29 1982-12-04 Oki Electric Ind Co Ltd Semiconductor flip chip element
JPS59117135A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 半導体装置の製造方法
JPS59154041A (ja) * 1983-02-22 1984-09-03 Fuji Electric Corp Res & Dev Ltd 半導体装置の電極形成方法
US4513905A (en) * 1983-07-29 1985-04-30 The Perkin-Elmer Corporation Integrated circuit metallization technique
JPS59145537A (ja) * 1984-02-08 1984-08-21 Hitachi Ltd 半導体装置
JPS60180146A (ja) * 1984-02-27 1985-09-13 Nippon Telegr & Teleph Corp <Ntt> ソルダバンプの一括形成方法
US4661375A (en) * 1985-04-22 1987-04-28 At&T Technologies, Inc. Method for increasing the height of solder bumps
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device
KR910006967B1 (ko) * 1987-11-18 1991-09-14 가시오 게이상기 가부시기가이샤 반도체 장치의 범프 전극 구조 및 그 형성 방법
US4840302A (en) * 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
JPH0237724A (ja) * 1988-07-28 1990-02-07 Nec Corp 半導体装置の突起型電極の形成方法
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
KR940010510B1 (ko) * 1988-11-21 1994-10-24 세이꼬 엡슨 가부시끼가이샤 반도체 장치 제조 방법
US5498573A (en) * 1989-11-29 1996-03-12 General Electric Company Method of making multi-layer address lines for amorphous silicon liquid crystal display devices
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
US5296407A (en) * 1990-08-30 1994-03-22 Seiko Epson Corporation Method of manufacturing a contact structure for integrated circuits
JP2731040B2 (ja) * 1991-02-05 1998-03-25 三菱電機株式会社 半導体装置の製造方法
JPH0513421A (ja) * 1991-07-04 1993-01-22 Tanaka Kikinzoku Kogyo Kk バンプ形成方法
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
EP0566253A1 (en) * 1992-03-31 1993-10-20 STMicroelectronics, Inc. Method for forming contact structures in integrated circuits
JP2796919B2 (ja) * 1992-05-11 1998-09-10 インターナショナル・ビジネス・マシーンズ・コーポレーション メタライゼーション複合体および半導体デバイス
JPH0653241A (ja) * 1992-08-03 1994-02-25 Nec Corp 電界効果トランジスタの製造方法
US5234149A (en) * 1992-08-28 1993-08-10 At&T Bell Laboratories Debondable metallic bonding method
US5268072A (en) * 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
JPH07105586B2 (ja) * 1992-09-15 1995-11-13 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップ結合構造
KR960004089B1 (ko) * 1992-12-30 1996-03-26 현대전자산업주식회사 반도체소자의 저저항 접촉형성방법
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
US5396702A (en) * 1993-12-15 1995-03-14 At&T Corp. Method for forming solder bumps on a substrate using an electrodeposition technique
JP3054021B2 (ja) * 1993-12-27 2000-06-19 株式会社東芝 化合物半導体装置
US5440167A (en) * 1994-02-23 1995-08-08 Crosspoint Solutions, Inc. Antifuse with double via contact and method of manufacture therefor
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5620611A (en) * 1996-06-06 1997-04-15 International Business Machines Corporation Method to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder pads

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316581C (zh) * 2003-07-31 2007-05-16 国际商业机器公司 用于改良晶片可靠性的密封针脚结构

Also Published As

Publication number Publication date
WO1996030933A3 (en) 1996-11-28
EP1134805A2 (en) 2001-09-19
US6222279B1 (en) 2001-04-24
KR100367702B1 (ko) 2003-04-07
CN1181841A (zh) 1998-05-13
US5767010A (en) 1998-06-16
EP0815593A2 (en) 1998-01-07
DE69617928T2 (de) 2002-07-18
EP1134805A3 (en) 2001-12-12
EP1441388A3 (en) 2004-09-22
DE69617928D1 (de) 2002-01-24
WO1996030933A2 (en) 1996-10-03
EP0815593B1 (en) 2001-12-12
EP1441388A2 (en) 2004-07-28
HK1036523A1 (en) 2002-01-04
AU6376796A (en) 1996-10-16
ATE210895T1 (de) 2001-12-15
JPH11505668A (ja) 1999-05-21
EP1134805B1 (en) 2004-07-21
DE69632969D1 (de) 2004-08-26
ATE271718T1 (de) 2004-08-15
KR19980703139A (ko) 1998-10-15
DE69632969T2 (de) 2005-07-28

Similar Documents

Publication Publication Date Title
CN1096110C (zh) 含有钛阻挡层的焊料凸点结构及其形成方法
EP0690504B1 (en) Solder terminal and method of fabricating it
US8580679B2 (en) Designs and methods for conductive bumps
US20080251927A1 (en) Electromigration-Resistant Flip-Chip Solder Joints
EP1321982B1 (en) Wafer-level method of fabricating a contact pad copper cap layer
US6329722B1 (en) Bonding pads for integrated circuits having copper interconnect metallization
US7328830B2 (en) Structure and method for bonding to copper interconnect structures
JP3172501B2 (ja) チタン・タングステン合金のエッチング方法およびエッチャント溶液
US3663184A (en) Solder bump metallization system using a titanium-nickel barrier layer
EP0687751B1 (en) Selective etching of TiW for C4 fabrication
US7005752B2 (en) Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
US7262126B2 (en) Sealing and protecting integrated circuit bonding pads
KR20010098699A (ko) 납 없는 범프 배선의 형성 방법
US5171711A (en) Method of manufacturing integrated circuit devices
US5800726A (en) Selective chemical etching in microelectronics fabrication
US7375020B2 (en) Method of forming bumps
US20080119056A1 (en) Method for improved copper layer etching of wafers with c4 connection structures
JP2001352005A (ja) 配線基板および半導体装置
CN1622287A (zh) 焊锡凸块的形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: UNITY INTERNATIONAL LIMITED

Free format text: FORMER OWNER: MICROELECTRONICS CENTRE OF NORTH CAROLING

Effective date: 20010712

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20010712

Address after: The Netherlands Antilles

Applicant after: Unitive Internat Ltd.

Address before: North Carolina

Applicant before: North Carolina Microelectronic Center

C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee