JP2010093771A - Ｄｌｌ回路 - Google Patents

Ｄｌｌ回路 Download PDF

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Publication number
JP2010093771A
JP2010093771A JP2009010679A JP2009010679A JP2010093771A JP 2010093771 A JP2010093771 A JP 2010093771A JP 2009010679 A JP2009010679 A JP 2009010679A JP 2009010679 A JP2009010679 A JP 2009010679A JP 2010093771 A JP2010093771 A JP 2010093771A
Authority
JP
Japan
Prior art keywords
clock
phase
unit
delay
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009010679A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010093771A5 (enExample
Inventor
Yong-Ju Kim
龍 珠 金
Sung Woo Han
成 宇 韓
Hee-Woong Song
喜 雄 宋
益 秀 ▲呉▼
Ic Su Oh
Hyung-Soo Kim
亨 洙 金
泰 鎭 ▲黄▼
Tae-Jin Hwang
Hae Rang Choi
▲海▼ ▲郎▼ 崔
Ji Wang Lee
智 王 李
Jae Min Jang
在 旻 張
Chang Keun Park
昌 根 朴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2010093771A publication Critical patent/JP2010093771A/ja
Publication of JP2010093771A5 publication Critical patent/JP2010093771A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
JP2009010679A 2008-10-13 2009-01-21 Ｄｌｌ回路 Pending JP2010093771A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080100255A KR100980405B1 (ko) 2008-10-13 2008-10-13 Ｄｌｌ 회로

Publications (2)

Publication Number Publication Date
JP2010093771A true JP2010093771A (ja) 2010-04-22
JP2010093771A5 JP2010093771A5 (enExample) 2012-03-08

Family

ID=42098306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009010679A Pending JP2010093771A (ja) 2008-10-13 2009-01-21 Ｄｌｌ回路

Country Status (4)

Country Link
US (1) US7821311B2 (enExample)
JP (1) JP2010093771A (enExample)
KR (1) KR100980405B1 (enExample)
TW (1) TWI488440B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120063186A1 (en) * 2010-09-15 2012-03-15 Tsui Philip Yu Wing Low current consumption electrical control switch
KR101765306B1 (ko) * 2016-08-19 2017-08-07 아주대학교산학협력단 분수형 주파수체배 지연고정루프

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KR101022669B1 (ko) * 2008-12-02 2011-03-22 주식회사 하이닉스반도체 지연고정루프회로
US7872507B2 (en) * 2009-01-21 2011-01-18 Micron Technology, Inc. Delay lines, methods for delaying a signal, and delay lock loops
KR20120111282A (ko) * 2011-03-31 2012-10-10 에스케이하이닉스 주식회사 클럭 신호 생성회로
JP6241246B2 (ja) * 2013-12-10 2017-12-06 セイコーエプソン株式会社 検出装置、センサー、電子機器及び移動体
JP5880603B2 (ja) * 2014-03-19 2016-03-09 日本電気株式会社 クロック発生装置、サーバシステムおよびクロック制御方法
CN106026994B (zh) * 2016-05-16 2019-03-01 东南大学 一种基于pvtm的宽电压时钟拉伸电路
US10659059B2 (en) * 2018-10-02 2020-05-19 Texas Instruments Incorporated Multi-phase clock generation circuit
JP6903195B1 (ja) * 2020-05-15 2021-07-14 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 遅延ロックループデバイスとその動作方法
US10965292B1 (en) 2020-06-08 2021-03-30 Winbond Electronics Corp. Delay-locked loop device and operation method therefor
KR20220003712A (ko) * 2020-07-02 2022-01-11 삼성전자주식회사 지연 고정 루프 회로의 지연 회로 및 지연 고정 루프 회로
KR102532895B1 (ko) * 2021-01-28 2023-05-15 고려대학교 산학협력단 적응형 위상 회전자 지연 고정 루프 및 그 동작 방법
US11742862B2 (en) * 2021-08-25 2023-08-29 Nanya Technology Corporation Delay locked loop device and method for operating the same

Citations (3)

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JPH11346145A (ja) * 1998-05-29 1999-12-14 Nec Corp 多相クロック生成回路及び方法
JP2001028538A (ja) * 1999-05-27 2001-01-30 Silicon Image Inc 広帯域遅延ロックループ回路
JP2004222276A (ja) * 2003-01-09 2004-08-05 Hynix Semiconductor Inc トラッキングアナログ−デジタル変換器を備えるアナログ遅延固定ループ及びアナログ位相固定ループ

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US4069462A (en) * 1976-12-13 1978-01-17 Data General Corporation Phase-locked loops
DE68915228T2 (de) * 1988-09-02 1994-12-15 Sanyo Electric Co Phasensynchronisierschaltung in einem Videosignalempfänger und Verfahren zur Herstellung der Phasensynchronisation.
JPH08180678A (ja) * 1994-12-27 1996-07-12 Hitachi Ltd ダイナミック型ｒａｍ
JP3189774B2 (ja) * 1998-01-28 2001-07-16 日本電気株式会社 ビット同期回路
US6219397B1 (en) * 1998-03-20 2001-04-17 Samsung Electronics Co., Ltd. Low phase noise CMOS fractional-N frequency synthesizer for wireless communications
US6310498B1 (en) * 1998-12-09 2001-10-30 Agere Systems Guardian Corp. Digital phase selection circuitry and method for reducing jitter
JP2000357951A (ja) * 1999-06-15 2000-12-26 Mitsubishi Electric Corp 遅延回路、クロック生成回路及び位相同期回路
JP2001007698A (ja) * 1999-06-25 2001-01-12 Mitsubishi Electric Corp データｐｌｌ回路
JP3622685B2 (ja) * 2000-10-19 2005-02-23 セイコーエプソン株式会社 サンプリングクロック生成回路、データ転送制御装置及び電子機器
US6809567B1 (en) * 2001-04-09 2004-10-26 Silicon Image System and method for multiple-phase clock generation
US6690243B1 (en) * 2001-06-07 2004-02-10 Cypress Semiconductor Corp. Multi-phase voltage-controlled oscillator at modulated, operating frequency
TW525350B (en) * 2001-12-20 2003-03-21 Realtek Semiconductor Co Ltd Hybrid phase locked loop
US6794912B2 (en) 2002-02-18 2004-09-21 Matsushita Electric Industrial Co., Ltd. Multi-phase clock transmission circuit and method
KR100477808B1 (ko) * 2002-05-21 2005-03-21 주식회사 하이닉스반도체 듀티 사이클 교정이 가능한 디지털 디엘엘 장치 및 듀티사이클 교정 방법
JP4031671B2 (ja) * 2002-06-11 2008-01-09 松下電器産業株式会社 クロックリカバリ回路
JP4660076B2 (ja) * 2003-06-23 2011-03-30 ルネサスエレクトロニクス株式会社 クロック発生回路
US7319345B2 (en) 2004-05-18 2008-01-15 Rambus Inc. Wide-range multi-phase clock generator
TW200721688A (en) * 2005-11-25 2007-06-01 Realtek Semiconductor Corp Phase lock circuit

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Publication number Priority date Publication date Assignee Title
JPH11346145A (ja) * 1998-05-29 1999-12-14 Nec Corp 多相クロック生成回路及び方法
JP2001028538A (ja) * 1999-05-27 2001-01-30 Silicon Image Inc 広帯域遅延ロックループ回路
JP2004222276A (ja) * 2003-01-09 2004-08-05 Hynix Semiconductor Inc トラッキングアナログ−デジタル変換器を備えるアナログ遅延固定ループ及びアナログ位相固定ループ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120063186A1 (en) * 2010-09-15 2012-03-15 Tsui Philip Yu Wing Low current consumption electrical control switch
US9343990B2 (en) * 2010-09-15 2016-05-17 Philip Yu Wing TSUI Low current consumption electrical control switch
KR101765306B1 (ko) * 2016-08-19 2017-08-07 아주대학교산학협력단 분수형 주파수체배 지연고정루프

Also Published As

Publication number Publication date
US7821311B2 (en) 2010-10-26
TWI488440B (zh) 2015-06-11
US20100090736A1 (en) 2010-04-15
TW201015864A (en) 2010-04-16
KR20100041197A (ko) 2010-04-22
KR100980405B1 (ko) 2010-09-07

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