KR100980405B1 - Ｄｌｌ 회로 - Google Patents

Ｄｌｌ 회로 Download PDF

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Publication number
KR100980405B1
KR100980405B1 KR1020080100255A KR20080100255A KR100980405B1 KR 100980405 B1 KR100980405 B1 KR 100980405B1 KR 1020080100255 A KR1020080100255 A KR 1020080100255A KR 20080100255 A KR20080100255 A KR 20080100255A KR 100980405 B1 KR100980405 B1 KR 100980405B1
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KR
South Korea
Prior art keywords
phase
clock
delay
control signal
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020080100255A
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English (en)
Korean (ko)
Other versions
KR20100041197A (ko
Inventor
김용주
한성우
송희웅
오익수
김형수
황태진
최해랑
이지왕
장재민
박창근
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080100255A priority Critical patent/KR100980405B1/ko
Priority to US12/346,614 priority patent/US7821311B2/en
Priority to JP2009010679A priority patent/JP2010093771A/ja
Priority to TW098122594A priority patent/TWI488440B/zh
Publication of KR20100041197A publication Critical patent/KR20100041197A/ko
Application granted granted Critical
Publication of KR100980405B1 publication Critical patent/KR100980405B1/ko
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
KR1020080100255A 2008-10-13 2008-10-13 Ｄｌｌ 회로 Expired - Fee Related KR100980405B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020080100255A KR100980405B1 (ko) 2008-10-13 2008-10-13 Ｄｌｌ 회로
US12/346,614 US7821311B2 (en) 2008-10-13 2008-12-30 Delay locked loop circuit and memory device having the same
JP2009010679A JP2010093771A (ja) 2008-10-13 2009-01-21 Ｄｌｌ回路
TW098122594A TWI488440B (zh) 2008-10-13 2009-07-03 延遲鎖定迴路電路及具有延遲鎖定迴路電路之記憶裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080100255A KR100980405B1 (ko) 2008-10-13 2008-10-13 Ｄｌｌ 회로

Publications (2)

Publication Number Publication Date
KR20100041197A KR20100041197A (ko) 2010-04-22
KR100980405B1 true KR100980405B1 (ko) 2010-09-07

Family

ID=42098306

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080100255A Expired - Fee Related KR100980405B1 (ko) 2008-10-13 2008-10-13 Ｄｌｌ 회로

Country Status (4)

Country Link
US (1) US7821311B2 (enExample)
JP (1) JP2010093771A (enExample)
KR (1) KR100980405B1 (enExample)
TW (1) TWI488440B (enExample)

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* Cited by examiner, † Cited by third party
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KR101022669B1 (ko) * 2008-12-02 2011-03-22 주식회사 하이닉스반도체 지연고정루프회로
US7872507B2 (en) * 2009-01-21 2011-01-18 Micron Technology, Inc. Delay lines, methods for delaying a signal, and delay lock loops
CA2714458C (en) * 2010-09-15 2012-02-21 Philip Y.W. Tsui Low current consumption electrical control switch
KR20120111282A (ko) * 2011-03-31 2012-10-10 에스케이하이닉스 주식회사 클럭 신호 생성회로
JP6241246B2 (ja) * 2013-12-10 2017-12-06 セイコーエプソン株式会社 検出装置、センサー、電子機器及び移動体
JP5880603B2 (ja) * 2014-03-19 2016-03-09 日本電気株式会社 クロック発生装置、サーバシステムおよびクロック制御方法
CN106026994B (zh) * 2016-05-16 2019-03-01 东南大学 一种基于pvtm的宽电压时钟拉伸电路
KR101765306B1 (ko) * 2016-08-19 2017-08-07 아주대학교산학협력단 분수형 주파수체배 지연고정루프
US10659059B2 (en) * 2018-10-02 2020-05-19 Texas Instruments Incorporated Multi-phase clock generation circuit
JP6903195B1 (ja) * 2020-05-15 2021-07-14 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 遅延ロックループデバイスとその動作方法
US10965292B1 (en) 2020-06-08 2021-03-30 Winbond Electronics Corp. Delay-locked loop device and operation method therefor
KR20220003712A (ko) * 2020-07-02 2022-01-11 삼성전자주식회사 지연 고정 루프 회로의 지연 회로 및 지연 고정 루프 회로
KR102532895B1 (ko) * 2021-01-28 2023-05-15 고려대학교 산학협력단 적응형 위상 회전자 지연 고정 루프 및 그 동작 방법
US11742862B2 (en) * 2021-08-25 2023-08-29 Nanya Technology Corporation Delay locked loop device and method for operating the same

Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2000357951A (ja) * 1999-06-15 2000-12-26 Mitsubishi Electric Corp 遅延回路、クロック生成回路及び位相同期回路

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US4069462A (en) * 1976-12-13 1978-01-17 Data General Corporation Phase-locked loops
DE68915228T2 (de) * 1988-09-02 1994-12-15 Sanyo Electric Co Phasensynchronisierschaltung in einem Videosignalempfänger und Verfahren zur Herstellung der Phasensynchronisation.
JPH08180678A (ja) * 1994-12-27 1996-07-12 Hitachi Ltd ダイナミック型ｒａｍ
JP3189774B2 (ja) * 1998-01-28 2001-07-16 日本電気株式会社 ビット同期回路
US6219397B1 (en) * 1998-03-20 2001-04-17 Samsung Electronics Co., Ltd. Low phase noise CMOS fractional-N frequency synthesizer for wireless communications
JPH11346145A (ja) * 1998-05-29 1999-12-14 Nec Corp 多相クロック生成回路及び方法
US6310498B1 (en) * 1998-12-09 2001-10-30 Agere Systems Guardian Corp. Digital phase selection circuitry and method for reducing jitter
US6326826B1 (en) * 1999-05-27 2001-12-04 Silicon Image, Inc. Wide frequency-range delay-locked loop circuit
JP2001007698A (ja) * 1999-06-25 2001-01-12 Mitsubishi Electric Corp データｐｌｌ回路
JP3622685B2 (ja) * 2000-10-19 2005-02-23 セイコーエプソン株式会社 サンプリングクロック生成回路、データ転送制御装置及び電子機器
US6809567B1 (en) * 2001-04-09 2004-10-26 Silicon Image System and method for multiple-phase clock generation
US6690243B1 (en) * 2001-06-07 2004-02-10 Cypress Semiconductor Corp. Multi-phase voltage-controlled oscillator at modulated, operating frequency
TW525350B (en) * 2001-12-20 2003-03-21 Realtek Semiconductor Co Ltd Hybrid phase locked loop
US6794912B2 (en) 2002-02-18 2004-09-21 Matsushita Electric Industrial Co., Ltd. Multi-phase clock transmission circuit and method
KR100477808B1 (ko) * 2002-05-21 2005-03-21 주식회사 하이닉스반도체 듀티 사이클 교정이 가능한 디지털 디엘엘 장치 및 듀티사이클 교정 방법
JP4031671B2 (ja) * 2002-06-11 2008-01-09 松下電器産業株式会社 クロックリカバリ回路
KR100531469B1 (ko) * 2003-01-09 2005-11-28 주식회사 하이닉스반도체 지연고정 정보저장부를 구비한 아날로그 지연고정루프
JP4660076B2 (ja) * 2003-06-23 2011-03-30 ルネサスエレクトロニクス株式会社 クロック発生回路
US7319345B2 (en) 2004-05-18 2008-01-15 Rambus Inc. Wide-range multi-phase clock generator
TW200721688A (en) * 2005-11-25 2007-06-01 Realtek Semiconductor Corp Phase lock circuit

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JP2000357951A (ja) * 1999-06-15 2000-12-26 Mitsubishi Electric Corp 遅延回路、クロック生成回路及び位相同期回路

Also Published As

Publication number Publication date
US7821311B2 (en) 2010-10-26
JP2010093771A (ja) 2010-04-22
TWI488440B (zh) 2015-06-11
US20100090736A1 (en) 2010-04-15
TW201015864A (en) 2010-04-16
KR20100041197A (ko) 2010-04-22

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