JP2009182104A - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

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Publication number
JP2009182104A
JP2009182104A JP2008019005A JP2008019005A JP2009182104A JP 2009182104 A JP2009182104 A JP 2009182104A JP 2008019005 A JP2008019005 A JP 2008019005A JP 2008019005 A JP2008019005 A JP 2008019005A JP 2009182104 A JP2009182104 A JP 2009182104A
Authority
JP
Japan
Prior art keywords
external connection
wiring board
semiconductor
semiconductor package
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008019005A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009182104A5 (enExample
Inventor
Yasuo Takemoto
康男 竹本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2008019005A priority Critical patent/JP2009182104A/ja
Priority to US12/361,083 priority patent/US7968997B2/en
Publication of JP2009182104A publication Critical patent/JP2009182104A/ja
Publication of JP2009182104A5 publication Critical patent/JP2009182104A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2008019005A 2008-01-30 2008-01-30 半導体パッケージ Pending JP2009182104A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008019005A JP2009182104A (ja) 2008-01-30 2008-01-30 半導体パッケージ
US12/361,083 US7968997B2 (en) 2008-01-30 2009-01-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008019005A JP2009182104A (ja) 2008-01-30 2008-01-30 半導体パッケージ

Publications (2)

Publication Number Publication Date
JP2009182104A true JP2009182104A (ja) 2009-08-13
JP2009182104A5 JP2009182104A5 (enExample) 2011-02-03

Family

ID=40898306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008019005A Pending JP2009182104A (ja) 2008-01-30 2008-01-30 半導体パッケージ

Country Status (2)

Country Link
US (1) US7968997B2 (enExample)
JP (1) JP2009182104A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117083656A (zh) * 2021-03-26 2023-11-17 京瓷株式会社 显示装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2503594A1 (en) * 2011-03-21 2012-09-26 Dialog Semiconductor GmbH Signal routing optimized IC package ball/pad layout
JP6076068B2 (ja) * 2012-12-17 2017-02-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR102245132B1 (ko) 2014-05-14 2021-04-28 삼성전자 주식회사 트레이스를 가지는 인쇄회로기판 및 볼 그리드 어레이 패키지
EP3535571B1 (en) * 2016-11-07 2020-12-30 Dnae Diagnostics Limited Isfet array
CN113629031A (zh) * 2021-06-21 2021-11-09 江西万年芯微电子有限公司 一种tsop48l pin to pin lga48封装设计方法

Citations (8)

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JP2002368190A (ja) * 2001-04-06 2002-12-20 Hitachi Ltd 半導体装置およびその製造方法
JP2003051545A (ja) * 2001-08-03 2003-02-21 Mitsubishi Electric Corp 半導体メモリチップとそれを用いた半導体メモリ装置
JP2003234359A (ja) * 2002-02-08 2003-08-22 Hitachi Ltd 半導体装置の製造方法
JP2003297995A (ja) * 2002-03-21 2003-10-17 Texas Instr Inc <Ti> エッチングされたプロファイルを有する事前めっき済みの型抜きされた小外形無リードリードフレーム
JP2004165637A (ja) * 2002-10-21 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置
JP2006196734A (ja) * 2005-01-14 2006-07-27 Renesas Technology Corp 半導体装置及びその製造方法
JP2006278374A (ja) * 2005-03-28 2006-10-12 Sony Corp 半導体装置及びその実装構造
JP2006294976A (ja) * 2005-04-13 2006-10-26 Nec Electronics Corp 半導体装置およびその製造方法

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US3838317A (en) * 1973-07-12 1974-09-24 Bell Telephone Labor Inc Cross connect switch
EP0339154B1 (en) * 1988-04-26 1994-11-17 Citizen Watch Co. Ltd. Memory card
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US6515355B1 (en) * 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000082757A (ja) 1998-09-07 2000-03-21 Sony Corp 表面実装部品の外部端子構造
US6927491B1 (en) 1998-12-04 2005-08-09 Nec Corporation Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board
JP2001217355A (ja) * 1999-11-25 2001-08-10 Hitachi Ltd 半導体装置
JP2001177266A (ja) 1999-12-16 2001-06-29 Kato Electrical Mach Co Ltd 小型開閉装置
JP2002043503A (ja) * 2000-07-25 2002-02-08 Nec Kyushu Ltd 半導体装置
JP2002057242A (ja) 2000-08-07 2002-02-22 Canon Inc エリアアレイ型半導体パッケージ
JP4341187B2 (ja) * 2001-02-13 2009-10-07 日本電気株式会社 半導体装置
KR100416000B1 (ko) * 2001-07-11 2004-01-24 삼성전자주식회사 다수의 핀을 갖는 부품이 실장되는 인쇄회로기판
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JP4237160B2 (ja) * 2005-04-08 2009-03-11 エルピーダメモリ株式会社 積層型半導体装置
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JP2007103423A (ja) * 2005-09-30 2007-04-19 Renesas Technology Corp 半導体装置及びその製造方法
JP4740765B2 (ja) * 2006-02-24 2011-08-03 エルピーダメモリ株式会社 半導体装置及びその製造方法
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JP2002368190A (ja) * 2001-04-06 2002-12-20 Hitachi Ltd 半導体装置およびその製造方法
JP2003051545A (ja) * 2001-08-03 2003-02-21 Mitsubishi Electric Corp 半導体メモリチップとそれを用いた半導体メモリ装置
JP2003234359A (ja) * 2002-02-08 2003-08-22 Hitachi Ltd 半導体装置の製造方法
JP2003297995A (ja) * 2002-03-21 2003-10-17 Texas Instr Inc <Ti> エッチングされたプロファイルを有する事前めっき済みの型抜きされた小外形無リードリードフレーム
JP2004165637A (ja) * 2002-10-21 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置
JP2006196734A (ja) * 2005-01-14 2006-07-27 Renesas Technology Corp 半導体装置及びその製造方法
JP2006278374A (ja) * 2005-03-28 2006-10-12 Sony Corp 半導体装置及びその実装構造
JP2006294976A (ja) * 2005-04-13 2006-10-26 Nec Electronics Corp 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117083656A (zh) * 2021-03-26 2023-11-17 京瓷株式会社 显示装置

Also Published As

Publication number Publication date
US20090189158A1 (en) 2009-07-30
US7968997B2 (en) 2011-06-28

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