JP2009130266A - 半導体基板および半導体装置、半導体装置の製造方法 - Google Patents
半導体基板および半導体装置、半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】第1の不純物濃度を有する炭化珪素基板(1)と、前記炭化珪素基板上に形成され、第2の不純物濃度を有する第1の炭化珪素層(5)と、前記第1の炭化珪素層の上に形成され、第3の不純物濃度を有する第1導電型の第2の炭化珪素層(2)とを具備し、第2の不純物濃度>第1の不純物濃度>第3の不純物濃度の関係を有する。
【選択図】 図1
Description
図1及び図2は本発明の第1の実施形態に係る半導体装置(ショットキーバリア型ダイオード)の断面図であり、図1はSiC半導体基板上に半導体素子が形成された最終形態直前の状態、図2が半導体装置の最終形態を示す。図1の左端に添付されたグラフは、半導体基板(SiC基板及びSiC半導体層)の不純物濃度分布を示している。図中1はn+ 型SiCバルク基板、2はn-型SiCエピタキシャル成長層、3はアノード電極、4はカソード電極、5はn+型SiCバルク基板の主面近傍に形成されたn++型SiC超高濃度層、6はn++型SiC超高濃度層5とn-型SiCエピタキシャル成長層2の間に形成されたn型SiCバッファ層である。
前述の実施形態における超高濃度層5はエピタキシャル成長で形成したが、イオン注入で形成してもよい。以下、イオン注入で形成する方法について前述の図3を援用して説明する。
前述の実施形態における基板薄片化法として、研磨ではなく、反応性ドライエッチングにて加工を行ってもよい。ガス系はフッ化物系、たとえばSF6などのガスを用いて、高密度プラズマ中でSiCの裏面をエッチングすることにより、5分で約50μm程度の比較的高いレートにてSiC裏面を研磨することができる。またイオン性の反応のため、処理面のダメージを低減できる。その際の表面保護材料としてレジストなどの半導体プロセスに馴染んだ材料を使用することも可能である。レジストであれば剥離も簡易に行える。また研磨でのダメージ除去と薄膜化時間の効率を考えるならば、研磨である程度薄膜化したのちに反応性ドライエッチングにより研磨によってできた高抵抗成分となるダメージ層を取り除いてもよい。
図9は本発明の第2の実施の形態に係るpnダイオードの断面図である。図10はこのダイオードに使用する半導体基板の層構成を示す断面図であり、左端に構成層の濃度プロファイルを示す。理解が容易なように、第1の実施形態と同一部分には同一番号を付している。
図11は、本発明の第3の実施の形態に係る縦型MOSFETの要部断面図である。第1の実施形態のSiC基板1(不図示)の主面側に超高濃度n++型層5を設け、その上にn型バッファ層6を介してn-型ドリフト層2を形成している。n-型ドリフト層2の表面には選択的にオーミック接合となるソース電極3と、薄い酸化膜または高誘電体膜のゲート絶縁膜16を介してゲート電極17が形成されている。SiC基板1の研磨により露出したn++型超高濃度層5の裏面には、オーミック接合となるドレイン電極4が形成されている。
図13は本発明の第4の実施の形態に係るIGBTの要部断面図である。IGBTは第3の実施形態のMOSFETと形状が類似しているが、第2の実施形態の図10に示したような基板を用いる。
2…ドリフト層(エピタキシャル層)
3…第1の電極
4…第2の電極
5…n型超高濃度層
6…バッファ層、フィールドストップ層
7…リサーフ層
8…エッジターミネーション層
9…ガードリング
10…チャネルストッパ
11…メタルフィールドプレート
12…絶縁膜
13…テープ材
14…低抵抗基板
15…p型超高濃度層
16…ゲート絶縁膜
17…ゲート電極
18…p型領域
19…n+コンタクト
20…n-型領域
70…終端構造
Claims (10)
- 第1の不純物濃度を有する炭化珪素基板と、
前記炭化珪素基板上に形成され、第2の不純物濃度を有する第1の炭化珪素層と、
前記第1の炭化珪素層の上に形成され、第3の不純物濃度を有する第1導電型の第2の炭化珪素層と、
を具備し、第2の不純物濃度>第1の不純物濃度>第3の不純物濃度の関係を有することを特徴とする半導体基板。 - 前記第1の炭化珪素層が第1導電型であることを特徴とする請求項1に記載の半導体基板。
- 前記第1の炭化珪素層が第2導電型であることを特徴とする請求項1に記載の半導体基板。
- 前記第1の炭化珪素層が、厚さ50μm以下であることを特徴とする請求項1〜3のいずれかに記載の半導体基板。
- 厚さ50μm以下の第1導電型の第1の炭化珪素層と、
前記第1の炭化珪素層の上面に形成され、不純物濃度が前記第1の炭化珪素層より低い第1導電型の第2の炭化珪素層と、
前記第2の炭化珪素層の上面に形成され、前記第2の炭化珪素層とショットキー接合を形成する第1の電極と、
前記第1の炭化珪素層の下面に形成された第2の電極と、
を具備することを特徴とする半導体装置。 - 厚さ50μm以下の第1導電型の第1の炭化珪素層と、
前記第1の炭化珪素層上に形成され、不純物濃度が前記第1の炭化珪素層より低い第2導電型の第2の炭化珪素層と、
前記第2の炭化珪素層の上面に形成された第1の電極と、
前記第1の炭化珪素層の下面に形成された第2の電極と、
を具備することを特徴とする半導体装置。 - 厚さ50μm以下の第1の炭化珪素層と、
前記第1の炭化珪素層上に形成され、不純物濃度が前記第1の炭化珪素層より低い第1導電型の第2の炭化珪素層と、
前記第2の炭化珪素層上に選択的に設けられた第2導電型の第1の炭化珪素領域と、
前記第1の炭化珪素領域の内部表面に形成される、第1導電型の第2の炭化珪素領域と、
前記第2の炭化珪素層の表面から、前記第1の炭化珪素領域を介して前記第2の炭化珪素領域の表面に連続的に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記第1及び第2の炭化珪素領域上に形成された第1の主電極と、
前記第1の炭化珪素層の下面に形成された第2の主電極と、
を具備することを特徴とする半導体装置。 - 前記第1の炭化珪素層が第1導電型であることを特徴とする請求項7に記載の半導体装置。
- 前記第1の炭化珪素層が第2導電型であることを特徴とする請求項7に記載の半導体装置。
- 請求項1に記載の半導体基板を用意し、前記半導体基板の上面に半導体素子を形成する工程と、
前記半導体素子を形成後、前記半導体基板の裏面を研磨して、前記第1の炭化珪素層を露出させる工程と、
前記露出させた前記炭化珪素層に電極を形成する工程と、
と具備することを特徴とする半導体装置の製造方法。
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