CN106356286B - 包括氧扩散阻挡的半导体器件及制造方法 - Google Patents
包括氧扩散阻挡的半导体器件及制造方法 Download PDFInfo
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- CN106356286B CN106356286B CN201610561974.6A CN201610561974A CN106356286B CN 106356286 B CN106356286 B CN 106356286B CN 201610561974 A CN201610561974 A CN 201610561974A CN 106356286 B CN106356286 B CN 106356286B
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- Recrystallisation Techniques (AREA)
Abstract
本公开涉及包括氧扩散阻挡的半导体器件及制造方法。具体地,制造半导体我器件的方法的实施例包括:在直拉或磁性直拉硅衬底的第一表面上形成氧扩散阻挡。硅层形成在氧扩散阻挡上。在硅层中形成p掺杂和n掺杂半导体器件区域。该方法还包括形成第一和第二负载终端接触件。
Description
技术领域
本公开总体上涉及半导体领域,更具体地涉及包括氧扩散阻挡的半导体器件及制造方法。
背景技术
在半导体功率器件中,例如半导体二极管、绝缘栅型场效应晶体管(IGFET)、绝缘栅型双极晶体管(IGBT)、晶闸管、双极结晶体管(BJT)电压阻挡要求通常通过结合到轻掺杂漂移或基极区域中的氧来满足,例如由于含氧半导体衬底外的扩散可用作热施主并引起漂移或基极区中掺杂浓度或者场阑区(field stop zone)中不期望的波动。此外,会不利地影响漂移或基极区中的自由载体的寿命。
期望减小半导体器件中的掺杂浓度的波动,并且提供对应的制造方法。
发明内容
本公开涉及制造半导体器件的方法。该方法包括:在直拉(Czochralski)或者磁性(也成为“磁控”)直拉硅衬底的第一表面上形成氧扩散阻挡;以及在氧扩散阻挡上形成硅层。该方法还包括:在硅层中形成掺杂半导体器件区域;以及形成第一和第二负载终端接触件。
本公开还涉及一种半导体器件。该半导体器件包括半导体本体,其包括相对的第一和第二表面。该半导体器件还包括位于半导体本体中的漂移或基极区以及位于半导体本体中的氧扩散阻挡。漂移或基极区位于第一表面和氧扩散阻挡之间并且直接邻接氧扩散阻挡。半导体器件还包括第一和第二负载终端接触件,其中,第一和第二负载终端接触件中的至少一个接触件通过第一表面电连接至半导体本体。
本领域技术人员在阅读以下详细描述以及查看附图之后将意识到附加的特征和优势。
附图说明
包括附图以提供对本发明的进一步理解并且结合并组成被说明书的一部分。附图示出了本发明的实施例,并且与说明书一起用于解释本发明的原理。本发明的其他实施例和预期优势将通过参照以下详细描述而变得更容易理解。
图1是用于示出制造半导体器件的方法的示意性流程图。
图2A至图2C是用于示出制造半导体器件的方法工艺的直拉或磁性直拉硅衬底的示意性截面图。
图3是包括氧扩散阻挡的半导体器件的实施例的示意性截面图。
图4是包括氧扩散阻挡的功率半导体二极管的实施例的示意性截面图。
图5是包括氧扩散阻挡的IGBT的实施例的示意性截面图。
图6是包括氧扩散阻挡的沟槽栅极IGFET的实施例的示意性截面图。
图7是包括氧扩散阻挡的半导体器件的另一实施例的示意性截面图。
图8是包括氧扩散阻挡的功率半导体二极管的另一实施例的示意性截面图。
图9是包括氧扩散阻挡的IGBT的另一实施例的示意性截面图。
图10是包括氧扩散阻挡的沟槽栅极IGFET的另一实施例的示意性截面图。
具体实施方式
在以下详细描述中,参照形成说明书的一部分并且通过可实践本公开的说明性具体实施例的附图。应该理解,在不背离本发明的范围的情况下可以使用其他实施例并且可以进行结构或逻辑改变。例如,针对一个实施例示出或描述的特征可用于其他实施例或结合其他实施例使用以产生又一实施例。本公开包括这些修改和变化。使用具体语言描述的示例不应限制所附权利要求的范围。附图不按比例绘制并且仅用于说明的目的。为了清楚,如果不另外指定,则在不同附图中通过对应的参考标号来表示相同的元件。
术语“具有”、“包含”、“包括”等是开放性术语,表示所提结构、元件或特征的存在,但是不排除附加元件或特征的存在。冠词“一个”和“该”用于包括多个以及单个,除非另有明确指定。
术语“电连接”描述电连接元件之间的永久低欧姆连接,例如所提元件之间的直接接触或者经由金属和/或重掺杂半导体的低欧姆连接。术语“电耦合”包括用于信号传输的一个或多个中间元件可存在于电耦合元件之间,例如在第一状态下临时提供低欧姆连接以及在第二状态下提供高欧姆电去耦的元件。
附图通过掺杂类型“n”或“p”相邻的符号“-”或“+”示出相对掺杂浓度。例如,“n-”表示掺杂浓度低于“n”掺杂区域的掺杂浓度,而“n+”区域的掺杂浓度高于“n”掺杂区域。相同的相对掺杂浓度的掺杂区域不是必须具有相同的绝对掺杂浓度。例如,两个不同的“n”掺杂区域可具有相同或不同的绝对掺杂浓度。
以下说明书中的使用的术语“晶圆”、“衬底”、“半导体本体”或“半导体衬底”可包括具有半导体表面的任何基于半导体的结构。晶圆和结构被理解为包括硅(Si)、绝缘体上硅(SOI)、蓝宝石上硅(SOS)、掺杂和非掺杂半导体、由基础半导体结构支持的硅的外延层和其他半导体结构。半导体不需要为基于硅的。半导体还可以为硅锗(SiGe)、锗(Ge)或砷化镓(GaAs)。根据其他实施例,碳化硅(SiC)或氮化镓(GaN)可形成半导体衬底材料。
本说明书中使用的术语“水平”用于描述基本平行于半导体衬底或本体的第一表面或主面的定向。这例如可以是晶圆或半导体裸片的表面。
说明书中使用的术语“垂直”用于描述基本被布置为与第一表面垂直,即,平行于半导体衬底或本体的第一表面的法线方向的定向。
在本说明书中,半导体衬底或半导体本体的第二表面被认为是由半导体衬底的下表面或背侧或后表面形成,而第一表面由半导体衬底的上表面、前表面或主表面形成。因此,说明书中使用的术语“之上”和“之下”描述了结构特征与另一个结构特征的相对位置。
在本说明书中,实施例被示为包括p和n掺杂半导体区域。可选地,半导体器件可形成为具有相对的掺杂关系,使得所示p掺杂区域是n掺杂的,且所示的n掺杂区域是p掺杂的。
半导体器件可具有终端接触件,诸如接触焊盘(或电极),其允许与包括在半导体本体中的集成电路或分立半导体器件进行电接触。电极可包括一个或多个电极金属层,它们被应用于半导体芯片的半导体材料。电极金属层可制造为任何期望的几何形状和任何期望的材料组成。电极金属层例如可以为覆盖区域的层的形式。任何期望的金属(例如,Cu、Ni、Sn、Au、Ag、Pt、Pd、Al、Ti)和这些金属的一种或多种的合金可用作材料。电极金属层不需要是同质的,或者仅通过一种材料制造,即,包含在电极金属层中的材料的各种组成和浓度都是可以的。作为示例,电极层的尺寸可以足够大以与线接合。
在本文描述的实施例中,应用一个或多个传导层(具体为导电层)。应该理解,“形成”或“施加”的任何这种术语如字面含义地表面覆盖应用层的所有种类和技术。具体地,表示覆盖一次整体应用层的技术,例如层压技术以及以顺序方式沉积层的技术,例如溅射、镀、模制、CVD(化学气相沉积)、物理气相沉积(PVD)、蒸发、混合物理-化学气相沉积(HPCVD)等。
具体地,所应用的导电层可以包括尤其一个或多个金属层(诸如Al、Cu或Sn或者其合金)、导电膏层和接合材料层。金属层可以是同质层。导电膏可以包括分布在可蒸发或可固化聚合材料中的金属粒子,其中膏可以是流体、粘性液体或蜡制体。可以应用接合材料以电和机械地连接半导体芯片至例如载体或例如至接触夹。可以使用能够形成扩散焊料接合的软焊料材料(或者具体为焊料材料),例如包括Sn、SnAg、SnAu、SnCu、In、InAg、InCu和InAu中的一种或多种的焊料材料。
切割工艺可用于将晶圆划分为对应芯片。可以应用用于切割的任何技术,例如刀片切割(锯切)、激光切割、蚀刻等。半导体本体(例如,半导体晶圆)可通过以下处理来切割:在带(具体为切割带)上放置半导体晶圆,例如根据一种或多种上述技术向半导体晶圆应用切割图案(具体为矩形图案),以及例如沿着带平面中的四个正交方向都拉动带。通过拉动带,半导体晶圆被分为多个半导体裸片(芯片)。
图1是用于说明制造半导体器件的方法100的示意性流程图。
应该理解,虽然方法100在以下被示出和描述为一系列动作或事件,这些动作或事件的所述顺序不是限制性的。例如,除了本文示出和/或描述的之外,一些动作可以以不同顺序发生和/或与其他动作或事件同时发生。此外,不是所有所示动作都要求实施本公开的实施例的一个或多个方面。此外,本文所述的一个或多个动作可在一个或多个独立的动作和/或阶段中执行。
处理步骤S100包括在直拉(CZ)或磁性直拉(MCZ)硅衬底的第一表面上形成氧扩散阻挡。在一些实施例中,氧扩散阻挡中的氧的扩散系数比室温下硅中的氧的扩散系数小至少3倍(即,氧扩散阻挡中的氧的扩散系数至多是室温下硅中的氧的扩散系数的1/3),或者小至少5倍或者小至少10倍。例如,扩散系数取决于SiGe阻挡层的Ge浓度和厚度。这两个参数的大小还取决于器件的工作流路由(workflow route)以实现无缺陷的半导体层。氧扩散阻挡可以连续地覆盖直拉或磁性直拉硅衬底的第一表面。
工艺步骤S110包括在氧扩散阻挡上形成硅层。在一些实施例中,硅层通过外延生长或沉积来形成,例如通过化学气相沉积来形成,诸如大气压CVD(APCVD)、亚大气压CVD(SACVD)或低压CVD(LPCVD)。
工艺步骤S120包括在硅层中形成掺杂半导体器件区域。在一些实施例中,IGFET的源极、本体和逻辑区域通过离子注入和/或掺杂物扩散到硅层和/或直拉或磁性直拉硅衬底中形成。在一些其他实施例中,IGBT发射极的源极和本体区域以及IGBT集电极的双极注入区域通过离子注入和/或掺杂物扩散到硅层和/或直拉或磁性直拉硅衬底中形成。在一些其他实施例中,功率pn结二极管的阳极和阴极区域通过离子注入和/或掺杂物扩散到硅层和/或直拉或磁性直拉硅衬底中形成。可以形成附加功能半导体区域(诸如重掺杂接触区域),用于向负载终端接触件、缓冲区域或场阑区域提供欧姆接触。
工艺步骤S130包括形成第一和第二负载终端接触件。在一些实施例中,第一和第二负载终端接触件是IGFET的源极和漏极接触件。在一些其他实施例中,第一和第二负载终端接触件是半导体功率二极管的阳极和阴极接触件。在一些其他实施例中,第一和第二负载终端接触件是IGBT或BJT的集电极和发射极接触件。
在一些实施例中,形成氧扩散阻挡的工艺包括形成SiGe扩散阻挡。SiGe扩散阻挡中的最大Ge含量可以设置为1%和40%之间的值,或者2%和20%之间的值。
在一些实施例中,SiGe阻挡的厚度被设置为0.2μm和2μm之间的值,或者0.5μm和1.5μm之间的值。层的可行厚度还取决于Ge浓度和以下器件制造的热预算,以确保无缺陷的半导体层。SiGe扩散阻挡的厚度可以设置得小于所谓的临界厚度(其是SiGe扩散阻挡的最大厚度,用于允许无缺陷的外延生长)。例如,临界厚度可以取决于SiGe扩散阻挡中的Ge含量以及SiGe扩散阻挡的生长期间的温度。
在一些实施例中,SiGe扩散阻挡中的Ge含量被设置为从直拉或磁性直拉硅沉积的表面开始沿着垂直于该表面的方向连续增加或者阶梯式增加。例如,这可以通过流动到CVD室中的CVD Ge前体气体流(例如,锗烷(GeH4)气体流)的连续或阶梯式增加来实现。
在一些实施例中,SiGe扩散阻挡被形成为包括SiGe和Si层的超晶格。超晶格的每一层的厚度可以选择低于开始晶格缺陷生长的临界值。
在一些实施例中,碳被添加至SiGe扩散阻挡。
在一些实施例中,硅层的厚度被设置为40μm和200μm之间的值。例如,该值可以取决于半导体器件的电压阻挡要求。
在一些实施例中,从直拉或磁性直拉硅衬底的与第一表面相对的第二表面去除直拉或磁性直拉硅衬底的材料。通过化学和/或机械工艺来去除材料,例如通过蚀刻和/或研磨。在一些实施例中,直拉或磁性直拉硅衬底被完全去除。氧扩散阻挡可用作蚀刻停止或掩模停止层。通过示例,当达到氧扩散阻挡时,蚀刻和/或研磨期间的特性可以改变。例如,通过检测特性的变化,可以停止蚀刻和/或研磨。
在一些实施例中,与氢有关的施主形成在硅层和/或直拉或磁性直拉硅衬底中,例如通过用质子照射硅层和/或直拉或磁性直拉硅衬底的工艺。根据实施例,质子照射在一百或几百keV至5MeV的能量范围,或者从200keV至4MeV或者从300keV至1.5MeV的能量范围内执行。根据另一实施例,多个质子照射(例如,两个、三个、四个或五个质子照射)以不同的能量执行,例如500keV之下到大于1MeV。例如,不同能量下的多个质子照射允许制造包括多个掺杂峰值的场阑区。根据实施例,质子照射在0.5x 1013质子/cm2至5x 1014质子/cm2的剂量范围下执行。根据另一实施例,在不同的剂量下执行多个质子照射,例如两个、三个、四个或五个质子照射。多个质子照射的所有照射剂量的总和的范围可以为几1013质子/cm2至几十1014质子/cm2,例如2x1013质子/cm2从至8x 1014质子/cm2。此外,不同照射剂量和能量的组合可用于实现场阑区的期望轮廓。
可以在300℃至550℃的温度范围下,或者在350℃至430℃之间或者380℃和420℃之间的温度下退火硅层和/或直拉或磁性直拉硅衬底。退火工艺可以在热处理系统中执行,例如在熔炉和/或快速热处理(RTP)系统中。例如,硅层和/或直拉或磁性直拉硅衬底可以通过热处理系统中的保持装置来支持。根据一个实施例,退火被执行30分钟至四个小时的持续时间。
质子照射和退火导致通过氢支持热施主形成(诸如氢相关浅施主复合物,例如氢空位施主复合物)的掺杂。
在一些实施例中,形成控制终端接触件,例如栅电极或栅电极接触件或基极接触件。
在一些实施例中,半导体器件形成为功率半导体二极管、功率绝缘栅型双极晶体管、功率双极结晶体管、功率晶闸管和功率绝缘栅型场效应晶体管中的一个器件。半导体器件可形成为垂直功率半导体器件。第一负载终端接触件可形成在包括硅层的半导体本体的第一表面处。第二负载终端接触件可形成为半导体本体与第一表面相对的第二表面处。边缘终端结构可形成在半导体本体的第一表面处,环绕边缘终端区域中的半导体器件的有源区域。边缘终端区域目的在于将电击穿偏移到有源区域中,用于避免由于边缘终端中可由该区域中的等势线的曲率引起的不期望的电击穿所引起的阻挡电压的劣化。例如,边缘终端区域中的结终端结构的典型结构元件包括一个或多个场板、环结构(诸如浮置保护环或环部分)、结终端延伸(JTE)结构和横向掺杂变化(VLD)结构。
通过避免或阻碍氧从衬底(诸如直拉或磁性直拉硅衬底,氧结合于其中)扩散到硅层中,设置氧扩散阻挡允许减小硅层或者硅层中的又一半导体区域(例如,场阑区)中的掺杂浓度的波动。
图2A至图2C是用于示出制造半导体器件的方法工艺的直拉或磁性直拉硅衬底105的示意性截面图。
在图2A的示意性截面图中,氧扩散阻挡107形成在直拉或磁性直拉硅衬底105的第一表面108上。第一表面108与第二表面109相对。氧扩散阻挡可以连续地覆盖直拉或磁性直拉硅衬底105的第一表面108。
紧接在截面图之后示出氧扩散阻挡107的示例。
氧扩散阻挡107通过SiGe扩散阻挡1070来例示。SiGe扩散阻挡1070中的最大Ge含量可以设置为1%和40%之间的值,或者2%和20%之间的值。在一些实施例中,SiGe扩散层1070的厚度被设置为0.2μm和2μm之间的值,或者0.5μm和1.5μm之间的值。层内的可行Ge浓度及其厚度还取决于器件制造的以下热预算以确保无缺陷的半导体层。SiGe扩散阻挡1070的厚度可以设置为小于所谓的临界厚度,其中该临界厚度是SiGe扩散阻挡的允许无缺陷外延生长的最大厚度。例如,临界厚度可以取决于SiGe扩散阻挡1070中的Ge含量以及SiGe扩散阻挡1070生长期间的温度。
曲线c1示出了SiGe扩散阻挡1070中的Ge含量沿着穿过SiGe扩散阻挡1070的垂直方向是横向或基本恒定的一个实施例。Ge含量轮廓类似于曲线c1的SiGe扩散阻挡可以例如通过保持进入CVD室的CVD Si或Ge前体气体的恒定或基本恒定的流动来制造。
曲线c2、c3、c4示出了SiGe扩散阻挡1070中的Ge含量的不同实施例,其从直拉或磁性直拉硅衬底105的第一表面108开始并沿着垂直于第一表面108的方向连续增加。Ge含量轮廓类似于曲线c2、c3、c4的SiGe扩散阻挡可以例如通过相对于进入CVD室的CVD Si前体气体流连续增加CVD Ge前体气体流来制造。例如,SiGe扩散阻挡1070中的Ge含量的增加可以是线性的(曲线c2)、凸起的(曲线c3)或凹陷的(曲线c4)。
曲线c5示出了SiGe扩散阻挡1070中的Ge含量沿着通过SiGe扩散阻挡1070的垂直方向从直拉或磁性直拉硅衬底105的第一表面108开始并沿着垂直于第一表面108的方向阶梯式增加的一个实施例。Ge含量轮廓类似于曲线c5的SiGe扩散阻挡可以例如通过相对于进入CVD室的CVD Si前体气体阶梯式增加CVD Ge前体气体的流动来制造。
氧扩散阻挡107还通过包括Si和SiGe层1072、1073的超晶格1071来例示。超晶格1071的每一层的厚度可以选择为低于开始晶体缺陷生成的临界值。每个SiGe层1073中的Ge含量可以保持恒定或基本恒定(参见曲线c6),或者可以从直拉或磁性直拉硅衬底105的第一表面108开始并沿着垂直于第一表面108的方向增加(参见曲线c7)。例如,SiGe层1073中的最大Ge含量也可以在每个SiGe层1073中随着与第一表面108的距离的增加而增加。超晶格可以以Si层1072/SiGe层1073的序列或者以SiGe层1073/SiGe层1072的序列从第一表面108生长。超晶格1071中的SiGe/Si单元的数量可以变化,例如一个、两个、三个、四个、五个,甚至更多。
曲线c8、c9、c10示出了SiGe扩散阻挡1070中的Ge含量从直拉或磁性直拉硅衬底105的第一表面108开始并沿着垂直于第一表面108的方向x连续减小的不同实施例。Ge含量轮廓类似于曲线c8、c9、c10的SiGe扩散阻挡可以例如通过相对于进入CVD室的CVD Si前体气体流连续减小CVD Ge前体气体流来制造。例如,SiGe扩散阻挡1070中的Ge含量的减小可以是线性的(曲线c8)、凸起的(曲线c9)或凹陷的(曲线c10)。
曲线c11示出了SiGe扩散阻挡1070中的Ge含量沿着通过SiGe扩散阻挡1070的垂直方向从直拉或磁性直拉硅衬底105的第一表面108开始并沿着垂直于第一表面108的方向x阶梯式减小的实施例。Ge含量轮廓类似于曲线c11的SiGe扩散阻挡可以例如通过相对于进入CVD室的CVD Si前体气体阶梯式减小CVD Ge前体气体的流动来制造。
曲线c12、c13、c14示出了SiGe扩散阻挡1070中的Ge含量沿着通过SiGe扩散阻挡1070的垂直方向朝向半导体本体的第一表面在第一部分中连续或阶梯式增加、在第二部分中恒定且在第三部分中连续或阶梯式减小的实施例。连续增加和/或减小可以是线性的(曲线c12)、凸起的(曲线c13)、凹陷的(曲线c14)或阶梯式的(曲线c15)。
超晶格1071的SiGe/Si单元中的Ge含量的轮廓还可以调整为凸起、凹陷、线性或阶梯式增加和/或减小Ge轮廓(包括任选的稳定阶段)。
在图2B的示意性截面图中,硅层110形成在氧扩散阻挡107上。在一些实施例中,硅层110通过外延生长或沉积来形成,例如通过化学气相沉积,诸如大气压CVD(APCVD)、亚大气压CVD(SACVD)或低压CVD(LPCVD)。
硅层110的厚度可以设置为40μm和200μm之间的值。例如,该值可以取决于半导体器件的电压阻挡要求。
在一些实施例中,从第二表面109去除直拉或磁性直拉硅衬底105的材料,参见图2C的示意性截面图。可以通过化学和/或机械工艺来去除材料,例如通过蚀刻和/或研磨。在一些实施例中,直拉或磁性直拉硅衬底105被完全去除。氧扩散阻挡可用作蚀刻停止或研磨停止层。通过示例,当到达氧扩散阻挡时,可以改变蚀刻和/或研磨期间的特性。例如,通过检测到特性的变化,可以停止蚀刻和/或研磨。
在图2B或图2C之后,可以通过包括硅层110和直拉或磁性直拉硅衬底105的剩余部分的半导体本体的一个或两个相对表面执行任选的质子照射和退火。这导致氢支持热施主形成的掺杂,诸如氢相关浅施主复合物,例如氢空位施主复合物。从而,例如可以形成一个或多个场阑区。
然后,在硅层110中形成掺杂半导体器件区域。在一些实施例中,通过离子注入和/或掺杂物扩散到硅层和/或直拉或磁性直拉硅衬底中来形成IGFET的源极、本体和漏极区域。在一些其他实施例中,通过离子注入和/或掺杂物扩散到硅层和/或直拉或磁性直拉硅衬底中来形成IGBT发射极的源极和本体区域以及IGBT集电极处的双极注入区域。在一些其他实施例中,通过离子注入和/或掺杂物扩散到硅层和/或直拉或磁性直拉硅衬底中来形成pn结二极管的阳极和阴极区域。可以形成附加功能半导体区域,诸如重掺杂接触区域,用于提供针对负载终端接触件、重掺杂载体注入区域、缓冲区域或场阑区的欧姆接触。此外,形成第一和第二负载终端接触件。在一些实施例中,第一和第二负载终端接触件是IGFET的源极和漏极接触件。在一些其他实施例中,第一和第二负载终端接触件是半导体功率二极管或功率二极管的阳极和阴极接触件。在一些其他实施例中,第一和第二负载终端接触件是IGBT或BJT的集电极和发射极接触件。
硅层110和直拉或磁性直拉硅衬底105的处理形成如图3的示意图所示的半导体器件。
该半导体器件包括半导体本体112,其包括相对的第一和第二表面113、114。作为图2A至图2C的硅层110的一部分并对应于图2A至图2C的硅层110的漂移或基区1100位于第一表面113和氧扩散阻挡107之间并且直接邻接氧扩散阻挡107。
该半导体器件还包括用于垂直功率半导体器件的位于半导体本体112的第一表面113处的第一负载终端接触件L1和位于半导体本体112的第二表面114处的第二负载终端接触件L21。可选地,对于横向半导体器件,第二负载终端接触件L22位于半导体本体112的第一表面113处。
当半导体器件形成为功率绝缘栅型双极晶体管、功率双极结晶体管、功率硅控整流器和功率绝缘栅型场效应晶体管的一个器件时,控制端接触件C位于半导体本体112的第一表面113处。当半导体器件形成为功率半导体二极管半导体器件时,缺少负载控制终端接触件C。考虑可集成到半导体层和/或直拉或磁性直拉硅衬底105中的具体半导体器件的大量变化,为了清楚的目的在图3中缺少功能半导体区域的示出。参照图4至图6示出和描述具有图3的基础设计的具体半导体器件的一些实施例。
在图4的示意性截面图400中,图3的半导体器件被示为功率半导体二极管,其包括p掺杂阳极区域120和任选的p掺杂结终端延伸(JTE)121(其在功率半导体二极管的边缘区域中环绕p掺杂阳极区域120)。作为可选或者除JTE 121之外,可以形成其他边缘终端结构,例如场板和/或环结构。p掺杂阳极区域120电连接至第一负载终端接触件L1。功率半导体二极管还包括位于第二表面114处的n+掺杂阴极接触区域122,其电连接至第二表面114处的第二负载终端接触件L21。
在图5的示意性截面图500中,图3的半导体器件被示为IGBT,其包括p掺杂本体区域130、p+掺杂本体接触区域131和n+掺杂源极区域132。栅极介电层133将栅电极134与漂移或基区1100电隔离。栅电极134电连接至控制终端接触件C。在一些实施例中,栅电极134对应于控制终端接触件C。第一负载终端接触件L1,例如发射极终端接触件电连接至p掺杂本体区域130和n+掺杂源极区域132。第二表面114处的p+掺杂双极注入区域135电连接至第二负载终端接触件L21,例如集电极终端接触件。
在上述半导体器件的实施例中,直拉或磁性直拉硅衬底105可以被部分或完全去除(例如,参见图2C)。
在其他实施例中,图5所示的平面栅极结构还可以被沟槽栅极结构代替。
在图6的示意性截面图600中,图3的半导体器件被示为沟槽栅极IGFET,其包括p掺杂本体区域150、p+掺杂本体接触区域151和n+掺杂源极区域152。沟槽156中的栅极介电层153将栅电极154与漂移或基区1100电隔离。栅电极154电连接至控制终端接触件C。在一些实施例中,栅电极154对应于控制终端接触件C。第一负载终端接触件L1,例如源极终端接触件电连接至p掺杂本体区域150和n+掺杂源极区域152。第二表面114处的n+掺杂漏极接触区域155电连接至第二负载终端接触件L21,例如漏极终端接触件。
直拉或磁性直拉硅衬底105可以被部分或完全去除(例如,参见图2C)。
半导体器件的实施例在图3的示意图中示出,并且还包括在图7的示意性截面图700中示出的完全去除的硅衬底105。第二负载终端接触件L21在半导体本体112的第二表面114处,用于直接邻接氧扩散阻挡107的垂直功率半导体器件。
功率半导体二极管的实施例在图4的示意图400中示出,并且还包括在图8的示意性截面图800中示出的完全去除的硅衬底105。第二负载终端接触件L21位于直接邻接氧扩散阻挡107的半导体本体112的第二表面114处。氧扩散阻挡107用作功率半导体二极管的n+掺杂阴极接触区域122,并且还可以是重掺杂的。
IGBT的实施例在图5的示意性截面图500中示出,并且还包括在图9的示意性截面图900中示出的完全去除的硅衬底105。第二负载终端接触件L21位于半导体本体112的第二表面114处,与氧扩散阻挡107直接邻接。氧扩散阻挡107用作IGBT的p+掺杂双极注入区域135,并且还可以是重掺杂的。
沟槽栅极IGFET的实施例在图6的示意图600中示出,并且还包括在图10的示意性截面图1000中示出的完全去除的硅衬底105。第二负载终端接触件L21位于半导体本体112的第二表面114处,与氧扩散阻挡107直接邻接。氧扩散阻挡107用作沟槽栅极IGFET的n+掺杂漏极接触区域155并且还可以是重掺杂的。
氧扩散阻挡107可以包括5x 1016cm-3和1x 1018cm-3、或8x1016cm-3和8x 1017cm-3或1x 1017cm-3和5x 1017cm-3的范围中的氧浓度。氧浓度可以基于氧基的复合物,例如B-O复合物、P-O复合物或V-O复合物。较大的氧浓度允许减小载体寿命,因此减少发射极注入效率同时由于重掺杂保持良好的接触特性。从而,可以通过增加掺杂提高接触特性而不经受过量的载体注入效率。
氧扩散阻挡107可以是n掺杂二极管发射极区域、n掺杂漏极区域和p掺杂发射极区域中的一个。
IGFET还可以形成为超结IGFET,用于实现具体的导通阻抗与击穿电压之间的最佳折中。例如,n掺杂漂移区的充电补偿可以通过布置在n掺杂漂移区部分之间的p掺杂充电补偿区域或者通过布置在n掺杂漂移区部分之间的场电极和通过场介电质与n掺杂漂移区部分电隔离的场电极来实现。一个或多个场电极可以布置在栅电极154下方的沟槽156中,例如通过将沟槽进一步延伸到漂移或基区1100中。
尽管本文示出和描述了具体实施例,但本领域技术人员可以理解,在不背离本发明的范围的情况下,可以针对示出和描述的具体实施例进行各种改变和/或等效实施。本申请用于覆盖本文讨论的具体实施例的任何修改或变化。因此,仅通过权利要求及其等效物来限制本发明。
Claims (31)
1.一种制造半导体器件的方法,所述方法包括:
在直拉硅衬底的第一表面上形成氧扩散阻挡;
在所述氧扩散阻挡上形成硅层;
在所述硅层中形成p掺杂半导体器件区域和n掺杂半导体器件区域;以及
形成第一负载终端接触件和第二负载终端接触件,
其中所述氧扩散阻挡中的氧浓度在5 x 1016cm-3和1 x 1018cm-3的范围内。
2.根据权利要求1所述的方法,其中形成所述氧扩散阻挡包括形成SiGe扩散阻挡。
3.根据权利要求2所述的方法,其中所述SiGe扩散阻挡中的最大Ge含量被设置为1%和40%之间的值。
4.根据权利要求2所述的方法,其中所述SiGe扩散阻挡的厚度被设置为0.2μm和2μm之间的值。
5.根据权利要求2所述的方法,其中所述SiGe扩散阻挡中的Ge含量被设置为从所述直拉硅衬底的一表面开始沿着垂直于该表面的方向连续或阶梯式增加。
6.根据权利要求2所述的方法,其中所述SiGe扩散阻挡中的Ge含量被设置为从所述直拉硅衬底的一表面开始沿着垂直于该表面的方向连续或阶梯式减小。
7.根据权利要求2所述的方法,其中所述SiGe扩散阻挡中的Ge含量被设置为:从所述直拉硅衬底的一表面开始沿着垂直于该表面的方向,在第一部分中连续或阶梯式增加、在第二部分中恒定以及在第三部分中连续或阶梯式减小。
8.根据权利要求2所述的方法,其中所述SiGe扩散阻挡形成为包括SiGe层和Si层的超晶格。
9.根据权利要求2所述的方法,还包括:向所述SiGe扩散阻挡中添加碳。
10.根据权利要求2所述的方法,其中所述硅层的厚度被设置为40μm和200μm之间的值。
11.根据权利要求1所述的方法,还包括:从所述直拉硅衬底的与所述第一表面相对的第二表面去除所述直拉硅衬底的材料。
12.根据权利要求11所述的方法,其中所述直拉硅衬底被完全去除。
13.根据权利要求1所述的方法,还包括:在所述硅层和所述直拉硅衬底的至少一个中形成氢相关施主。
14.根据权利要求1所述的方法,还包括:形成控制终端接触件。
15.根据权利要求1所述的方法,还包括:形成所述半导体器件作为功率半导体二极管、功率绝缘栅型双极晶体管、功率双极结晶体管、功率硅控整流器和功率绝缘栅型场效应晶体管中的一个器件。
16.根据权利要求1所述的方法,还包括:形成所述半导体器件作为垂直功率半导体器件,在包括所述硅层的半导体本体的第一表面处形成所述第一负载终端接触件以及在所述半导体本体的与所述第一表面相对的第二表面处形成所述第二负载终端接触件,并且还包括:在所述半导体本体的所述第一表面处形成环绕所述半导体器件的有源区域的边缘终端结构。
17.一种半导体器件,包括:
半导体本体,包括相对的第一表面和第二表面;
漂移区或基区,位于所述半导体本体中;
氧扩散阻挡,位于所述半导体本体中,其中所述漂移区或所述基区位于所述第一表面与所述氧扩散阻挡之间并且直接邻接所述氧扩散阻挡,并且所述氧扩散阻挡上形成有硅层;以及
第一负载终端接触件和第二负载终端接触件,其中所述第一负载终端接触件和所述第二负载终端接触件中的至少一个接触件通过所述第一表面电连接至所述半导体本体,
其中所述氧扩散阻挡中的氧浓度在5 x 1016cm-3和1 x 1018cm-3的范围内。
18.根据权利要求17所述的半导体器件,其中所述半导体本体还包括位于所述半导体本体的第二表面与所述氧扩散阻挡之间的直拉硅衬底。
19.根据权利要求17所述的半导体器件,其中所述氧扩散阻挡包括SiGe扩散阻挡。
20.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡中的最大Ge含量在1%和40%的范围内。
21.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡的厚度在0.2μm和2μm的范围内。
22.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡中的Ge含量朝向所述半导体本体的所述第一表面连续或阶梯式增加。
23.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡中的Ge含量朝向所述半导体本体的所述第一表面连续或阶梯式减小。
24.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡中的Ge含量朝向所述半导体本体的所述第一表面在第一部分中连续或阶梯式增加、在第二部分中恒定以及在第三部分中连续或阶梯式减小。
25.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡是包括SiGe层和Si层的超晶格。
26.根据权利要求19所述的半导体器件,其中所述SiGe扩散阻挡中还包括碳。
27.根据权利要求17所述的半导体器件,其中所述硅层的厚度被设置为40μm和200μm之间的值。
28.根据权利要求17所述的半导体器件,其中所述半导体器件是功率半导体二极管、功率绝缘栅型双极晶体管、功率双极结晶体管、功率硅控整流器和功率绝缘栅型场效应晶体管中的一个器件。
29.根据权利要求28所述的半导体器件,其中所述半导体器件是垂直功率半导体器件,包括位于所述半导体本体的第一表面处的所述第一负载终端接触件以及位于所述半导体本体的第二表面处的所述第二负载终端接触件,并且还包括位于所述半导体本体的所述第一表面处的环绕所述半导体器件的有源区域的边缘终端结构。
30.根据权利要求17所述的半导体器件,其中所述半导体本体还包括n掺杂区域,所述n掺杂区域包括氢相关施主。
31.根据权利要求17所述的半导体器件,其中所述氧扩散阻挡是n掺杂二极管发射极区域、n掺杂漏极区域和p掺杂发射极区域中的一个。
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