JP6455514B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6455514B2 JP6455514B2 JP2016529402A JP2016529402A JP6455514B2 JP 6455514 B2 JP6455514 B2 JP 6455514B2 JP 2016529402 A JP2016529402 A JP 2016529402A JP 2016529402 A JP2016529402 A JP 2016529402A JP 6455514 B2 JP6455514 B2 JP 6455514B2
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
[先行技術文献]
[特許文献]
[特許文献1]特開平7−226521号公報
[特許文献2]特開2003−224281号公報
[特許文献3]特開2009−218496号公報
Claims (11)
- 第1導電型の半導体基板に設けられた第1導電型のドリフト層と、
前記ドリフト層の表面側に設けられた第2導電型の表面側領域と、
前記表面側領域の表面側に設けられ、厚さが自然酸化膜よりも薄い絶縁膜層と、
前記絶縁膜層の表面側に設けられた金属層とを備え、
前記絶縁膜層は、二酸化シリコンからなる半導体装置。 - 第1導電型の半導体基板に設けられた第1導電型のドリフト層と、
前記ドリフト層の表面側に設けられた第2導電型の表面側領域と、
前記表面側領域の表面側に設けられ、厚さが自然酸化膜よりも薄い絶縁膜層と、
前記絶縁膜層の表面側に設けられた金属層とを備える半導体装置であって、
前記半導体装置の外周近傍の少なくとも一部に設けられる外側電極と複数のゲート電極に電気的に接続する金属電極との間に、厚さが自然酸化膜よりも薄い前記絶縁膜層をさらに有する半導体装置。 - 前記外側電極は、前記ゲート電極に電気的に接続したポリシリコンである
請求項2に記載の半導体装置。 - 第1導電型の半導体基板に設けられた第1導電型のドリフト層と、
前記ドリフト層の表面側に設けられた第2導電型の表面側領域と、
前記表面側領域の表面側に設けられ、厚さが自然酸化膜よりも薄い絶縁膜層と、
前記絶縁膜層の表面側に設けられた金属層とを備え、
前記絶縁膜層は、アルミニウム酸化物とシリコン酸化物とを含む混成膜である半導体装置。 - 前記表面側領域を取り囲むように、前記ドリフト層の表面側に選択的に形成され、前記表面側領域と離間して形成された第2導電型の複数のガードリング層をさらに備え、
前記複数のガードリング層の表面側に前記絶縁膜層が設けられる請求項1から4のいずれか一項に記載の半導体装置。 - 前記表面側領域はアノード層である、請求項1から5のいずれか一項に記載の半導体装置。
- 前記表面側領域は、複数のゲート電極間における第2導電型のコンタクト領域である、請求項1から5のいずれか一項に記載の半導体装置。
- 前記絶縁膜層の厚さは、1Å以上6Å以下である、請求項1から7のいずれか一項に記載の半導体装置。
- 前記絶縁膜層の厚さは、6Å〜7Åである
請求項1から7のいずれか一項に記載の半導体装置。 - 前記絶縁膜層は、前記半導体基板と前記絶縁膜層との界面において、自然酸化膜よりもSi‐H結合を多く含む、請求項1から9のいずれか一項に記載の半導体装置。
- 前記絶縁膜層は窒素を含有しない、請求項1から10のいずれか一項に記載の半導体装置。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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JP2014125007 | 2014-06-18 | ||
JP2014125007 | 2014-06-18 | ||
JP2015033862 | 2015-02-24 | ||
JP2015033862 | 2015-02-24 | ||
PCT/JP2015/067468 WO2015194590A1 (ja) | 2014-06-18 | 2015-06-17 | 半導体装置および半導体装置の製造方法 |
Publications (2)
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JPWO2015194590A1 JPWO2015194590A1 (ja) | 2017-04-20 |
JP6455514B2 true JP6455514B2 (ja) | 2019-01-23 |
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JP2016529402A Active JP6455514B2 (ja) | 2014-06-18 | 2015-06-17 | 半導体装置および半導体装置の製造方法 |
Country Status (5)
Country | Link |
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US (1) | US10050133B2 (ja) |
JP (1) | JP6455514B2 (ja) |
CN (1) | CN105814693B (ja) |
DE (1) | DE112015000204T5 (ja) |
WO (1) | WO2015194590A1 (ja) |
Cited By (1)
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KR20200125185A (ko) * | 2019-04-26 | 2020-11-04 | 홍익대학교 산학협력단 | 항복전압 특성이 개선된 쇼트키 장벽 다이오드 및 그 제조방법 |
Families Citing this family (3)
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CN108269742A (zh) * | 2016-12-30 | 2018-07-10 | 无锡昌德微电子股份有限公司 | 一种超快恢复二极管结构的实现方法 |
JP6854654B2 (ja) | 2017-01-26 | 2021-04-07 | ローム株式会社 | 半導体装置 |
JP7190256B2 (ja) * | 2018-02-09 | 2022-12-15 | ローム株式会社 | 半導体装置 |
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JPS5845831B2 (ja) * | 1975-06-06 | 1983-10-12 | サンケンデンキ カブシキガイシヤ | シヨツトキバリア半導体装置の製造方法 |
JPS5950232B2 (ja) * | 1977-11-04 | 1984-12-07 | 三菱電機株式会社 | 半導体装置とその製造方法 |
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JP4067159B2 (ja) * | 1997-12-01 | 2008-03-26 | 新電元工業株式会社 | 半導体装置および半導体装置の製造方法 |
JP4816834B2 (ja) * | 1999-05-21 | 2011-11-16 | 日産自動車株式会社 | 半導体装置 |
JP4123913B2 (ja) | 2001-11-26 | 2008-07-23 | 富士電機デバイステクノロジー株式会社 | 半導体装置の製造方法 |
US7393736B2 (en) * | 2005-08-29 | 2008-07-01 | Micron Technology, Inc. | Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics |
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2015
- 2015-06-17 DE DE112015000204.9T patent/DE112015000204T5/de not_active Ceased
- 2015-06-17 JP JP2016529402A patent/JP6455514B2/ja active Active
- 2015-06-17 WO PCT/JP2015/067468 patent/WO2015194590A1/ja active Application Filing
- 2015-06-17 CN CN201580002936.0A patent/CN105814693B/zh active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20200125185A (ko) * | 2019-04-26 | 2020-11-04 | 홍익대학교 산학협력단 | 항복전압 특성이 개선된 쇼트키 장벽 다이오드 및 그 제조방법 |
KR102183959B1 (ko) | 2019-04-26 | 2020-11-27 | 홍익대학교 산학협력단 | 항복전압 특성이 개선된 쇼트키 장벽 다이오드 및 그 제조방법 |
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Publication number | Publication date |
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WO2015194590A1 (ja) | 2015-12-23 |
JPWO2015194590A1 (ja) | 2017-04-20 |
DE112015000204T5 (de) | 2016-08-25 |
US10050133B2 (en) | 2018-08-14 |
CN105814693B (zh) | 2019-05-03 |
US20160300936A1 (en) | 2016-10-13 |
CN105814693A (zh) | 2016-07-27 |
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