WO2015194590A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- WO2015194590A1 WO2015194590A1 PCT/JP2015/067468 JP2015067468W WO2015194590A1 WO 2015194590 A1 WO2015194590 A1 WO 2015194590A1 JP 2015067468 W JP2015067468 W JP 2015067468W WO 2015194590 A1 WO2015194590 A1 WO 2015194590A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 227
- 239000011259 mixed solution Substances 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 10
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 19
- 238000000034 method Methods 0.000 description 18
- 235000012431 wafers Nutrition 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 11
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- LKTZODAHLMBGLG-UHFFFAOYSA-N alumanylidynesilicon;$l^{2}-alumanylidenesilylidenealuminum Chemical group [Si]#[Al].[Si]#[Al].[Al]=[Si]=[Al] LKTZODAHLMBGLG-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002129 infrared reflectance spectroscopy Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005502 peroxidation Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H01L29/868—PIN diodes
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- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Definitions
- the present invention relates to a power semiconductor device such as a semiconductor rectifier (hereinafter referred to as a diode) and an IGBT (insulated gate bipolar transistor).
- a power semiconductor device such as a semiconductor rectifier (hereinafter referred to as a diode) and an IGBT (insulated gate bipolar transistor).
- a free wheeling diode (FWD) for power is connected in anti-parallel with a switching element such as an IGBT, and it is important to improve the performance of the FWD as well as improving the performance of the switching element to increase the frequency of the inverter.
- FWD free wheeling diode
- FIG. 11 is a cross-sectional view showing the structure of a conventional, conventional power return diode.
- the power diode is a diode having a p-intrinsic-n type (pin type) structure, and holds a high voltage in a high resistance intrinsic layer (i layer). This i layer is also referred to as n - drift layer 62. Since a power diode having a rated voltage of 600 V or more uses a wafer cut from an ingot of silicon or the like, an n-type semiconductor substrate (wafer) constitutes an n ⁇ drift layer 62. A p-anode layer 63 is formed on the surface side of the n ⁇ drift layer 62.
- An anode electrode 65 for passing a main current is connected to the surface 64 of the p anode layer 63.
- the p anode layer 63 and the anode electrode 65 are referred to as an active region because the main current flows.
- field plate electrode 72 connected to p + guard ring 71 and p + guard ring 71 is formed so as to surround p anode layer 63.
- a p-type or n-type channel stopper layer 73 and a stopper electrode 74 connected to the channel stopper layer 73 are formed at the chip outer peripheral end of the diode.
- the portion surrounding the outer periphery of the active region is a region for relaxing the electric field when a reverse bias voltage is applied to the diode, and is called an edge termination region.
- An interlayer insulating film 68 is formed on part of the surface of the diode to protect the surface of the semiconductor from exposure. Furthermore, although not shown, a protective film for protecting the surface, such as a polyimide film or a silicon nitride film, is also formed.
- the n - other surface of the drift layer 62, n - a high concentration of n field stop layer 67 is formed than the drift layer 62.
- the n field stop layer 67 has a function of suppressing the spread of the depletion layer.
- an n + cathode layer 61 is formed in contact with the n field stop layer 67 as well.
- a cathode electrode 66 is formed to be connected to the n + cathode layer 61.
- the injection efficiency of the anode can be lowered to achieve soft recovery.
- FIG. 1 of Patent Document 3 a diode with a pin structure in which a natural oxide film is sandwiched between a p-type polysilicon layer (corresponding to a p-type anode layer) and an n -- type semiconductor layer (corresponding to a drift layer). Is described.
- Patent Document 3 Japanese Patent Application Publication No. 2009-218496
- a semiconductor device provided with an insulating film layer provided on the surface side of a side region and having a thickness smaller than that of a natural oxide film, and a metal layer provided on the surface side of the insulating film layer.
- the plurality of guard ring layers of the second conductivity type selectively formed on the surface side of the drift layer so as to surround the surface side region and separated from the surface side region are further provided.
- the insulating film layer may be provided on the surface side.
- the front side region may be an anode layer.
- the surface side region may be a contact region of the second conductivity type between the plurality of gate electrodes.
- the semiconductor device may further include an insulating film layer between an outer electrode provided in at least a part in the vicinity of the outer periphery of the semiconductor device and a metal electrode electrically connected to the plurality of gate electrodes.
- the thickness of the insulating film layer may be 1 ⁇ or more and 6 ⁇ or less.
- the insulating film layer may contain more Si—H bonds than the natural oxide film at the interface between the semiconductor substrate and the insulating film layer.
- the insulating film layer may not contain nitrogen.
- An insulating film layer forming step of forming an insulating film layer thinner than a natural oxide film on a surface of a semiconductor substrate exposed at an opening of a formed interlayer insulating film is provided.
- the insulating film layer forming step may include exposing the exposed surface of the semiconductor substrate to a mixed solution of ammonia water, hydrogen peroxide solution, and pure water.
- the thickness of the insulating film layer may be adjusted according to the concentration of ammonia water in the mixed solution.
- the concentration of ammonia water in the mixed solution may be 1 ppm or more and 150000 ppm or less.
- FIG. 1 is a cross-sectional view showing a layer configuration of a semiconductor device according to a first embodiment.
- FIG. 5 is a flow diagram showing a manufacturing flow of the semiconductor device according to the first embodiment.
- FIG. 5 is a characteristic diagram showing the relationship between the solution concentration and the oxide film thickness in the semiconductor device according to the first embodiment. It is a figure which shows the example which is the hybrid film which the insulating film layer 4 contains an aluminum oxide and a silicon oxide.
- FIG. 3 is a characteristic diagram showing an internal state of the semiconductor device according to the first embodiment at the time of energization.
- FIG. 6 is a characteristic diagram showing current and voltage waveforms at the time of reverse recovery for the semiconductor device according to the first embodiment.
- FIG. 1 is a cross-sectional view showing a layer configuration of a semiconductor device according to a first embodiment.
- FIG. 5 is a flow diagram showing a manufacturing flow of the semiconductor device according to the first embodiment.
- FIG. 5 is a characteristic diagram showing the relationship between the solution
- FIG. 6 is a characteristic diagram showing the relationship between the oxide film thickness and the electrical characteristics of the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view showing a layer configuration of a semiconductor device according to a second embodiment.
- FIG. 16 is a schematic top view of the corner 110 of the semiconductor substrate 100 according to the fourth embodiment. It is a figure which shows the A1-A2 cross section of FIG. It is sectional drawing which shows the laminated constitution of the conventional semiconductor device.
- n and p in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively.
- + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively.
- concentration indicates the concentration of a dopant exhibiting n-type or p-type conductivity unless otherwise specified, that is, the doping concentration.
- the first conductivity type is described as n-type
- the second conductivity type is described as p-type. However, this may be reversed to make the first conductivity type p-type and the second conductivity type n-type.
- FIG. 1 is a cross sectional view showing a cross sectional structure of a semiconductor device according to a first embodiment of the present invention.
- the semiconductor device is a pin diode in the first embodiment.
- a silicon semiconductor substrate for example, a wafer cut out of a silicon ingot formed by CZ (Czochralski method), MCZ (Czochralski method with applied magnetic field), FZ (float zone method) or the like is used.
- the specific resistance of the wafer is, for example, higher than 10 ⁇ cm, for example 55 to 90 ⁇ cm.
- the thickness of the n ⁇ drift layer 2 may be, for example, 100 to 130 ⁇ m.
- the semiconductor device includes an n ⁇ drift layer 2 as a drift layer of the first conductivity type, an oxide film layer 4 as an insulating film layer, and an anode electrode 5 as a metal layer.
- the n ⁇ drift layer 2 is provided on a silicon semiconductor substrate of the first conductivity type.
- the n - surface side of the drift layer 2, n - p-anode layer 3 as a surface side region of the second conductivity type having a high impurity concentration is provided than the drift layer 2.
- a very thin oxide film 4 having a thickness of several angstroms is provided on the surface side of the p anode layer 3.
- the thickness of the oxide film layer 4 is thinner than that of the native oxide film.
- the oxide film layer 4 covers the entire p anode layer 3.
- An anode electrode 5 is provided on the surface side of the p anode layer 3 with the oxide film layer 4 interposed therebetween.
- the oxide film layer 4 separates the anode electrode 5 from the p-anode layer 3.
- the thickness t of the oxide film layer 4 which is this separation distance determines the electrical characteristics of the diode.
- the thickness t of the oxide film layer 4 is thinner than the thickness (20 ⁇ or more) of the native oxide film.
- this oxide film layer 4 between the p anode layer 3 and the anode electrode 5
- injection of carriers (holes) is suppressed more than in the conventional structure.
- the depletion layer extends in the p anode layer 3 and the n ⁇ drift layer 2, so that the voltage is not shared by the oxide film layer 4. Therefore, no strong electric field is generated in oxide film layer 4. Therefore, dielectric breakdown of oxide film layer 4 does not occur.
- the thickness t of the oxide film layer 4 will be described later.
- the dopant of the p anode layer 3 is, for example, boron.
- the total impurity concentration of boron may be 1 ⁇ 10 13 cm ⁇ 2 to 5 ⁇ 10 13 cm ⁇ 2 and the diffusion depth may be about 4 ⁇ m or less.
- the anode electrode 5 and the p anode layer 3 become an active region for flowing a main current.
- the semiconductor device of this example is formed selectively on the surface side of the n ⁇ drift layer 2 so as to surround the active region, and is formed of a plurality of guard ring layers of the second conductivity type formed apart from the p anode layer 3. As a plurality of p + guard ring layer 11 is provided.
- Ap + guard ring layer 11 and a field plate electrode 12 are provided to surround the active region. Also, channel stopper layer 13 and stopper electrode 14 are provided to surround p + guard ring layer 11 and field plate electrode 12.
- the area surrounding the active area is an edge termination area.
- the oxide film layer 4 is also provided on the surface side of the plurality of p + guard ring layers 11.
- the p + guard ring layer 11 and the field plate electrode 12 are separated by sandwiching the oxide film layer 4 similarly to the active region.
- the channel stopper layer 13 and the stopper electrode 14 are separated by sandwiching the oxide film layer 4.
- An interlayer insulating film is provided on the surface side of the semiconductor substrate, between the anode electrode 5 and the field plate electrode 12, between the field plate electrodes 12, and between the field plate electrode 12 and the stopper electrode 14. Eight is provided.
- n + cathode layer 1 is provided on the back surface side of the silicon semiconductor substrate.
- a cathode electrode 6 is provided on the back surface side of the n + cathode layer 1. The n + cathode layer 1 and the cathode electrode 6 are connected to each other.
- an n field stop layer 7 is provided between the n + cathode layer 1 and the n ⁇ drift layer 2.
- the n + cathode layer 1 may have a total impurity amount of phosphorus as a dopant of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 .
- the n + cathode layer 1 may have a thickness of 1 ⁇ m or less.
- FIG. 2 is a flow chart showing the manufacturing flow of the semiconductor device of the present invention.
- an n-type high specific resistance semiconductor substrate FZ wafer, CZ wafer, MCZ wafer, etc.
- a thermal oxide film field oxide film or the like
- the p anode layer 3 and the p + guard ring layer 11 as the surface side region are selectively formed.
- an interlayer insulating film 8 is formed on the surface side of the semiconductor substrate. By selectively removing the interlayer insulating film 8, the opening of the interlayer insulating film 8 is selectively formed. Thereby, the interlayer insulating film 8 is selectively formed.
- the underlying semiconductor substrate is exposed at the opening. This is referred to as the surface structure forming step (S1).
- the surface of the semiconductor substrate exposed at the opening of the interlayer insulating film 8 selectively formed is ammonia water ([NH 4 + ] [OH ⁇ ] diluted aqueous solution, hereinafter described as NH 4 OH), peroxidation It is exposed to a mixed solution of hydrogen water (H 2 O 2 ) and pure water (H 2 O).
- a resin carrier in which several tens of wafers are arranged, is dipped in the mixed solution. The immersion time may be a few seconds to a few minutes, for example 60 seconds to 120 seconds.
- the temperature of the mixed solution is, for example, about room temperature (about 23 ° C.) to about 60 ° C.
- the thin oxide film layer 4 can also be formed by exposing the wafer to a mixture of hydrochloric acid (HCl), hydrogen peroxide solution (H 2 O 2 ) and water (H 2 O).
- the oxide film layer 4 thinner than the natural oxide film is formed on the exposed surface which is the surface side of the semiconductor substrate.
- the step of exposing the exposed surface to the mixed solution needs to be performed before the natural oxide film is formed on the semiconductor substrate exposed at the opening. Thereby, the thickness of the oxide film layer 4 can be controlled to be smaller than that of the natural oxide film.
- the step of forming the oxide film layer 4 on the surface side of the semiconductor substrate exposed in the opening as described above is referred to as an oxide film layer forming step (S2).
- the thickness of the oxide film layer 4 is adjusted in accordance with the concentration of aqueous ammonia (NH 4 OH) in the mixed solution.
- FIG. 3 is a characteristic diagram showing the correlation between the concentration (horizontal axis) of ammonia water in the mixed solution and the thickness t (vertical axis) of the oxide film layer 4 to be formed.
- the natural oxide film on the surface of the semiconductor substrate was removed by hydrofluoric acid.
- the oxide film layer 4 was formed by immersing the semiconductor substrate in a mixed solution of a predetermined concentration.
- the thickness of the formed oxide film layer 4 was measured by X-ray photoelectron spectroscopy (Electron Spectroscopy for Chemical Analysis, ESCA).
- the ESCA measurement device using the PHI Quantera SXM TM of Abubakku Phi Corporation.
- the thickness of the oxide film layer 4 is 1 to 3 ⁇ at a concentration of 1 ppm of NH 4 OH, and increases to about 6 ⁇ when it is increased to 100 ppm. Further, at 1000 ppm, the thickness of the oxide film 4 to be formed is saturated and becomes about 6 ⁇ to 7 ⁇ .
- the thickness of the natural oxide film is generally 10 ⁇ or more, for example, 20 ⁇ . Therefore, the oxide film layer 4 in the semiconductor device of the present invention is an oxide film layer whose thickness is controlled to be thinner than that of the natural oxide film. Therefore, the contact resistance between the anode electrode 5 and the p anode layer 3 can be reduced as compared to the case of using a natural oxide film.
- the concentration of NH 4 OH is preferably 1 ppm or more and 150000 ppm (15%) or less, more preferably 10000 ppm (1%) or more and 50000 ppm (5%) or less to obtain the oxide film layer 4 having a predetermined thickness. Thereby, oxide film layer 4 of about 6 ⁇ can be stably formed. On the other hand, in order to make the oxide film layer 4 thinner, for example, it may be 1 ppm or more and 100 ppm or less.
- FIG. 4 is a diagram showing an example in which the oxide film layer 4 is a mixed film containing aluminum oxide and silicon oxide.
- the thin oxide film layer 4 formed by the above method may be not only SiO 2 but also a hybrid film containing AlO x and SiO x .
- AlO x in the mixed film is shown by colored circles, and SiO x is shown by white circles.
- the oxygen concentration of the oxide film layer 4 can be evaluated by energy dispersive X-ray spectroscopy (EDX). It may be confirmed by EDX that the oxide film layer 4 is different from the natural oxide film.
- EDX energy dispersive X-ray spectroscopy
- oxide film layer 4 is formed by the above method, oxidation and etching are repeated by the mixed solution on the surface of the silicon substrate as the semiconductor substrate. This causes the surface of the silicon substrate to be slightly roughened. In order to measure the surface roughness of the silicon substrate, a scanning tunneling microscope (STM) was used to evaluate the roughness of the formed oxide film layer 4.
- STM scanning tunneling microscope
- the roughness of the oxide film layer 4 formed was 10 to 30% of the film thickness.
- the roughness of the native oxide is less than 10%, typically on the order of 1%. That is, the surface of the oxide film layer 4 formed by the above method becomes rougher than the surface of the natural oxide film.
- the oxide film layer 4 is formed by repetition of oxidation and etching by the mixed solution.
- the natural oxide film grows in the horizontal direction parallel to the surface of the silicon substrate, with the oxide film grown in the form of an island as a nucleus. Therefore, the surface of the oxide film layer 4 is considered to be rougher than the surface of the native oxide film.
- the insulating film layer 4 contains more Si—H bonds at the interface between the oxide film layer 4 and the silicon substrate than the natural oxide film. Since the natural oxide film is formed by the reaction with air containing oxygen and nitrogen, it is considered that the natural oxide film contains more nitrogen than the insulating film layer 4.
- the insulating film layer 4 may not contain nitrogen. In the present specification, not containing nitrogen may mean that the nitrogen content at the interface between the silicon substrate and the natural oxide film is smaller than 1 ⁇ 10 14 cm ⁇ 3 . Infrared reflection absorption spectrometry (IR-RAS) may be used to evaluate the chemical bonding state of the interface.
- IR-RAS Infrared reflection absorption spectrometry
- the above describes a batch process in which multiple wafers are immersed in the mixed solution.
- single-wafer processing in which each sheet is exposed to the mixed solution.
- single-wafer processing for example, one wafer is placed on a stage with the top surface facing the wafer, and the wafer is rotated at a predetermined rotation speed.
- the mixed solution is dropped onto the rotating wafer, and the mixed solution is spread over the entire wafer to expose the opening of the interlayer insulating film 8 to the mixed solution (spin coating).
- the processing conditions such as the time of exposure to the solution per sheet, the temperature and the like can be adjusted, and the variation in processing conditions among the wafers can be suppressed small.
- the anode electrode 5 is selectively formed by sputtering or the like.
- the metal of the anode electrode 5 is, for example, an alloy of aluminum (Al) and silicon (Si). If necessary, the metal film to be the electrode is sintered at a temperature of about 380 ° C. to 450 ° C.
- a protective film may be formed of polyimide or the like. The above is referred to as a surface electrode forming step (S3).
- the anode electrode 5 may use an alloy of aluminum (Al), silicon (Si) and copper (Cu) in addition to the above-mentioned metals. In that case, the mass ratio of Si in the alloy may be 1 to 2%, and the mass ratio of Cu may be 0.1% or more.
- the back surface of the semiconductor substrate is ground and etched.
- the thickness of the semiconductor substrate is reduced to about 50 ⁇ m to 200 ⁇ m.
- the process of reducing the thickness of the semiconductor substrate is referred to as a grinding process (S5).
- n field stop layer 7 and the n + cathode layer 1 are formed.
- a cathode electrode containing aluminum (Al), titanium (Ti), nickel (Ni), gold (Au) or the like is formed by a sputtering method or the like. These steps are called back surface structure forming step (S6). Through the above steps, the semiconductor device of the present invention is formed.
- FIG. 5 is a characteristic diagram showing the concentration distribution of holes and electrons when a forward bias is applied to the diode in the semiconductor device according to the first embodiment of the present invention.
- the horizontal axis indicates the depth from the anode surface, and the left end is the anode and the right end is the cathode.
- the vertical axis shows the density of holes. It can be seen that the carrier density on the anode side is smaller in the structure in which the oxide film layer 4 is deposited than in the conventional structure. Therefore, it can be said that carrier injection is suppressed by the oxide film layer 4.
- FIG. 6 is a characteristic diagram comparing the current and voltage waveforms at the time of reverse recovery with the conventional example for the semiconductor device according to the first embodiment of the invention. It can be seen that the reverse recovery peak current (Irp) is reduced because the injection of holes is suppressed in the structure of the present invention compared to the conventional structure.
- Irp reverse recovery peak current
- FIG. 7 is a characteristic diagram showing the relationship between the thickness of the oxide film layer 4 and the electrical characteristics of the semiconductor device according to the first embodiment of the present invention.
- the left axis shows the reverse recovery peak current (Irp).
- the vertical axis of the broken line graph is the left axis.
- the value on the left axis indicates a value obtained by normalizing the reverse recovery peak current when the diode is reversely recovered with the forward current as the rated current with the rated current.
- the right axis shows the forward voltage drop (forward voltage, V F ) when the rated current flows.
- the vertical axis of the solid line graph is the right axis.
- the horizontal axis is the thickness of the oxide film layer 4.
- the reverse recovery peak current of the broken line graph decreases as the thickness of the oxide layer 4 increases from 1 ⁇ to 4 ⁇ . On the other hand, when the thickness of the oxide film layer 4 exceeds 4 ⁇ , saturation occurs.
- the forward voltage of the solid line graph is substantially flat in the range from 1 ⁇ to less than 6 ⁇ in thickness of the oxide film layer 4. On the other hand, when the thickness of the oxide film 4 exceeds 6 ⁇ , the forward voltage sharply increases.
- the thickness of the oxide film layer 4 is preferably 1 ⁇ or more and 6 ⁇ or less, more preferably 2 ⁇ or more and 4 ⁇ or less.
- the oxide film layer 4 is formed between the anode electrode 5 and the p anode layer 3 with a controlled thickness and a thickness smaller than that of the natural oxide film.
- a semiconductor device capable of suppressing the injection of holes from the anode layer and reducing the reverse recovery peak current (Irp) with almost no change in the switching loss (Err), and a method of manufacturing the same.
- FIG. 8 is a cross sectional view showing a layer structure of a semiconductor device according to a second embodiment of the present invention.
- the difference between the semiconductor device of the second embodiment and the semiconductor device of the first embodiment is that the field plate electrode 12 in the edge termination region directly and annularly forms the p + guard ring layer 11 without sandwiching the oxide film layer 4. It is to connect electrically. By doing this, it becomes possible to transmit the potential further without delay in response to voltage application.
- the thin oxide film layer 4 is not limited to only SiO 2 .
- oxygen derived from the SiO 2 film may be taken into the Al film during heat treatment to form an AlO x film.
- the AlO x film of 1 nm or less also has an effect of suppressing the injection of carriers. Therefore, the oxide film layer 4 may include an AlO x film having a thickness of 1 nm or less.
- the oxide film layer 4 may include a film in which AlO x and SiO 2 are mixed and whose thickness is 1 nm or less.
- FIG. 9 is a schematic top view of a corner 110 of a semiconductor device according to a fourth embodiment.
- FIG. 9 is not a view showing the outermost surface of the corner 110.
- FIG. 9 is a schematic diagram for explaining the positional relationship between the gate electrode 30 and the lower interconnection 31. As shown in FIG. In FIG. 9, the gate electrode 30 is shown by a broken line, and the lower wiring 31 is shown by a solid line.
- Lower interconnection 31 has a portion extending parallel to an end parallel to the first direction of semiconductor substrate 100.
- Lower interconnection 31 has a portion extending parallel to an end parallel to the second direction of semiconductor substrate 100.
- Lower interconnection 31 is electrically connected to a contact metal provided on the surface side of lower interconnection 31 in contact portion 42.
- the gate electrode 30 has a portion extending parallel to an end parallel to the first direction of the semiconductor substrate 100.
- the gate electrode 30 has a U-shaped folded portion 40 when the semiconductor substrate 100 is viewed from the top.
- the lower wiring 31 is provided on the surface side of the gate electrode 30.
- the lower wire 31 is electrically connected to the gate electrode 30 at the U-shaped folded portion 40 of the gate electrode 30.
- FIG. 10 is a view showing a cross section A1-A2 of FIG.
- the semiconductor device of this example has a reverse conducting IGBT (RC-IGBT).
- the semiconductor substrate 100 has a collector electrode 20, a p + collector layer 21, a field stop layer 22, and a drift layer 23 in order from the back surface side to the front surface side.
- the semiconductor substrate 100 also has a p region 24 and a guard ring layer 26 on the surface side of the drift layer 23.
- the p region 24 has ap base region 24a shallower than the trench-shaped gate electrode 30, and ap + well region 24b deeper than the p base region 24a.
- an n ++ cathode layer 56 is formed in part.
- the region where the n ++ cathode layer 56 is formed becomes a reverse conducting diode in which the p base region 24 a on the surface side functions as a p-type anode layer.
- the reverse recovery operation of the reverse conducting diode becomes soft recovery.
- the p region 24 is provided with a contact region of the second conductivity type as a surface side region.
- the contact region of the second conductivity type is the p + contact 25.
- the p + contact 25 is provided between the plurality of gate electrodes 30.
- Gate electrode 30 is electrically separated from p region 24 by gate insulating film 32.
- the gate electrode 30 in this example is a trench-shaped gate electrode.
- the gate electrode 30 of this example has polysilicon.
- the gate insulating film 32 in this example is an oxide film having a thickness of 1000 ⁇ .
- An n + region 27 is provided between the gate insulating film 32 and the p + contact 25.
- the lower wiring 31 is, for example, polysilicon. When the gate electrode 30 is viewed from above the semiconductor substrate 100, polysilicon forming the gate electrode 30 may be continuously connected to the upper wiring 34 at the U-shaped folded portion 40.
- an interlayer insulating film 38 is provided on the surface side of the semiconductor substrate 100 relative to the gate electrode 30 and in contact with the gate electrode 30.
- the semiconductor device of this embodiment is the surface side of the semiconductor substrate 100 than p + contact 25, and having an oxide film layer 4 in contact with the p + contact 25.
- the oxide film layer 4 is an oxide film layer formed by the above-described mixed solution. Oxide film layer 4 has a thickness sufficiently thinner than interlayer insulating film 38.
- An emitter electrode 39 is provided on the surface side of oxide film layer 4 and interlayer insulating film 38.
- the emitter electrode 39 in this example is aluminum silicide (Al-Si).
- the surface side of oxide film layer 4 is the surface of oxide film layer 4 on the opposite side to the surface on which oxide film layer 4 and p + contact 25 are in contact.
- the semiconductor device of this example has a thermal oxide film 37 on the surface side of the semiconductor substrate 100 in the p region 24 (p + well region 24 b) in the vicinity of the guard ring layer 26.
- the portion where thermal oxide film 37 and p region 24 are in contact is referred to as the back surface side of thermal oxide film 37.
- the surface of the thermal oxide film 37 opposite to the back surface is referred to as the surface side of the thermal oxide film 37.
- the semiconductor device of this example has a lower interconnection 31 as an electrode of a polysilicon film electrically connected to the plurality of gate electrodes 30 on the surface side of the thermal oxide film 37.
- Lower interconnection 31 is formed above p + well region 24 b with thermal oxide film 37 interposed therebetween.
- An interlayer insulating film 38 is provided on the surface side of the lower interconnection 31.
- the semiconductor device of this example has the oxide film layer 4 in the opening of the interlayer insulating film 38. This oxide film layer 4 is also an oxide film layer formed by the above-mentioned mixed solution.
- the portion where the oxide film layer 4 and the lower wiring 31 are in contact with each other is referred to as the back surface side of the oxide film layer 4.
- the surface opposite to the back surface side of the oxide film layer 4 is referred to as the front surface side of the oxide film layer 4.
- the semiconductor device of this example has an upper wire 34 as an outer metal electrode on the surface side of the oxide film layer 4.
- the upper wiring 34 is an outer electrode provided on at least a part in the vicinity of the outer periphery of the semiconductor device.
- the upper wiring 34 is, for example, Al-Si.
- the oxide film layer 4 is also provided between the upper wiring 34 and the lower wiring 31.
- the present invention is not limited to silicon, and can be applied to wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). That is, the object of the present invention can be achieved if there is an insulating film, particularly a silicon oxide film, whose thickness is controlled to be thinner than the natural oxide film as described above between the metal serving as the electrode and the semiconductor substrate.
- SiC silicon carbide
- GaN gallium nitride
- contact portion 56 ... cathode layer, 61 ... n + cathode layer, 62 ... n - drift layer, 63 ... p anode layer, 64 ... surface, 65 ... anode electrode, 66 ⁇ ⁇ cathode electrode, 67 ⁇ ⁇ n field stop layer, 68 ⁇ ⁇ interlayer insulating film, 71 ⁇ ⁇ p + guard ring, 72 ⁇ ⁇ ⁇ field plate electrode 73 ⁇ ⁇ ⁇ channel stopper layer, 74 ⁇ ⁇ stopper electrode, 100 ⁇ ⁇ Semiconductor substrate, 110 ⁇ ⁇ ⁇ corner
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Abstract
Description
[先行技術文献]
[特許文献]
[特許文献1]特開平7-226521号公報
[特許文献2]特開2003-224281号公報
[特許文献3]特開2009-218496号公報
Claims (13)
- 第1導電型の半導体基板に設けられた第1導電型のドリフト層と、
前記ドリフト層の表面側に設けられた第2導電型の表面側領域と、
前記表面側領域の表面側に設けられ、厚さが自然酸化膜よりも薄い絶縁膜層と、
前記絶縁膜層の表面側に設けられた金属層とを備える半導体装置。 - 前記表面側領域を取り囲むように、前記ドリフト層の表面側に選択的に形成され、前記表面側領域と離間して形成された第2導電型の複数のガードリング層をさらに備え、
前記複数のガードリング層の表面側に前記絶縁膜層が設けられる請求項1に記載の半導体装置。 - 前記表面側領域はアノード層である、請求項1または2に記載の半導体装置。
- 前記表面側領域は、複数のゲート電極間における第2導電型のコンタクト領域である、請求項1または2に記載の半導体装置。
- 前記半導体装置の外周近傍の少なくとも一部に設けられる外側電極と前記複数のゲート電極に電気的に接続する金属電極との間に、前記絶縁膜層をさらに有する
請求項4に記載の半導体装置。 - 前記絶縁膜層の厚さは、1Å以上6Å以下である、請求項1から5のいずれかまたは2に記載の半導体装置。
- 前記絶縁膜層は、前記半導体基板と前記絶縁膜層との界面において、自然酸化膜よりもSi‐H結合を多く含む、請求項1から6のいずれか一項に記載の半導体装置。
- 前記絶縁膜層は窒素を含有しない、請求項1から7のいずれか一項に記載の半導体装置。
- 前記絶縁膜層は、アルミニウム酸化物とシリコン酸化物とを含む混成膜である、請求項1から8のいずれか一項に記載の半導体装置。
- 第1導電型の半導体基板の表面側に、表面側領域、熱酸化膜、および層間絶縁膜をそれぞれ選択的に形成する表面構造形成工程と、
選択的に形成された前記層間絶縁膜の開口部において露出する前記半導体基板の表面に、自然酸化膜よりも薄い絶縁膜層を形成する絶縁膜層形成工程と
を備える半導体装置の製造方法。 - 前記絶縁膜層形成工程は、露出する前記半導体基板の表面を、アンモニア水、過酸化水素水、および純水の混合溶液に晒すことを含む請求項10の半導体装置の製造方法。
- 前記混合溶液におけるアンモニア水の濃度に応じて、前記絶縁膜層の厚さを調整する請求項11に記載の半導体装置の製造方法。
- 前記混合溶液におけるアンモニア水の濃度は、1ppm以上150000ppm以下である請求項12に記載の半導体装置の製造方法。
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CN201580002936.0A CN105814693B (zh) | 2014-06-18 | 2015-06-17 | 半导体装置以及半导体装置的制造方法 |
DE112015000204.9T DE112015000204T5 (de) | 2014-06-18 | 2015-06-17 | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
JP2016529402A JP6455514B2 (ja) | 2014-06-18 | 2015-06-17 | 半導体装置および半導体装置の製造方法 |
US15/170,945 US10050133B2 (en) | 2014-06-18 | 2016-06-02 | Application of thin insulating film layer in semiconductor device and method of manufacturing semiconductor device |
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JP6854654B2 (ja) | 2017-01-26 | 2021-04-07 | ローム株式会社 | 半導体装置 |
JP7190256B2 (ja) * | 2018-02-09 | 2022-12-15 | ローム株式会社 | 半導体装置 |
KR102183959B1 (ko) * | 2019-04-26 | 2020-11-27 | 홍익대학교 산학협력단 | 항복전압 특성이 개선된 쇼트키 장벽 다이오드 및 그 제조방법 |
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JPS62160730A (ja) * | 1986-01-09 | 1987-07-16 | Fujitsu Ltd | 半導体装置の製造方法 |
JP3737524B2 (ja) | 1994-02-10 | 2006-01-18 | 新電元工業株式会社 | 整流用半導体装置 |
JP3287269B2 (ja) * | 1997-06-02 | 2002-06-04 | 富士電機株式会社 | ダイオードとその製造方法 |
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CN105814693A (zh) | 2016-07-27 |
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US20160300936A1 (en) | 2016-10-13 |
JPWO2015194590A1 (ja) | 2017-04-20 |
CN105814693B (zh) | 2019-05-03 |
JP6455514B2 (ja) | 2019-01-23 |
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