JP2008503073A - 層構造の製造方法 - Google Patents

層構造の製造方法 Download PDF

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Publication number
JP2008503073A
JP2008503073A JP2007515772A JP2007515772A JP2008503073A JP 2008503073 A JP2008503073 A JP 2008503073A JP 2007515772 A JP2007515772 A JP 2007515772A JP 2007515772 A JP2007515772 A JP 2007515772A JP 2008503073 A JP2008503073 A JP 2008503073A
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JP
Japan
Prior art keywords
layer
etching
manufacturing
sacrificial
sacrificial layer
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Pending
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JP2007515772A
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English (en)
Japanese (ja)
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JP2008503073A5 (enExample
Inventor
エッカート，シュテファン
ゴラー，クラウス
ヴェント，ヘルマン
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2008503073A publication Critical patent/JP2008503073A/ja
Publication of JP2008503073A5 publication Critical patent/JP2008503073A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2007515772A 2004-06-18 2005-06-15 層構造の製造方法 Pending JP2008503073A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004029519A DE102004029519A1 (de) 2004-06-18 2004-06-18 Verfahren zum Herstellen einer Schicht-Anordnung
PCT/DE2005/001067 WO2005124854A1 (de) 2004-06-18 2005-06-15 Verfahren zum herstellen einer schicht-anordnung

Publications (2)

Publication Number Publication Date
JP2008503073A true JP2008503073A (ja) 2008-01-31
JP2008503073A5 JP2008503073A5 (enExample) 2010-03-18

Family

ID=34972419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007515772A Pending JP2008503073A (ja) 2004-06-18 2005-06-15 層構造の製造方法

Country Status (5)

Country Link
US (1) US7795135B2 (enExample)
JP (1) JP2008503073A (enExample)
CN (1) CN101006577A (enExample)
DE (1) DE102004029519A1 (enExample)
WO (1) WO2005124854A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004029519A1 (de) * 2004-06-18 2006-01-12 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung
KR101732975B1 (ko) * 2010-12-03 2017-05-08 삼성전자주식회사 반도체 장치의 제조 방법
CN103969966B (zh) * 2014-05-15 2015-04-15 京东方科技集团股份有限公司 一种光刻胶的去除方法
JP6816964B2 (ja) * 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
DE102017216835B9 (de) * 2017-09-22 2022-06-30 Infineon Technologies Ag MEMS-Bauelement und Herstellungsverfahren für ein MEMS-Bauelement
DE102020201567A1 (de) 2020-02-08 2021-08-12 Robert Bosch Gesellschaft mit beschränkter Haftung Herstellungsverfahren für ein mikromechanisches Bauelement und entsprechendes mikromechanisches Bauelement
US12062547B2 (en) * 2021-09-08 2024-08-13 Nanya Technology Corporation Method of fabricating semiconductor device and patterning semiconductor structure

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04218946A (ja) * 1990-08-03 1992-08-10 Oki Electric Ind Co Ltd スルーホールの形成方法
JPH04259241A (ja) * 1991-02-14 1992-09-14 Olympus Optical Co Ltd 半導体装置の製造方法
JPH05190688A (ja) * 1992-01-14 1993-07-30 Matsushita Electric Ind Co Ltd 多層配線の形成方法
JPH08274170A (ja) * 1995-03-30 1996-10-18 Nec Corp 半導体装置の製造方法
JPH09129732A (ja) * 1995-10-31 1997-05-16 Nec Corp 半導体装置の製造方法
JPH09191051A (ja) * 1995-12-29 1997-07-22 Lg Semicon Co Ltd 半導体素子の配線構造及びその形成方法
JPH10303299A (ja) * 1997-04-25 1998-11-13 Oki Electric Ind Co Ltd コンタクトホールの形成方法
JP2000235973A (ja) * 1999-02-17 2000-08-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001127151A (ja) * 1999-10-26 2001-05-11 Fujitsu Ltd 半導体装置およびその製造方法
US20030036227A1 (en) * 2001-08-17 2003-02-20 Falko Hohnsdorf Process for producing contact holes on a metallization structure
JP2004079805A (ja) * 2002-08-19 2004-03-11 Seiko Epson Corp 配線、配線の形成方法、半導体装置及びその製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943539A (en) * 1989-05-09 1990-07-24 Motorola, Inc. Process for making a multilayer metallization structure
US5817574A (en) * 1993-12-29 1998-10-06 Intel Corporation Method of forming a high surface area interconnection structure
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US5686356A (en) * 1994-09-30 1997-11-11 Texas Instruments Incorporated Conductor reticulation for improved device planarity
US5700737A (en) * 1996-02-26 1997-12-23 Taiwan Semiconductor Manufactured Company Ltd. PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination
US6015751A (en) * 1998-04-06 2000-01-18 Taiwan Semiconductor Manufacturing Company Self-aligned connection to underlayer metal lines through unlanded via holes
US20030201121A1 (en) * 2002-04-25 2003-10-30 Pei-Ren Jeng Method of solving the unlanded phenomenon of the via etch
US20040048203A1 (en) * 2002-09-10 2004-03-11 Hitachi, Ltd. Method of manufacturing a semiconductor device for high speed operation and low power consumption
US7176571B2 (en) * 2004-01-08 2007-02-13 Taiwan Semiconductor Manufacturing Company Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
US7232762B2 (en) * 2004-06-16 2007-06-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an improved low power SRAM contact
DE102004029519A1 (de) * 2004-06-18 2006-01-12 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung
US7259083B2 (en) * 2004-10-22 2007-08-21 Lsi Corporation Local interconnect manufacturing process
US20080073724A1 (en) * 2006-09-22 2008-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Double layer etch stop layer structure for advanced semiconductor processing technology

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04218946A (ja) * 1990-08-03 1992-08-10 Oki Electric Ind Co Ltd スルーホールの形成方法
JPH04259241A (ja) * 1991-02-14 1992-09-14 Olympus Optical Co Ltd 半導体装置の製造方法
JPH05190688A (ja) * 1992-01-14 1993-07-30 Matsushita Electric Ind Co Ltd 多層配線の形成方法
JPH08274170A (ja) * 1995-03-30 1996-10-18 Nec Corp 半導体装置の製造方法
JPH09129732A (ja) * 1995-10-31 1997-05-16 Nec Corp 半導体装置の製造方法
JPH09191051A (ja) * 1995-12-29 1997-07-22 Lg Semicon Co Ltd 半導体素子の配線構造及びその形成方法
JPH10303299A (ja) * 1997-04-25 1998-11-13 Oki Electric Ind Co Ltd コンタクトホールの形成方法
JP2000235973A (ja) * 1999-02-17 2000-08-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001127151A (ja) * 1999-10-26 2001-05-11 Fujitsu Ltd 半導体装置およびその製造方法
US20030036227A1 (en) * 2001-08-17 2003-02-20 Falko Hohnsdorf Process for producing contact holes on a metallization structure
JP2004079805A (ja) * 2002-08-19 2004-03-11 Seiko Epson Corp 配線、配線の形成方法、半導体装置及びその製造方法

Also Published As

Publication number Publication date
US7795135B2 (en) 2010-09-14
CN101006577A (zh) 2007-07-25
DE102004029519A9 (de) 2006-05-11
US20080102625A1 (en) 2008-05-01
DE102004029519A1 (de) 2006-01-12
WO2005124854A1 (de) 2005-12-29

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