CN101006577A - 用于制造层结构的方法 - Google Patents

用于制造层结构的方法 Download PDF

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Publication number
CN101006577A
CN101006577A CNA2005800284267A CN200580028426A CN101006577A CN 101006577 A CN101006577 A CN 101006577A CN A2005800284267 A CNA2005800284267 A CN A2005800284267A CN 200580028426 A CN200580028426 A CN 200580028426A CN 101006577 A CN101006577 A CN 101006577A
Authority
CN
China
Prior art keywords
layer
make
sacrificial layer
conductive
layer structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005800284267A
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English (en)
Chinese (zh)
Inventor
S·厄克特
K·格勒
H·温德特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN101006577A publication Critical patent/CN101006577A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNA2005800284267A 2004-06-18 2005-06-15 用于制造层结构的方法 Pending CN101006577A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004029519.0 2004-06-18
DE102004029519A DE102004029519A1 (de) 2004-06-18 2004-06-18 Verfahren zum Herstellen einer Schicht-Anordnung

Publications (1)

Publication Number Publication Date
CN101006577A true CN101006577A (zh) 2007-07-25

Family

ID=34972419

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005800284267A Pending CN101006577A (zh) 2004-06-18 2005-06-15 用于制造层结构的方法

Country Status (5)

Country Link
US (1) US7795135B2 (enExample)
JP (1) JP2008503073A (enExample)
CN (1) CN101006577A (enExample)
DE (1) DE102004029519A1 (enExample)
WO (1) WO2005124854A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569173A (zh) * 2010-12-03 2012-07-11 三星电子株式会社 制造半导体装置的方法
CN109534280A (zh) * 2017-09-22 2019-03-29 英飞凌科技股份有限公司 Mems器件和mems器件的制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004029519A1 (de) * 2004-06-18 2006-01-12 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung
CN103969966B (zh) * 2014-05-15 2015-04-15 京东方科技集团股份有限公司 一种光刻胶的去除方法
JP6816964B2 (ja) * 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
DE102020201567A1 (de) 2020-02-08 2021-08-12 Robert Bosch Gesellschaft mit beschränkter Haftung Herstellungsverfahren für ein mikromechanisches Bauelement und entsprechendes mikromechanisches Bauelement
US12062547B2 (en) * 2021-09-08 2024-08-13 Nanya Technology Corporation Method of fabricating semiconductor device and patterning semiconductor structure

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US4943539A (en) * 1989-05-09 1990-07-24 Motorola, Inc. Process for making a multilayer metallization structure
JPH04218946A (ja) * 1990-08-03 1992-08-10 Oki Electric Ind Co Ltd スルーホールの形成方法
JPH04259241A (ja) * 1991-02-14 1992-09-14 Olympus Optical Co Ltd 半導体装置の製造方法
JPH05190688A (ja) * 1992-01-14 1993-07-30 Matsushita Electric Ind Co Ltd 多層配線の形成方法
US5817574A (en) * 1993-12-29 1998-10-06 Intel Corporation Method of forming a high surface area interconnection structure
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US5686356A (en) * 1994-09-30 1997-11-11 Texas Instruments Incorporated Conductor reticulation for improved device planarity
JP2959619B2 (ja) * 1995-03-30 1999-10-06 日本電気株式会社 半導体装置の製造方法
JPH09129732A (ja) * 1995-10-31 1997-05-16 Nec Corp 半導体装置の製造方法
KR100214467B1 (ko) 1995-12-29 1999-08-02 구본준 반도체소자의 배선구조 형성방법
US5700737A (en) * 1996-02-26 1997-12-23 Taiwan Semiconductor Manufactured Company Ltd. PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination
JP4114215B2 (ja) * 1997-04-25 2008-07-09 沖電気工業株式会社 コンタクトホールの形成方法
US6015751A (en) * 1998-04-06 2000-01-18 Taiwan Semiconductor Manufacturing Company Self-aligned connection to underlayer metal lines through unlanded via holes
JP4201421B2 (ja) * 1999-02-17 2008-12-24 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2001127151A (ja) * 1999-10-26 2001-05-11 Fujitsu Ltd 半導体装置およびその製造方法
DE10140468B4 (de) * 2001-08-17 2006-01-05 Infineon Technologies Ag Verfahren zur Erzeugung von Kontaktlöchern auf einer Metallisierungsstruktur
US20030201121A1 (en) * 2002-04-25 2003-10-30 Pei-Ren Jeng Method of solving the unlanded phenomenon of the via etch
JP2004079805A (ja) * 2002-08-19 2004-03-11 Seiko Epson Corp 配線、配線の形成方法、半導体装置及びその製造方法
US20040048203A1 (en) * 2002-09-10 2004-03-11 Hitachi, Ltd. Method of manufacturing a semiconductor device for high speed operation and low power consumption
US7176571B2 (en) * 2004-01-08 2007-02-13 Taiwan Semiconductor Manufacturing Company Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
US7232762B2 (en) * 2004-06-16 2007-06-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an improved low power SRAM contact
DE102004029519A1 (de) * 2004-06-18 2006-01-12 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung
US7259083B2 (en) * 2004-10-22 2007-08-21 Lsi Corporation Local interconnect manufacturing process
US20080073724A1 (en) * 2006-09-22 2008-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Double layer etch stop layer structure for advanced semiconductor processing technology

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569173A (zh) * 2010-12-03 2012-07-11 三星电子株式会社 制造半导体装置的方法
CN102569173B (zh) * 2010-12-03 2015-07-01 三星电子株式会社 制造半导体装置的方法
CN109534280A (zh) * 2017-09-22 2019-03-29 英飞凌科技股份有限公司 Mems器件和mems器件的制造方法

Also Published As

Publication number Publication date
US20080102625A1 (en) 2008-05-01
WO2005124854A1 (de) 2005-12-29
DE102004029519A9 (de) 2006-05-11
DE102004029519A1 (de) 2006-01-12
US7795135B2 (en) 2010-09-14
JP2008503073A (ja) 2008-01-31

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Open date: 20070725