CN102569173A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN102569173A
CN102569173A CN2011104027688A CN201110402768A CN102569173A CN 102569173 A CN102569173 A CN 102569173A CN 2011104027688 A CN2011104027688 A CN 2011104027688A CN 201110402768 A CN201110402768 A CN 201110402768A CN 102569173 A CN102569173 A CN 102569173A
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China
Prior art keywords
substrate
sacrifice layer
layer pattern
opening
electrode
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CN102569173B (zh
Inventor
朴炳律
崔吉铉
方硕哲
文光辰
林东灿
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明公开了一种制造半导体装置的方法。在制造半导体装置的方法中，准备具有第一表面和与第一表面相对的第二表面的基底。在基底的将形成贯通电极的区域中形成牺牲层图案。牺牲层图案沿基底的厚度方向从基底的第一表面延伸。在基底的第一表面上形成上部布线层。上部布线层包括位于牺牲层图案上的布线。将基底的第二表面部分地去除以暴露牺牲层图案。从基底的第二表面去除牺牲层图案，以形成暴露布线的开口。在开口中形成要电连接到布线的贯通电极。

Description

制造半导体装置的方法
本申请要求2010年12月3日在韩国知识产权局(KIPO)提交的第2010-0122577号韩国专利申请的优先权，该申请的全部内容通过引用包含于此。
技术领域
示例实施例涉及制造半导体装置的方法。更具体地讲，示例实施例涉及制造在半导体基底中具有贯通电极的半导体装置的方法。
背景技术
随着装置速度和装置集成度提高，信号延迟也会增加，例如，因互联结构所引起的寄生电容导致的信号延迟。集成技术的发展已经引起三维集成的发展，其中，与传统的二维方法相比，晶片可以三维堆叠。
在三维晶片堆叠封装件(WSP)中，可以使用被称作硅通孔(TSV)的技术来延伸穿过基底的通孔，从而可使贯通电极的导电通孔形成为竖直延伸并完全穿透基底。与长的布线图案互联相比，这样的TSV结构可提供更高的速度、更高的集成度以及改善的功能。例如，可以使用具有低电阻的铜(Cu)来形成导电通孔。然而，已知的是铜在硅中具有高的扩散率。
传统地，可以在后道工序之前穿过基底形成TSV。具体来讲，可通过在基底(例如，硅基底)中形成开口或孔来形成TSV结构。可在基底上和在开口中形成绝缘层。可例如通过镀覆工艺或沉积工艺在开口中形成导电金属层(例如，铜层(Cu))。之后，基底的背部可以凹陷以暴露导电金属层的至少一部分，从而形成穿过基底延伸的导电通孔。在这种情况下，包括导电通孔的基底可以在工艺(例如，蚀刻工艺)中重复地被暴露。特别地，当导电金属层的部分在蚀刻工艺中被暴露时，导电金属层的金属(例如，铜)会扩散到基底中，从而使诸如半导体芯片之类的半导体装置劣化。此外，会因金属与基底之间的热膨胀差而产生热应力。因此，会难于在基底中形成具有期望的高宽比的开口。此外，当在基底中形成开口时，会发生上部布线与贯通电极之间的未对准问题。
发明内容
示例实施例涉及制造半导体装置的方法。更具体地讲，示例实施例涉及制造在半导体基底中具有贯通电极的半导体装置的方法。
示例实施例提供一种包括具有期望的高宽比的贯通电极的半导体装置。
示例实施例提供一种包括半导体装置的半导体封装件。
示例实施例提供制造半导体装置的方法。
根据示例实施例，在制造半导体装置的方法中，准备具有第一表面和与第一表面相对的第二表面的基底。在基底的将形成贯通电极的区域中形成牺牲层图案。牺牲层图案沿基底的厚度方向从基底的第一表面延伸。在基底的第一表面上形成上部布线层。上部布线层包括位于牺牲层图案上的布线。将基底的第二表面部分地去除以暴露牺牲层图案。从基底的第二表面去除牺牲层图案，以形成暴露布线的第一开口。在第一开口中形成要电连接到布线的贯通电极。
在示例实施例中，形成牺牲层图案的步骤可包括：在基底中形成第二开口，所述第二开口沿基底的厚度方向从第一表面延伸；在第二开口的侧壁和底表面上形成第一绝缘层；在第一绝缘层上形成牺牲层；部分地去除牺牲层，以形成部分地填充第二开口的牺牲层图案。
在示例实施例中，可使用相对于第一绝缘层具有蚀刻选择性的绝缘材料来形成牺牲层。
在示例实施例中，牺牲层的蚀刻速率可以是第一绝缘层的蚀刻速率的至少三倍。
在示例实施例中，牺牲层和第一绝缘层的蚀刻选择性的范围可在大约3∶1至大约20∶1。
在示例实施例中，形成牺牲层图案的步骤可包括通过化学机械抛光工艺或蚀刻工艺部分地去除牺牲层。
在示例实施例中，可通过干蚀刻工艺或湿蚀刻工艺从基底去除牺牲层图案。
在示例实施例中，可将牺牲层图案形成为在其中具有空隙。
在示例实施例中，所述方法还可包括在形成暴露布线的第一开口之后在第一开口的侧壁上形成分隔件。
在示例实施例中，所述方法还可包括在牺牲层图案上形成覆层。
在示例实施中，形成暴露布线的第一开口的步骤可包括当从基底去除牺牲层图案时(即，同时)部分地去除覆层。
在示例实施例中，可使贯通电极形成为完全填充第一开口。
在示例实施例中，可沿第一开口的外形共形地形成贯通电极，以部分地填充开口。
在示例实施例中，贯通电极可在其下部包括凹进。
在示例实施例中，可在基底的第一表面上形成至少一个电路图案，并且布线可电连接到所述至少一个电路图案。
在示例实施例中，部分地去除基底的第二表面以暴露牺牲层图案的步骤可包括：部分地去除基底的第二表面，以暴露牺牲层图案的一部分；在基底的第二表面上形成第二绝缘层，以覆盖暴露的牺牲层图案；部分地去除第二绝缘层，以形成暴露牺牲层的下部的第二绝缘层。
在示例实施例中，可通过化学机械抛光工艺或蚀刻工艺来去除基底的第二表面。
在示例实施例中，可使用相对于牺牲层图案具有蚀刻选择性的绝缘材料来形成第二绝缘层。
在示例实施例中，牺牲层图案的蚀刻速率可以是第二绝缘层的蚀刻速率的至少三倍。
在示例实施例中，可通过连接构件将贯通电极电连接到另一半导体装置。根据示例实施例，制造半导体装置的方法可包括提供具有第一凹进的基底。在基底的第一表面上形成牺牲层图案。牺牲层图案填充在第一凹进中。可在基底的第一表面上形成上部布线层。通过部分地去除基底的第二表面来暴露牺牲层图案。第二表面与基底的第一表面相对。通过从第一凹进去除暴露的牺牲层图案来暴露上部布线层，并且形成连接到暴露的上部布线层的贯通电极。贯通电极电连接到暴露的上部布线层中的布线。
在示例实施例中，在暴露布线之后，可在第一凹进的侧壁上共形地形成绝缘层。可蚀刻绝缘层以在第一凹进的侧壁上形成分隔件。可在分隔件上形成种子层。贯通电极可形成在种子层上。
在示例实施例中，在基底的第一表面上形成牺牲层图案的步骤包括用用来形成牺牲层图案的绝缘材料填充第一凹进。
在示例实施例中，牺牲层图案可具有空隙。
在示例实施例中，在形成上部布线层之前，可在牺牲层图案上形成覆层。当暴露上部布线层时，可将覆层部分地去除。
在示例实施例中，在暴露上部布线层之后，可在第一凹进的侧壁和覆层上共形地形成绝缘层。可蚀刻绝缘层，以在第一凹进的侧壁上形成分隔件。可在分隔件上形成种子层。贯通电极可形成在种子层上。
在示例实施例中，可在贯通电极中形成第二凹进。
根据示例实施例，在根据示例实施例的制造半导体装置的方法中，可以在用于使贯通电极形成为沿基底的厚度方向从基底的第一表面延伸的区域中形成牺牲层图案。可执行布线工序(BEOL工序)以在第一表面上形成包括电连接到贯通电极的布线的上部布线层。然后，在从基底的第二表面去除牺牲层图案来形成开口之后，可在开口中形成要电连接到布线的贯通电极。
因此，由于贯通电极形成在从基底去除牺牲层图案的区域中，所以不会发生上部布线层的第一上部布线与贯通电极之间的未对准问题。此外，由于在执行布线工序(BEOL工序)之后形成贯通电极，所以可避免BEOL工序的高温下对贯通电极的热应力。此外，由于在对基底的背部执行平坦化工艺之后形成贯通电极，所以可防止贯通电极的诸如铜之类的导电材料在制造工艺中扩散到基底中。
附图说明
通过下面结合附图的详细描述，示例实施例将变得更容易理解。图1至图29代表在这里描述的非限制性示例实施例。
图1至图14是示出根据示例实施例的制造半导体装置的方法的剖视图。
图15至图17是示出根据示例实施例的制造半导体装置的方法的剖视图。
图18和图19是示出根据示例实施例的制造半导体装置的方法的剖视图。
图20至图23是示出根据示例实施例的制造半导体装置的方法的剖视图。
图24和图25是示出根据示例实施例的制造半导体装置的方法的剖视图。
图26是示出根据示例实施例的制造半导体装置的方法的剖视图。
图27示出另一示例实施例。
图28示出又一示例实施例。
图29示出再一示例实施例。
具体实施方式
在下文中将参照附图更充分地描述各种示例实施例，在附图中示出了示例实施例。然而，示例实施例可以用许多不同的形式来实施，且不应该解释为局限于在这里所提出的示例实施例。相反，提供这些示例实施例将使得本公开是彻底的和完整的，并将把示例实施例的范围充分地传达给本领域技术人员。在附图中，为了清晰起见，会夸大层和区域的尺寸和相对尺寸。
应该理解的是，当元件或层被称作“在”另一元件或层“上”、“连接到”或“结合到”另一元件或层时，该元件或层可以直接在另一元件或层上、直接连接到或直接结合到另一元件或层，或者可以存在中间元件或中间层。相反，当元件被称作“直接在”另一元件或层“上”、“直接连接到”或“直接结合到”另一元件或层时，不存在中间元件或中间层。相同的标号始终表示相同的元件。如在这里使用的，术语“和/或”包括一个或多个相关所列项的任意组合和所有组合。
应该理解的是，虽然术语“第一”、“第二”、“第三”等在这里可以用来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应该受这些术语的限制。这些术语仅用来将一个元件、组件、区域、层或者部分与另一区域、层或者部分区别开来。因此，在不脱离示例实施例的教导的情况下，在下面讨论的第一元件、组件、区域、层或者部分可被称为第二元件、组件、区域、层或者部分。
为了便于描述，在这里可使用空间相对术语，如“在...之下”、“下面的”、“下部的”、“在...上方”、“上面的”等，用来描述如在图中所示的一个元件或特征与其他元件或特征的关系。应该理解的是，空间相对术语意在包含除了在附图中描述的方位之外的装置在使用或操作中的不同方位。例如，如果附图中的装置被翻转，则描述为“在”其他元件或特征“下面的”或“之下”的元件随后将被定位为“在”其他元件或特征“上方”。因而，示例性术语“在...之下”可包括“在...上方”和“在...下方”两种方位。所述装置可被另外定位(旋转90度或者在其他方位)，并对在这里使用的空间相对描述符做出相应的解释。
这里使用的术语仅为了描述特定示例实施例的目的，而不意图限制示例实施例。如这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还应理解的是，当在本说明书中使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
在此参照作为理想示例性实施例(和中间结构)的示意图的剖视图来描述示例实施例。这样，预计会出现例如由制造技术和/或公差引起的图示的形状的变化。因此，示例实施例不应该被解释为局限于在此示出的区域的具体形状，而将包括例如由制造导致的形状偏差。例如，示出为矩形的注入区域将通常在其边缘具有倒圆或弯曲的特征和/或具有注入浓度的梯度，而不是从注入区域到非注入区域的二元变化。同样，通过注入形成的埋区会导致在埋区和通过其发生注入的表面之间的区域中的一些注入。因此，在图中示出的区域本质上是示意性的，它们的形状并不意图示出装置的区域的实际形状，也不意图限制示例实施例的范围。
除非另有定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与示例实施例所属领域的普通技术人员所通常理解的意思相同的意思。还将理解的是，除非在此明确地定义，否则诸如在通用字典中定义的术语应该被解释为具有与相关领域的环境中它们的意思一致的意思，而将不以理想的或者过于正式的含义来解释它们。
下文中，将参照附图来详细解释示例实施例。
示例实施例涉及制造半导体装置的方法。更具体地讲，示例实施例涉及制造在半导体基底中具有贯通电极的半导体装置的方法。
图1至图14是示出根据示例实施例的制造半导体装置的方法的剖视图。
参照图1，可准备其上形成有电路图案12的基底10。基底10可具有第一表面(例如，上表面)和与第一表面相对的第二表面(例如，底表面)。例如，基底10可以是单晶硅基底。
可在基底10的第一表面上形成电路图案12。可在基底10的第一表面上形成绝缘间层14，以覆盖电路图案12。可在绝缘间层14上形成蚀刻停止层(未示出)。
例如，电路图案12可包括晶体管、二极管、电容器等。电路图案12可构成电路元件。因此，半导体装置可以是包括在其中形成多个电路元件的半导体芯片。
电路元件可包括多个存储装置。存储装置的示例可以是易失性存储装置和非易失性存储装置。易失性存储装置的示例可以是DRAM、SRAM等。非易失性存储装置的示例可以是EPROM、EEPROM、闪存EEPROM等。
因此，可以执行晶片工序(FEOL(前道)工序)，以在基底10上形成电路图案12。
参照图2，第一开口20可形成在基底10中，以沿厚度方向从基底10的第一表面延伸。
第一开口20的形成包括在基底10上的绝缘间层14上形成光致抗蚀剂层(未示出)，然后将光致抗蚀剂层图案化以形成光致抗蚀剂图案(未示出)，所述光致抗蚀剂图案暴露用于将要形成贯通电极的区域。
可使用光致抗蚀剂图案作为蚀刻掩模来局部地蚀刻蚀刻停止层、绝缘间层和基底10，以形成第一开口20。例如，可以通过干蚀刻工艺或湿蚀刻工艺来形成第一开口20。考虑到贯通电极的长度、堆叠封装件的厚度等，可以确定第一开口的深度。然后，可以将光致抗蚀剂图案从基底10去除。
参照图3和图4，可形成牺牲层图案26来填充第一开口20。在示例实施例中，可在第一开口20中顺序地形成第一绝缘层22和牺牲层24。
具体来讲，可在第一开口20的侧壁和底表面上以及绝缘间层14的上表面上共形地形成第一绝缘层22。第一绝缘层22可将基底10与第一开口20内的导电材料绝缘。
第一绝缘层可包括氧化硅或碳掺杂的氧化硅。例如，可通过等离子体氧化工艺或化学气相沉积工艺来形成第一绝缘层。可使用TEOS层、臭氧TEOS层、USG层等来形成第一绝缘层。
然后，可在第一绝缘层22上形成牺牲层24以完全填充第一开口20。可使用相对于第一绝缘层22具有蚀刻选择性的绝缘材料来形成牺牲层24。例如，可使用SOD(旋涂介电)材料来形成牺牲层24。牺牲层24的蚀刻速率可以是第一绝缘层22的蚀刻速率的至少三倍。例如，在相同的湿蚀刻条件下，牺牲层24和第一绝缘层22的蚀刻选择性的范围可以在大约3∶1至大约20∶1。
然后，可将牺牲层24的上部去除，以在第一开口20中形成牺牲层图案26。例如，可通过化学机械抛光工艺、蚀刻工艺等将牺牲层24去除。如图4所示，可将牺牲层24的一部分去除来形成牺牲层图案26。可选地，可将绝缘间层14上的牺牲层24和第一绝缘层22部分地或全部去除来形成牺牲层图案。
参照图5至图7，可在基底10的第一表面上形成上部布线层38。可以执行布线工序(BEOL(后道)工序)，以在基底10的第一表面上形成上部布线层。
上部布线层38可包括上部布线32和36。上部布线可电连接到电路图案12和贯通电极。
具体来讲，可在绝缘间层14上形成第一金属间介电层30。可局部地蚀刻第一金属间介电层30和第一绝缘层22，以形成暴露下部布线16和牺牲层图案26的上表面的开口。可用导电材料来填充所述开口，以形成第一上部布线32。因此，可在牺牲层图案26和下部布线16上分别形成第一上部布线32。
可在第一金属间介电层30上形成第二金属间介电层34，然后，可在第二金属间介电层34中形成第二上部布线36。第二上部布线36可电连接到第一上部布线32。
可将第二金属间介电层34从暴露最上部的第二上部布线36的开口部分地去除。连接焊盘40可形成在开口中，以与最上部的第二上部布线36接触。
可选地，可将最上部的第二上部布线36用作连接焊盘。在这种情况下，第二金属间介电层34还可包括暴露最上部的第二上部布线36的保护层(未示出)。例如，保护层可包括聚酰亚胺。可通过保护层来暴露最上部的第二上部布线36(例如，连接焊盘)。连接构件(例如，凸起)可设置在最上部的第二上部布线36上，以电连接到另一半导体装置。
然后，为了从基底10的第二表面形成贯通电极，可使操作基底50附着到第二金属间介电层34。在形成贯通电极之后可将操作基底50从基底10去除。
参照图8至图10，可将基底10的第二表面(例如，底部表面)部分地去除，直到牺牲层图案26从基底10暴露。
首先，可将基底10的第二表面部分地去除，以暴露部分牺牲层图案26和牺牲层图案26上的第一绝缘层22。例如，可通过化学机械抛光工艺、蚀刻工艺等来去除基底10的第二表面。可部分地去除基底10的第二表面，以控制基底10的厚度。
然后，可在被部分地去除的基底10的第二表面上形成第二绝缘层60，以覆盖被暴露的牺牲层图案26和第一绝缘层22。可使用相对于牺牲层图案26具有蚀刻选择性的绝缘材料来形成第二绝缘层60。例如，牺牲层图案26的蚀刻速率可以是第二绝缘层60的蚀刻速率的至少三倍。第二绝缘层60的绝缘材料可以与第一绝缘层22的绝缘材料基本相同。第二绝缘层60可具有与第一绝缘层22的蚀刻速率相同的蚀刻速率。
然后，可将牺牲层图案26上的第二绝缘层60和第一绝缘层22部分地去除，以形成暴露牺牲层图案26的第二绝缘层图案62。例如，可通过化学机械抛光工艺或蚀刻工艺将第二绝缘层60和第一绝缘层22部分地去除。
参照图11，可将牺牲层图案26去除，以形成限定用于将要形成贯通电极的区域的第二开口21。
可通过湿蚀刻工艺、干蚀刻工艺等将牺牲层图案26去除。因此，可仅将牺牲层从基底10去除，从而第一绝缘层22留在第一开口22的侧壁上。可通过第二开口21暴露第一上部布线32。
参照图12，可在第二开口21中形成贯通电极72。
在示例实施例中，可在第二开口21的侧壁和底表面以及第二绝缘层图案62上共形地形成种子层70。在形成随后的导电层的镀覆工艺中可将种子层70用作电极。
可在种子层70上形成导电层(未示出)，以填充第二开口21。可使用具有相对低的电阻的金属来形成导电层。例如，可通过电镀工艺、无电镀工艺等来形成导电层。导电层可包括铜(Cu)、铝(Al)、金(Au)、钛(Ti)、钽(Ta)、钨(W)等。可单独使用这些材料或使用它们的组合。
然后，可将导电层图案化以在第二开口21中形成要被电连接到第一上部布线32的贯通电极72。可选地，可通过化学气相沉积工艺来形成贯通电极。
在本示例实施例中，在执行晶片工序(FEOL工序)以在基底10的第一表面上形成电路图案12并且牺牲层图案26形成在基底10中以从基底10的第一表面延伸之后，可执行布线工序(BEOL工序)以在基底10的第一表面(例如，上表面)上形成上部布线层38。然后，在将牺牲层图案26从基底10的第二表面去除来形成开口21之后，贯通电极72可形成在开口21中以被电连接到第一上部布线32。
因此，由于贯通电极形成在从基底去除牺牲层图案的区域中，所以不会发生上部布线层38的第一上部布线与贯通电极之间的未对准问题。
此外，由于在执行布线工序(BEOL工序)之后形成贯通电极72，所以可避免在BEOL工序的高温(例如，400℃)下对贯通电极72的热应力。因此，可在没有热应力的情况下使贯通电极72形成为具有期望的深度。
此外，由于在对基底的背部执行平坦化工艺后形成贯通电极72，所以可以防止贯通电极72的诸如铜之类的导电材料在制造工艺中扩散到基底。
参照图13和图14，可使用贯通电极来堆叠通过上述工艺形成的半导体装置。在下文中，可将堆叠的半导体装置称作第一半导体芯片和第二半导体芯片。
例如，可通过第一凸起80在第二半导体芯片上堆叠第一半导体芯片。第一凸起80可设置在第二半导体芯片的连接焊盘140上并可附着到第一半导体芯片的贯通电极72。
具体来讲，第一凸起80可通过回流工艺附着到第二半导体芯片的连接焊盘140，使得第一半导体芯片堆叠在第二半导体芯片上。相似地，第二凸起82可附着到安装基底200的连接焊盘220，使得第二半导体芯片安装在安装基底200上来形成堆叠封装件300。
因此，贯通电极72和172可附着到连接构件(例如，凸起80/82)，以电连接第一半导体芯片和第二半导体芯片。
然后，可以在安装基底200的上表面上形成密封构件250，以保护第一半导体芯片和第二半导体芯片免受外部影响。在将焊球240设置在安装基底200的下表面上的多个外部连接焊盘230上之后，可在模块基底(未示出)上安装堆叠封装件300以完成存储模块(未示出)。
图15至图17是示出根据示例实施例的制造半导体装置的方法的剖视图。除了形成贯通电极的工艺以外，本实施例与图1至图14的实施例基本相同。因此，将使用相同的附图标号来表示与在图1至图14中所描述元件相同或相似的元件，并且将为了简明而省略与上述元件有关的任何进一步的重复解释。
首先，可执行参照图1至图11示出的工艺，以形成沿基底的厚度方向从基底10的第二表面延伸的第二开口21。第一上部布线32可通过第二开口21的底表面暴露。
参照图15和图16，可在第二开口21的侧壁和底表面以及第二绝缘层图案62的上表面上共形地形成用来形成分隔件的第三绝缘层64。可使用具有优异的阶梯覆盖的绝缘材料来形成第三绝缘层64。例如，可使用氧化硅或氮化硅来形成第三绝缘层。然后，可对第三绝缘层64进行各向异性蚀刻，以在第二开口21的侧壁上形成分隔件66。
参照图17，可在第二开口21中的分隔件66上形成贯通电极72。
例如，可在第二开口21的底表面、分隔件66和第二绝缘层图案62上共形地形成种子层70。可在种子层70上形成导电层(未示出)来填充第二开口21。可使用具有相对低的电阻的金属来形成导电层。例如，可使用电镀工艺、无电镀工艺等来形成导电层。导电层可包括铜(Cu)、铝(Al)、金(Au)、铟(In)、镍(Ni)等。可单独使用这些材料或使用它们的组合。然后，可将导电层图案化，以在第二开口21中形成要被电连接到第一上部布线32的贯通电极72。
在本示例实施例中，在将牺牲层图案26去除以形成第二开口21之后，可在第二开口21的侧壁上形成分隔件66。可在第二开口21中的分隔件66上形成要被电连接到第一上部布线32的贯通电极72。
可通过去除牺牲层图案26来形成第二开口21。因此，可在第二开口21的侧壁上形成分隔件66，从而改善第二开口21的外形。
图18和图19是示出根据示例实施例的制造半导体装置的方法的剖视图。除了形成牺牲层图案的工序以外，本实施例与图1至图14的实施例基本相同。因此，将使用相同的附图标号来表示与在图1至图14中所描述元件相同或相似的元件，并且将为了简明而省略与上述元件有关的任何进一步的重复解释。
首先，可执行参照图1和图2示出的工艺，以形成沿基底的厚度方向从基底10的第一表面延伸的第一开口20。
参照图18和图19，可在第一开口20中形成牺牲层图案26。
可在第一开口20的侧壁和底表面上以及绝缘间层14的上表面和侧壁上形成第一绝缘层22。可在第一绝缘层22上形成牺牲层24来填充第一开口20。可使用相对于第一绝缘层22具有蚀刻选择性的绝缘材料来形成牺牲层24。
在本示例实施例中，可使牺牲层24形成为具有空隙25。因此，可使牺牲层24形成为局部地填充第一开口20。
然后，可将牺牲层24的上部去除，以在第一开口20中形成具有空隙25的牺牲层图案26。例如，可通过化学机械抛光工艺、蚀刻工艺等将牺牲层24去除。
然后，可执行与参照图5至图14示出的工艺相同或相似的工艺来形成半导体装置。
在本示例实施例中，在形成具有空隙25的牺牲层图案26之后，可执行布线工序(BEOL工序)，以在基底10的表面上形成上部布线层。
因此，尽管可以在相对高的温度下执行布线工序，但是牺牲层图案26的空隙25可减少或补偿布线工序过程中在高温下的热应力。
图20至图23是示出根据示例实施例的制造半导体装置的方法的剖视图。除了形成上部布线层之前形成额外的覆层以外，本实施例与图1至图14的实施例基本相同。因此，将使用相同的附图标号来表示与在图1至图14中所描述元件相同或相似的元件，并且将为了简明而省略与上述元件有关的任何进一步的重复解释。
首先，可执行参照图1至图4示出的工艺，以在将形成贯通电极的区域中形成牺牲层图案26。牺牲层图案26可沿基底10的厚度方向从基底10的第一表面延伸。
参照图20，可在牺牲层图案26上形成覆层28。例如，可使用氧化硅或氮化硅来形成覆层28。
参照图21和图23，可在覆层28上形成上部布线层38。
具体来讲，在第一金属间介电层30形成在覆层28上之后，第一上部布线32可形成在覆层28中(例如，延伸通过)或形成在覆层28上。第一上部布线32可形成在第一金属间介电层30中。因此，覆层28可设置在第一上部布线32与牺牲层图案26之间。
然后，可在第一金属间介电层30上形成第二金属间介电层34。第二上部布线36可形成在第二金属间介电层34中。
参照图22，可执行与参照图8至图11示出的工艺相同或相似的工艺来从基底10去除牺牲层图案26。在这种情况下，可与牺牲层图案26一起将覆层28部分地去除，以形成通过第二开口21的底表面暴露第一上部布线32的覆层图案29。
参照图23，可在第二开口21中形成贯通电极72。因此，可将贯通电极72电连接到被覆层图案29暴露的第一上部布线32。
在本示例实施例中，在形成覆层28之后，形成上部布线层38。然后，可与牺牲层图案26一起将覆层28部分地去除，以形成暴露第一上部布线32的第二开口21。
因此，可使用覆层28来进行用于去除牺牲层图案26的蚀刻工艺中的端点检测，从而改善第二开口21的外形。
图24和图25是示出根据示例实施例的制造半导体装置的方法的剖视图。除了形成贯通电极的工艺以外，本实施例与图20至图23的实施例基本相同。因此，将使用相同的附图标号来表示与在图20至图23中所描述元件相同或相似的元件，并且将省略与上述元件有关的任何进一步的重复解释。
首先，可执行参照图20至图22示出的工艺，从而将牺牲层图案26和覆层28的一部分去除以形成通过第二开口21的底表面暴露第一上部布线32的覆层图案29。
参照图24，可在第二开口21的侧壁上形成分隔件66。
具体来讲，可在第二开口21的侧壁和底表面以及第二绝缘层图案62的上表面上共形地形成用来形成分隔件的第三绝缘层(未示出)。可对第三绝缘层进行各向异性蚀刻，以在第二开口21的侧壁上形成分隔件66。
参照图25，可在第二开口21中的分隔件66上形成贯通电极72。
例如，可在第二开口21的底表面、分隔件66和第二绝缘层图案62上共形地形成种子层70。可在种子层70上形成导电层(未示出)，以填充第二开口21。可使用具有相对低的电阻的金属来形成导电层。然后，可将导电层图案化以在第二开口21中形成要被电连接到第一上部布线32的贯通电极72。
在本示例实施例中，在形成覆层28之后，可形成上部布线层38。可与牺牲层图案26一起将覆层28部分地去除，以形成暴露第一上部布线32的第二开口21。此外，在形成第二开口21之后，可在第二开口21的侧壁上形成分隔件66。可在第二开口21中的分隔件66上形成要被电连接到第一上部布线32的贯通电极72。
因此，可使用覆层28来进行用于去除牺牲层图案26的蚀刻工艺中的端点检测并且可在第二开口21的侧壁上形成分隔件66，从而改善第二开口21的外形。
图26是示出根据示例实施例的制造半导体装置的方法的剖视图。除了形成贯通电极的工艺以外，本实施例与图1至图14的实施例基本相同。因此，将使用相同的附图标号来表示与在图1至图14中所描述元件相同或相似的元件，并且将为了简明而省略与上述元件有关的任何进一步的重复解释。
首先，可以执行参照图1至图11示出的工艺，从而将牺牲层图案26从基底10去除，以形成限定用于将要形成贯通电极的区域的第二开口21。
参照图26，可在开口21中形成具有凹进75的贯通电极74。
例如，可在第二开口21中形成种子层70，并可在种子层70上形成导电层(未示出)，以部分地填充第二开口21。然后，可将导电层图案化，以在第二开口21中形成电连接到第一上部布线32的贯通电极74。
在本示例实施例中，贯通电极74可在其下部具有凹进。贯通电极74可具有环形横截面。可在贯通电极74上形成掩埋图案(未示出)来填充凹进。掩埋图案可包括绝缘材料或导电材料。例如，掩埋图案可包括旋涂玻璃(SOG)氧化物、可流动硅、钛、铝、多孔材料等。贯通电极74可具有杯形状。贯通电极74可起到用于电信号通道的接触插塞的作用。
图27示出了另一示例实施例。
如图27所示，这些示例实施例包括连接到存储控制器520的存储器510。存储器510可包括在上面讨论的存储装置。存储控制器520供应用来控制存储器的操作的输入信号。
图28示出了又一示例实施例。
参照图28，这些示例实施例包括与主机系统700连接的存储器。存储器510可包括上面讨论的存储装置。
主机系统700可包括诸如个人计算机、数码照相机、移动设备、游戏机、通讯设备等的电子产品。主机系统700供应用于控制存储器510的操作的输入信号。可将存储器510用作数据存储介质。
图29示出再一示例实施例。这些示例实施例代表便携式装置600。便携式装置600可以是MP3播放器、视频播放器、视音频组合播放器等。如所示出的，便携式装置600可包括存储器510和存储控制器520。存储器可包括在上面讨论的存储装置。便携式装置600还可包括编码/解码器EDC 610、展示组件620和接口670。通过EDC 610，数据(视频、音频等)经由存储控制器520输入到存储器510或从存储器510输出。
如上面所提到的，在制造根据示例实施例的半导体装置的方法中，可在这样的区域中形成牺牲层图案，即，在所述区域中，贯通电极将形成为沿基底的厚度方向从基底的第一表面延伸。可执行布线工序(BEOL工序)，以在第一表面上形成包括电连接到贯通电极的布线的上部布线层。然后，在将牺牲层图案从基底的第二表面去除来形成开口之后，可在开口中形成将要电连接到布线的贯通电极。
因此，由于贯通电极形成在从基底去除牺牲层图案的区域中，所以不会发生上部布线层的第一上部布线与贯通电极之间的未对准问题。此外，由于在执行布线工序(BEOL工序)之后形成贯通电极，所以可以避免在BEOL工序的高温下对贯通电极的热应力。此外，由于在对基底的背部执行平坦化工艺之后形成贯通电极，所以可以防止贯通电极的诸如铜之类的导电材料在制造工艺中扩散到基底中。
以上内容是对示例实施例的举例说明并且不被解释为对示例实施例的限制。尽管已经描述了一些示例实施例，但是本领域的技术人员应该容易地意识到，在本质上不脱离本发明的新颖的教导和优点的情况下，可以对示例实施例进行多种修改。因此，所有这样的修改都意图被包括在权利要求限定的示例实施例的范围内。在权利要求书中，功能性限定意图覆盖在这里被描述成执行所述功能的结构，不但覆盖结构上的等同物而且覆盖等同的结构。因此，应该理解，以上内容是对各种示例实施例的举例说明并且不被解释为局限于所公开的具体的示例实施例，并且意图将所公开的示例实施例的各种修改和其他示例实施例包括在权利要求书的范围内。

Claims (20)

1.一种制造半导体装置的方法，所述方法包括以下步骤：
准备具有第一表面和与第一表面相对的第二表面的基底；
在基底的将形成贯通电极的区域中形成牺牲层图案，所述牺牲层图案沿基底的厚度方向从基底的第一表面延伸；
在基底的第一表面上形成上部布线层，所述上部布线层包括位于牺牲层图案上的布线；
将基底的第二表面部分地去除以暴露牺牲层图案；
从基底的第二表面去除牺牲层图案，以形成暴露所述布线的第一开口；以及
在第一开口中形成要电连接到所述布线的贯通电极。
2.如权利要求1所述的方法，其中，形成牺牲层图案的步骤包括：
在基底中形成第二开口，所述第二开口沿基底的厚度方向从第一表面延伸；
在第二开口的侧壁和底表面上形成第一绝缘层；
在第一绝缘层上形成牺牲层；以及
部分地去除牺牲层，以形成部分地填充第二开口的牺牲层图案。
3.如权利要求2所述的方法，其中，使用相对于第一绝缘层具有蚀刻选择性的绝缘材料来形成牺牲层。
4.如权利要求3所述的方法，其中，牺牲层的蚀刻速率是第一绝缘层的蚀刻速率的至少三倍。
5.如权利要求3所述的方法，其中，牺牲层和第一绝缘层的蚀刻选择性的范围在3∶1至20∶1。
6.如权利要求2所述的方法，其中，形成牺牲层图案的步骤包括通过化学机械抛光工艺或蚀刻工艺部分地去除牺牲层。
7.如权利要求1所述的方法，所述方法还包括在形成暴露所述布线的第一开口之后在第一开口的侧壁上形成分隔件。
8.如权利要求1所述的方法，其中，牺牲层图案具有形成其中的空隙。
9.如权利要求1所述的方法，所述方法还包括在牺牲层图案上形成覆层。
10.如权利要求9所述的方法，其中，形成暴露所述布线的第一开口的步骤包括当从基底去除牺牲层图案时部分地去除覆层。
11.如权利要求1所述的方法，其中，沿第一开口的外形共形地形成贯通电极，以部分地填充第一开口。
12.如权利要求11所述的方法，其中，贯通电极在其下部包括凹进。
13.如权利要求1所述的方法，其中，部分地去除基底的第二表面以暴露牺牲层图案的步骤包括：
部分地去除基底的第二表面，以暴露牺牲层图案的一部分；
在基底的第二表面上形成第二绝缘层，以覆盖暴露的牺牲层图案；以及
部分地去除第二绝缘层，以形成暴露牺牲层图案的下部的第二绝缘层图案。
14.一种制造半导体装置的方法，所述方法包括以下步骤：
提供具有第一凹进的基底；
在基底的第一表面上形成牺牲层图案，所述牺牲层图案填充在第一凹进中；
在基底的第一表面上形成上部布线层；
通过部分地去除基底的第二表面来暴露牺牲层图案，所述第二表面与基底的第一表面相对；
通过从第一凹进去除暴露的牺牲层图案来暴露上部布线层；以及
形成连接到暴露的上部布线层的贯通电极，其中，贯通电极电连接到暴露的上部布线层中的布线。
15.如权利要求14所述的方法，所述方法还包括：
在暴露所述上部布线层之后，在第一凹进的侧壁上共形地形成绝缘层；
蚀刻绝缘层，以在第一凹进的侧壁上形成分隔件；以及
在分隔件上形成种子层，贯通电极形成在种子层上。
16.如权利要求14所述的方法，其中，在基底的第一表面上形成牺牲层图案的步骤包括用用来形成牺牲层图案的绝缘材料填充第一凹进。
17.如权利要求16所述的方法，其中，牺牲层图案具有空隙。
18.如权利要求14所述的方法，所述方法还包括：
在形成上部布线层之前，在牺牲层图案上形成覆层，
其中，暴露上部布线层的步骤包括部分地去除所述覆层。
19.如权利要求18所述的方法，所述方法还包括：
在暴露上部布线层之后，在第一凹进和覆层的侧壁上共形地形成绝缘层；
蚀刻绝缘层，以在第一凹进的侧壁上形成分隔件；
在分隔件上形成种子层，贯通电极形成在种子层上。
20.如权利要求19所述的方法，所述方法还包括在贯通电极中形成第二凹进。
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