KR100440259B1 - 반도체 소자의 듀얼 다마신 패턴 형성 방법 - Google Patents
반도체 소자의 듀얼 다마신 패턴 형성 방법 Download PDFInfo
- Publication number
- KR100440259B1 KR100440259B1 KR10-2001-0081296A KR20010081296A KR100440259B1 KR 100440259 B1 KR100440259 B1 KR 100440259B1 KR 20010081296 A KR20010081296 A KR 20010081296A KR 100440259 B1 KR100440259 B1 KR 100440259B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- via hole
- dual damascene
- insulating layer
- damascene pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000009977 dual effect Effects 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011800 void material Substances 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (4)
- 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 제 1 절연막을 형성하는 단계와,상기 제 1 절연막에 소정 영역에 비아홀을 형성하는 단계와,상기 비아홀에 보이드가 발생되도록 상기 제 1 절연막 상에 제 2 절연막을 형성하는 단계와,상기 제 2 절연막에 트렌치를 형성하면서 상기 비아홀을 개방시켜 상기 트렌치 및 상기 비아홀로 이루어지는 듀얼 다마신 패턴을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 절연막 상에 식각 정지층을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성 방법.
- 제 2 항에 있어서,상기 식각 정지층은 Si3N4로 형성되는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 2 절연막에 트렌치를 형성하는 단계에서 상기 비아홀에 증착된 제 2 절연막이 동시에 제거되는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0081296A KR100440259B1 (ko) | 2001-12-19 | 2001-12-19 | 반도체 소자의 듀얼 다마신 패턴 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0081296A KR100440259B1 (ko) | 2001-12-19 | 2001-12-19 | 반도체 소자의 듀얼 다마신 패턴 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030050778A KR20030050778A (ko) | 2003-06-25 |
KR100440259B1 true KR100440259B1 (ko) | 2004-07-15 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0081296A KR100440259B1 (ko) | 2001-12-19 | 2001-12-19 | 반도체 소자의 듀얼 다마신 패턴 형성 방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100440259B1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100702790B1 (ko) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | 반도체 소자 제조방법 |
CN111403333A (zh) * | 2020-03-24 | 2020-07-10 | 合肥晶合集成电路有限公司 | 一种半导体结构及其制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000056457A (ko) * | 1999-02-22 | 2000-09-15 | 김영환 | 반도체장치의 배선 형성방법 |
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2001
- 2001-12-19 KR KR10-2001-0081296A patent/KR100440259B1/ko active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000056457A (ko) * | 1999-02-22 | 2000-09-15 | 김영환 | 반도체장치의 배선 형성방법 |
Also Published As
Publication number | Publication date |
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KR20030050778A (ko) | 2003-06-25 |
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