JP2008503029A - データ保持ラッチを含むメモリ素子 - Google Patents

データ保持ラッチを含むメモリ素子 Download PDF

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Publication number
JP2008503029A
JP2008503029A JP2007527283A JP2007527283A JP2008503029A JP 2008503029 A JP2008503029 A JP 2008503029A JP 2007527283 A JP2007527283 A JP 2007527283A JP 2007527283 A JP2007527283 A JP 2007527283A JP 2008503029 A JP2008503029 A JP 2008503029A
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JP
Japan
Prior art keywords
state
bit line
value
output
memory
Prior art date
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Pending
Application number
JP2007527283A
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English (en)
Japanese (ja)
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JP2008503029A5 (enExample
Inventor
ラマラジュ、ラビンドララジ
ピー． フークストラ、ジョージ
ユー． ケンケア、プラシャント
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NXP USA Inc
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NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2008503029A publication Critical patent/JP2008503029A/ja
Publication of JP2008503029A5 publication Critical patent/JP2008503029A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
JP2007527283A 2004-06-10 2005-05-05 データ保持ラッチを含むメモリ素子 Pending JP2008503029A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/865,274 US7349266B2 (en) 2004-06-10 2004-06-10 Memory device with a data hold latch
PCT/US2005/015858 WO2006001910A2 (en) 2004-06-10 2005-05-05 Memory device with a data hold latch

Publications (2)

Publication Number Publication Date
JP2008503029A true JP2008503029A (ja) 2008-01-31
JP2008503029A5 JP2008503029A5 (enExample) 2008-06-26

Family

ID=35505511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007527283A Pending JP2008503029A (ja) 2004-06-10 2005-05-05 データ保持ラッチを含むメモリ素子

Country Status (6)

Country Link
US (1) US7349266B2 (enExample)
EP (1) EP1915502A4 (enExample)
JP (1) JP2008503029A (enExample)
KR (1) KR20070029193A (enExample)
CN (1) CN101023237B (enExample)
WO (1) WO2006001910A2 (enExample)

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* Cited by examiner, † Cited by third party
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TWI261167B (en) * 2004-12-29 2006-09-01 Via Networking Technologies In Method and related apparatus for realizing two-port synchronous memory device
US7623404B2 (en) * 2006-11-20 2009-11-24 Freescale Semiconductor, Inc. Memory device having concurrent write and read cycles and method thereof
US8189408B2 (en) * 2009-11-17 2012-05-29 Freescale Semiconductor, Inc. Memory device having shifting capability and method thereof
US8456945B2 (en) * 2010-04-23 2013-06-04 Advanced Micro Devices, Inc. 10T SRAM for graphics processing
WO2016031023A1 (ja) * 2014-08-28 2016-03-03 株式会社 東芝 半導体記憶装置
US9384825B2 (en) * 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
KR20180058478A (ko) * 2016-11-24 2018-06-01 에스케이하이닉스 주식회사 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법
US20210098057A1 (en) * 2019-09-26 2021-04-01 Qualcomm Incorporated Sram low-power write driver
US20210327501A1 (en) * 2020-04-20 2021-10-21 Stmicroelectronics International N.V. Lower power memory write operation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0485789A (ja) * 1990-07-27 1992-03-18 Nec Corp メモリ装置
JPH10308662A (ja) * 1997-05-09 1998-11-17 Sharp Corp Ｃｍｏｓ論理回路およびその駆動方法
JP2000133724A (ja) * 1998-10-27 2000-05-12 Fujitsu Ltd 半導体記憶装置
JP2001312888A (ja) * 2000-04-28 2001-11-09 Texas Instr Japan Ltd 半導体記憶装置

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JP2501344B2 (ja) * 1987-12-26 1996-05-29 株式会社東芝 デ―タ転送回路
US5185722A (en) * 1989-11-22 1993-02-09 Sharp Kabushiki Kaisha Semiconductor memory device having a memory test circuit
JPH04216392A (ja) * 1990-12-18 1992-08-06 Mitsubishi Electric Corp ブロックライト機能を備える半導体記憶装置
JPH06103781A (ja) * 1992-09-21 1994-04-15 Sharp Corp メモリセル回路
JP3317746B2 (ja) * 1993-06-18 2002-08-26 富士通株式会社 半導体記憶装置
JP3547466B2 (ja) * 1993-11-29 2004-07-28 株式会社東芝 メモリ装置、シリアル‐パラレルデータ変換回路、メモリ装置にデータを書き込む方法、およびシリアル‐パラレルデータ変換方法
US5515315A (en) * 1993-12-24 1996-05-07 Sony Corporation Dynamic random access memory
KR0165159B1 (ko) * 1994-07-28 1999-02-01 사또 후미오 반도체 기억 장치
US5677703A (en) * 1995-01-06 1997-10-14 Texas Instruments Incorporated Data loading circuit for digital micro-mirror device
US5612713A (en) * 1995-01-06 1997-03-18 Texas Instruments Incorporated Digital micro-mirror device with block data loading
JP2900854B2 (ja) * 1995-09-14 1999-06-02 日本電気株式会社 半導体記憶装置
EP1014270A4 (en) * 1996-10-24 2004-10-06 Mitsubishi Electric Corp MICROCOMPUTER WITH MEMORY AND PROCESSOR ON THE SAME CHIP
JP3615009B2 (ja) * 1997-02-12 2005-01-26 株式会社東芝 半導体記憶装置
KR100245276B1 (ko) * 1997-03-15 2000-02-15 윤종용 버스트 모드 성능을 갖는 랜덤 억세스 메모리 장치 및 그의 동작 방법
JP3592887B2 (ja) * 1997-04-30 2004-11-24 株式会社東芝 不揮発性半導体記憶装置
JPH1139877A (ja) * 1997-07-15 1999-02-12 Mitsubishi Electric Corp 半導体記憶装置
JPH11224492A (ja) * 1997-11-06 1999-08-17 Toshiba Corp 半導体記憶装置、不揮発性半導体記憶装置及びフラッシュメモリ
US5936898A (en) * 1998-04-02 1999-08-10 Vanguard International Semiconductor Corporation Bit-line voltage limiting isolation circuit
JPH11317074A (ja) * 1998-04-30 1999-11-16 Nec Corp ワード線制御回路
US6195301B1 (en) 1998-12-30 2001-02-27 Texas Instruments Incorporated Feedback driver for memory array bitline
JP2000207900A (ja) * 1999-01-12 2000-07-28 Mitsubishi Electric Corp 同期型半導体記憶装置
US6324110B1 (en) * 1999-03-12 2001-11-27 Monolithic Systems Technology, Inc. High-speed read-write circuitry for semi-conductor memory
KR100319892B1 (ko) * 1999-06-30 2002-01-10 윤종용 데이터 출력 패스의 데이터 라인 상의 데이터를 래치하는 회로를 구비하는 반도체 메모리 장치 예컨대, 동기식 디램 및 이 반도체 메모리 장치의 데이터 래칭 방법
JP3586591B2 (ja) * 1999-07-01 2004-11-10 シャープ株式会社 冗長機能を有する不揮発性半導体メモリ装置のための不良アドレスデータ記憶回路および不良アドレスデータ書き込み方法
US6262920B1 (en) * 1999-08-25 2001-07-17 Micron Technology, Inc. Program latch with charge sharing immunity
JP2003157682A (ja) * 2001-11-26 2003-05-30 Mitsubishi Electric Corp 不揮発性半導体記憶装置
JP2003233986A (ja) 2002-02-07 2003-08-22 Sony Corp 半導体記憶装置
US6570799B1 (en) * 2002-03-14 2003-05-27 United Memories, Inc. Precharge and reference voltage technique for dynamic random access memories
US6674673B1 (en) * 2002-08-26 2004-01-06 International Business Machines Corporation Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture
US6845059B1 (en) * 2003-06-26 2005-01-18 International Business Machines Corporation High performance gain cell architecture
JP2005056452A (ja) 2003-08-04 2005-03-03 Hitachi Ltd メモリ及び半導体装置
JP4309304B2 (ja) * 2004-04-23 2009-08-05 株式会社東芝 半導体記憶装置及びその制御方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0485789A (ja) * 1990-07-27 1992-03-18 Nec Corp メモリ装置
JPH10308662A (ja) * 1997-05-09 1998-11-17 Sharp Corp Ｃｍｏｓ論理回路およびその駆動方法
JP2000133724A (ja) * 1998-10-27 2000-05-12 Fujitsu Ltd 半導体記憶装置
JP2001312888A (ja) * 2000-04-28 2001-11-09 Texas Instr Japan Ltd 半導体記憶装置

Also Published As

Publication number Publication date
CN101023237A (zh) 2007-08-22
US20050286327A1 (en) 2005-12-29
EP1915502A4 (en) 2009-08-05
EP1915502A2 (en) 2008-04-30
WO2006001910A3 (en) 2006-09-14
WO2006001910A2 (en) 2006-01-05
KR20070029193A (ko) 2007-03-13
US7349266B2 (en) 2008-03-25
CN101023237B (zh) 2010-05-05

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