CN101023237B - 具有数据保持锁存器的存储器设备及其操作方法 - Google Patents

具有数据保持锁存器的存储器设备及其操作方法 Download PDF

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Publication number
CN101023237B
CN101023237B CN2005800189027A CN200580018902A CN101023237B CN 101023237 B CN101023237 B CN 101023237B CN 2005800189027 A CN2005800189027 A CN 2005800189027A CN 200580018902 A CN200580018902 A CN 200580018902A CN 101023237 B CN101023237 B CN 101023237B
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China
Prior art keywords
bit line
output
coupled
write
value
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Expired - Lifetime
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CN2005800189027A
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English (en)
Chinese (zh)
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CN101023237A (zh
Inventor
拉文德拉拉·拉玛拉朱
乔治·P.·霍克斯特拉
普拉山特·U.·肯卡莱
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101023237A publication Critical patent/CN101023237A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
CN2005800189027A 2004-06-10 2005-05-05 具有数据保持锁存器的存储器设备及其操作方法 Expired - Lifetime CN101023237B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/865,274 US7349266B2 (en) 2004-06-10 2004-06-10 Memory device with a data hold latch
US10/865,274 2004-06-10
PCT/US2005/015858 WO2006001910A2 (en) 2004-06-10 2005-05-05 Memory device with a data hold latch

Publications (2)

Publication Number Publication Date
CN101023237A CN101023237A (zh) 2007-08-22
CN101023237B true CN101023237B (zh) 2010-05-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2005800189027A Expired - Lifetime CN101023237B (zh) 2004-06-10 2005-05-05 具有数据保持锁存器的存储器设备及其操作方法

Country Status (6)

Country Link
US (1) US7349266B2 (enExample)
EP (1) EP1915502A4 (enExample)
JP (1) JP2008503029A (enExample)
KR (1) KR20070029193A (enExample)
CN (1) CN101023237B (enExample)
WO (1) WO2006001910A2 (enExample)

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TWI261167B (en) * 2004-12-29 2006-09-01 Via Networking Technologies In Method and related apparatus for realizing two-port synchronous memory device
US7623404B2 (en) * 2006-11-20 2009-11-24 Freescale Semiconductor, Inc. Memory device having concurrent write and read cycles and method thereof
US8189408B2 (en) * 2009-11-17 2012-05-29 Freescale Semiconductor, Inc. Memory device having shifting capability and method thereof
US8456945B2 (en) * 2010-04-23 2013-06-04 Advanced Micro Devices, Inc. 10T SRAM for graphics processing
WO2016031023A1 (ja) * 2014-08-28 2016-03-03 株式会社 東芝 半導体記憶装置
US9384825B2 (en) * 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
KR20180058478A (ko) * 2016-11-24 2018-06-01 에스케이하이닉스 주식회사 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법
US20210098057A1 (en) * 2019-09-26 2021-04-01 Qualcomm Incorporated Sram low-power write driver
US20210327501A1 (en) * 2020-04-20 2021-10-21 Stmicroelectronics International N.V. Lower power memory write operation

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US5966319A (en) * 1997-07-15 1999-10-12 Mitsubishi Denki Kabushiki Kaisha Static memory device allowing correct data reading
CN1233837A (zh) * 1998-04-30 1999-11-03 日本电气株式会社 字线控制电路
US6470467B2 (en) * 1999-01-12 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester

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JPH0485789A (ja) * 1990-07-27 1992-03-18 Nec Corp メモリ装置
JPH04216392A (ja) * 1990-12-18 1992-08-06 Mitsubishi Electric Corp ブロックライト機能を備える半導体記憶装置
JPH06103781A (ja) * 1992-09-21 1994-04-15 Sharp Corp メモリセル回路
JP3317746B2 (ja) * 1993-06-18 2002-08-26 富士通株式会社 半導体記憶装置
JP3547466B2 (ja) * 1993-11-29 2004-07-28 株式会社東芝 メモリ装置、シリアル‐パラレルデータ変換回路、メモリ装置にデータを書き込む方法、およびシリアル‐パラレルデータ変換方法
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JP3615009B2 (ja) * 1997-02-12 2005-01-26 株式会社東芝 半導体記憶装置
KR100245276B1 (ko) * 1997-03-15 2000-02-15 윤종용 버스트 모드 성능을 갖는 랜덤 억세스 메모리 장치 및 그의 동작 방법
JP3592887B2 (ja) * 1997-04-30 2004-11-24 株式会社東芝 不揮発性半導体記憶装置
JP3756285B2 (ja) * 1997-05-09 2006-03-15 シャープ株式会社 Ｃｍｏｓ論理回路およびその駆動方法
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JP3852729B2 (ja) * 1998-10-27 2006-12-06 富士通株式会社 半導体記憶装置
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US6324110B1 (en) * 1999-03-12 2001-11-27 Monolithic Systems Technology, Inc. High-speed read-write circuitry for semi-conductor memory
KR100319892B1 (ko) * 1999-06-30 2002-01-10 윤종용 데이터 출력 패스의 데이터 라인 상의 데이터를 래치하는 회로를 구비하는 반도체 메모리 장치 예컨대, 동기식 디램 및 이 반도체 메모리 장치의 데이터 래칭 방법
JP3586591B2 (ja) * 1999-07-01 2004-11-10 シャープ株式会社 冗長機能を有する不揮発性半導体メモリ装置のための不良アドレスデータ記憶回路および不良アドレスデータ書き込み方法
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US5966319A (en) * 1997-07-15 1999-10-12 Mitsubishi Denki Kabushiki Kaisha Static memory device allowing correct data reading
US5936898A (en) * 1998-04-02 1999-08-10 Vanguard International Semiconductor Corporation Bit-line voltage limiting isolation circuit
CN1233837A (zh) * 1998-04-30 1999-11-03 日本电气株式会社 字线控制电路
US6470467B2 (en) * 1999-01-12 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester

Also Published As

Publication number Publication date
CN101023237A (zh) 2007-08-22
US20050286327A1 (en) 2005-12-29
EP1915502A4 (en) 2009-08-05
EP1915502A2 (en) 2008-04-30
WO2006001910A3 (en) 2006-09-14
WO2006001910A2 (en) 2006-01-05
KR20070029193A (ko) 2007-03-13
US7349266B2 (en) 2008-03-25
JP2008503029A (ja) 2008-01-31

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Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

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Granted publication date: 20100505

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