JP2008503029A5 - - Google Patents

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Publication number
JP2008503029A5
JP2008503029A5 JP2007527283A JP2007527283A JP2008503029A5 JP 2008503029 A5 JP2008503029 A5 JP 2008503029A5 JP 2007527283 A JP2007527283 A JP 2007527283A JP 2007527283 A JP2007527283 A JP 2007527283A JP 2008503029 A5 JP2008503029 A5 JP 2008503029A5
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JP
Japan
Prior art keywords
bit line
output
coupled
value
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007527283A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008503029A (ja
Filing date
Publication date
Priority claimed from US10/865,274 external-priority patent/US7349266B2/en
Application filed filed Critical
Publication of JP2008503029A publication Critical patent/JP2008503029A/ja
Publication of JP2008503029A5 publication Critical patent/JP2008503029A5/ja
Pending legal-status Critical Current

Links

JP2007527283A 2004-06-10 2005-05-05 データ保持ラッチを含むメモリ素子 Pending JP2008503029A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/865,274 US7349266B2 (en) 2004-06-10 2004-06-10 Memory device with a data hold latch
PCT/US2005/015858 WO2006001910A2 (en) 2004-06-10 2005-05-05 Memory device with a data hold latch

Publications (2)

Publication Number Publication Date
JP2008503029A JP2008503029A (ja) 2008-01-31
JP2008503029A5 true JP2008503029A5 (enExample) 2008-06-26

Family

ID=35505511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007527283A Pending JP2008503029A (ja) 2004-06-10 2005-05-05 データ保持ラッチを含むメモリ素子

Country Status (6)

Country Link
US (1) US7349266B2 (enExample)
EP (1) EP1915502A4 (enExample)
JP (1) JP2008503029A (enExample)
KR (1) KR20070029193A (enExample)
CN (1) CN101023237B (enExample)
WO (1) WO2006001910A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI261167B (en) * 2004-12-29 2006-09-01 Via Networking Technologies In Method and related apparatus for realizing two-port synchronous memory device
US7623404B2 (en) * 2006-11-20 2009-11-24 Freescale Semiconductor, Inc. Memory device having concurrent write and read cycles and method thereof
US8189408B2 (en) * 2009-11-17 2012-05-29 Freescale Semiconductor, Inc. Memory device having shifting capability and method thereof
US8456945B2 (en) * 2010-04-23 2013-06-04 Advanced Micro Devices, Inc. 10T SRAM for graphics processing
WO2016031023A1 (ja) * 2014-08-28 2016-03-03 株式会社 東芝 半導体記憶装置
US9384825B2 (en) * 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
KR20180058478A (ko) * 2016-11-24 2018-06-01 에스케이하이닉스 주식회사 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법
US20210098057A1 (en) * 2019-09-26 2021-04-01 Qualcomm Incorporated Sram low-power write driver
US20210327501A1 (en) * 2020-04-20 2021-10-21 Stmicroelectronics International N.V. Lower power memory write operation

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JP2501344B2 (ja) * 1987-12-26 1996-05-29 株式会社東芝 デ―タ転送回路
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