JP2008258411A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
JP2008258411A
JP2008258411A JP2007099221A JP2007099221A JP2008258411A JP 2008258411 A JP2008258411 A JP 2008258411A JP 2007099221 A JP2007099221 A JP 2007099221A JP 2007099221 A JP2007099221 A JP 2007099221A JP 2008258411 A JP2008258411 A JP 2008258411A
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Prior art keywords
lead
semiconductor device
sealing resin
semiconductor chip
die pad
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JP2007099221A
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Japanese (ja)
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JP2008258411A5 (enExample
Inventor
Yasumasa Kasuya
泰正 糟谷
基治 ▲芳▼我
Motoharu Haga
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2007099221A priority Critical patent/JP2008258411A/ja
Priority to US12/078,772 priority patent/US7608930B2/en
Publication of JP2008258411A publication Critical patent/JP2008258411A/ja
Publication of JP2008258411A5 publication Critical patent/JP2008258411A5/ja
Pending legal-status Critical Current

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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JP2007099221A 2007-04-05 2007-04-05 半導体装置および半導体装置の製造方法 Pending JP2008258411A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007099221A JP2008258411A (ja) 2007-04-05 2007-04-05 半導体装置および半導体装置の製造方法
US12/078,772 US7608930B2 (en) 2007-04-05 2008-04-04 Semiconductor device and method of manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
JP2007099221A JP2008258411A (ja) 2007-04-05 2007-04-05 半導体装置および半導体装置の製造方法

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JP2008258411A true JP2008258411A (ja) 2008-10-23
JP2008258411A5 JP2008258411A5 (enExample) 2010-05-06

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Cited By (17)

* Cited by examiner, † Cited by third party
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JP2011151069A (ja) * 2010-01-19 2011-08-04 Dainippon Printing Co Ltd 樹脂付リードフレーム、リードフレーム、半導体装置および樹脂付リードフレームの製造方法
JP2012109459A (ja) * 2010-11-18 2012-06-07 Dainippon Printing Co Ltd リードフレームおよびリードフレームの製造方法
JP2012114354A (ja) * 2010-11-26 2012-06-14 Dainippon Printing Co Ltd リードフレームおよびリードフレームの製造方法
JP2013236113A (ja) * 2013-08-27 2013-11-21 Dainippon Printing Co Ltd 樹脂付リードフレーム、リードフレーム、半導体装置および樹脂付リードフレームの製造方法
JP2013243409A (ja) * 2013-08-27 2013-12-05 Dainippon Printing Co Ltd 樹脂付リードフレーム、リードフレーム、半導体装置および樹脂付リードフレームの製造方法
JP2014207481A (ja) * 2014-07-18 2014-10-30 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5358089B2 (ja) * 2007-12-21 2013-12-04 スパンション エルエルシー 半導体装置
US8106502B2 (en) * 2008-11-17 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with plated pad and method of manufacture thereof
US8569877B2 (en) * 2009-03-12 2013-10-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
TWI392065B (zh) * 2009-06-08 2013-04-01 乾坤科技股份有限公司 電子元件封裝模組
EP2361000A1 (en) * 2010-02-11 2011-08-24 Nxp B.V. Leadless chip package mounting method and carrier
US8329509B2 (en) * 2010-04-01 2012-12-11 Freescale Semiconductor, Inc. Packaging process to create wettable lead flank during board assembly
TWI419290B (zh) 2010-10-29 2013-12-11 日月光半導體製造股份有限公司 四方扁平無引腳封裝及其製作方法
US8502363B2 (en) * 2011-07-06 2013-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with solder joint enhancement element and related methods
US8674487B2 (en) 2012-03-15 2014-03-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages with lead extensions and related methods
US9653656B2 (en) 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
US8716066B2 (en) * 2012-07-31 2014-05-06 Freescale Semiconductor, Inc. Method for plating a semiconductor package lead
US9059379B2 (en) 2012-10-29 2015-06-16 Advanced Semiconductor Engineering, Inc. Light-emitting semiconductor packages and related methods
JP6244147B2 (ja) * 2013-09-18 2017-12-06 エスアイアイ・セミコンダクタ株式会社 半導体装置の製造方法
US9773722B1 (en) 2014-05-07 2017-09-26 UTAC Headquarters Pte. Ltd. Semiconductor package with partial plating on contact side surfaces
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US9741642B1 (en) 2014-05-07 2017-08-22 UTAC Headquarters Pte. Ltd. Semiconductor package with partial plating on contact side surfaces
CN105895611B (zh) * 2014-12-17 2019-07-12 恩智浦美国有限公司 具有可湿性侧面的无引线方形扁平半导体封装
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US9806043B2 (en) 2016-03-03 2017-10-31 Infineon Technologies Ag Method of manufacturing molded semiconductor packages having an optical inspection feature
DE102017212457A1 (de) * 2017-07-20 2019-01-24 Infineon Technologies Ag Halbleitergehäuse mit Nickelplattierung und Verfahren zum Herstellen desselben
US20200227343A1 (en) * 2019-01-11 2020-07-16 Chang Wah Technology Co., Ltd. Semiconductor device package
KR102811924B1 (ko) 2019-03-08 2025-05-23 실리코닉스 인코포레이티드 측벽 도금을 갖는 반도체 패키지
JP7368055B2 (ja) * 2019-06-21 2023-10-24 ローム株式会社 半導体装置、および、半導体装置の実装構造
KR102564558B1 (ko) * 2021-11-30 2023-08-08 해성디에스 주식회사 프리 몰드 기판 및 프리 몰드 기판의 제조 방법

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63151056A (ja) * 1986-12-16 1988-06-23 Matsushita Electronics Corp リ−ドフレ−ムの製造方法
JPH06350013A (ja) * 1993-06-11 1994-12-22 Hitachi Constr Mach Co Ltd リードフレーム及び半導体装置並びに半導体装置の製造方法
JPH0758274A (ja) * 1993-08-20 1995-03-03 Hitachi Constr Mach Co Ltd リードフレーム及び半導体装置並びにリードフレーム用帯材
JP2002026223A (ja) * 2000-07-05 2002-01-25 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置およびその製造方法
JP2003158235A (ja) * 2001-11-20 2003-05-30 Mitsui High Tec Inc 半導体装置の製造方法
JP2003218307A (ja) * 2002-01-24 2003-07-31 Nec Kansai Ltd リード成形装置
JP2004349728A (ja) * 1999-04-29 2004-12-09 “ドリー・ペー”ライセンシング・ベー・ベー カプセル化電子部品、特に集積回路の製造方法
JP2005033043A (ja) * 2003-07-08 2005-02-03 New Japan Radio Co Ltd リードフレームおよび半導体装置並びにそれらの製造方法
JP2005191158A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
JP2006165411A (ja) * 2004-12-10 2006-06-22 New Japan Radio Co Ltd 半導体装置およびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4329678B2 (ja) 2004-11-11 2009-09-09 株式会社デンソー 半導体装置に用いるリードフレームの製造方法
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
US7608916B2 (en) * 2006-02-02 2009-10-27 Texas Instruments Incorporated Aluminum leadframes for semiconductor QFN/SON devices

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63151056A (ja) * 1986-12-16 1988-06-23 Matsushita Electronics Corp リ−ドフレ−ムの製造方法
JPH06350013A (ja) * 1993-06-11 1994-12-22 Hitachi Constr Mach Co Ltd リードフレーム及び半導体装置並びに半導体装置の製造方法
JPH0758274A (ja) * 1993-08-20 1995-03-03 Hitachi Constr Mach Co Ltd リードフレーム及び半導体装置並びにリードフレーム用帯材
JP2004349728A (ja) * 1999-04-29 2004-12-09 “ドリー・ペー”ライセンシング・ベー・ベー カプセル化電子部品、特に集積回路の製造方法
JP2002026223A (ja) * 2000-07-05 2002-01-25 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置およびその製造方法
JP2003158235A (ja) * 2001-11-20 2003-05-30 Mitsui High Tec Inc 半導体装置の製造方法
JP2003218307A (ja) * 2002-01-24 2003-07-31 Nec Kansai Ltd リード成形装置
JP2005033043A (ja) * 2003-07-08 2005-02-03 New Japan Radio Co Ltd リードフレームおよび半導体装置並びにそれらの製造方法
JP2005191158A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
JP2006165411A (ja) * 2004-12-10 2006-06-22 New Japan Radio Co Ltd 半導体装置およびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US9887331B2 (en) 2010-03-30 2018-02-06 Dai Nippon Printing Co., Ltd. LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate
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US9899583B2 (en) 2010-11-02 2018-02-20 Dai Nippon Printing Co., Ltd. Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements
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