TWI392065B - 電子元件封裝模組 - Google Patents

電子元件封裝模組 Download PDF

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Publication number
TWI392065B
TWI392065B TW098119053A TW98119053A TWI392065B TW I392065 B TWI392065 B TW I392065B TW 098119053 A TW098119053 A TW 098119053A TW 98119053 A TW98119053 A TW 98119053A TW I392065 B TWI392065 B TW I392065B
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TW
Taiwan
Prior art keywords
electronic component
package module
component package
lead frame
cover
Prior art date
Application number
TW098119053A
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English (en)
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TW201044517A (en
Inventor
Da Jung Chen
Chi Feng Huang
Yi Tsung Chen
Huei Ren You
Jeng Jen Li
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Cyntec Co Ltd
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Publication date
Application filed by Cyntec Co Ltd filed Critical Cyntec Co Ltd
Priority to TW098119053A priority Critical patent/TWI392065B/zh
Priority to US12/783,792 priority patent/US8253041B2/en
Publication of TW201044517A publication Critical patent/TW201044517A/zh
Application granted granted Critical
Publication of TWI392065B publication Critical patent/TWI392065B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description

電子元件封裝模組
本發明是有關於一種封裝結構，且特別是有關於一種電子元件封裝模組。
在現今資訊發達的社會中，電子產品遍佈於日常生活中，且伴隨著電子科技不斷地演進，電子產品朝向輕、薄、短、小的趨勢設計。因此，在封裝(Package)的領域亦對應開發出許多高密度的封裝技術，例如系統式封裝(System In A Package)等封裝技術。系統式封裝即為系統整合化構裝，也就是將電子元件整合於單一封裝體內，其內包含被動元件、記憶體及電子連接器等電子元件。
圖1繪示習知之一種系統式封裝結構的剖面圖。請參照圖1，習知的系統式封裝結構100是將多個晶片110配置於線路板120上，且晶片110藉由多條導線140電性連接至線路板120，並利用一封裝膠體130包覆這些晶片110。系統式封裝結構100具有晶片110間電性連接線路短及線路配置體積小等優點。
然而，系統式封裝結構100暴露於空氣中時，封裝膠體130易吸收空氣中的水氣，以致於系統式封裝結構100與其他電子元件焊接時封裝膠體130易因受熱而產生爆米花效應。此外，由於系統式封裝結構100是利用封裝膠體130包覆晶片110，因此，當晶片110損壞或者是導線140斷路(或短路)時，無法重工且不易進行元件的損壞分析(failure analysis)。另外，由於封裝膠體130及線路板120的導熱性質甚差，因此晶片110於運作中產生之熱量易累積在系統式封裝結構100中，以致於晶片110容易因過熱而運算錯誤或失效。
本發明提供一種具有良好散熱效率的電子元件封裝模組。
本發明提出一種電子元件封裝模組，包括一導線架、一絕緣層以及至少一電子元件。導線架為一圖案化金屬片，導線架具有一第一表面、相對於第一表面的一第二表面以及連通第一表面與第二表面的一貫槽，導線架藉由貫槽定義出一承載部與位於承載部外圍的多個引腳部，導線架之第二表面曝露於電子元件封裝模組的外部。絕緣層配置於貫槽中，且絕緣層具有實質上與第一表面切齊的一第三表面以及實質上與第二表面切齊的一第四表面。電子元件配置於第一表面上且與導線架電性連接。
在本發明之一實施例中，絕緣層的熱傳導係數大於或等於0.75W/(m‧K)。
在本發明之一實施例中，貫槽將承載部劃分成彼此分離的多個子承載部。
在本發明之一實施例中，子承載部分別與至少部分的引腳部相連接。
在本發明之一實施例中，導線架的第一表面與第二表面之間的距離實質上小於或等於毫米。
在本發明之一實施例中，導線架為一單層結構。
在本發明之一實施例中，導線架具有多個溝槽，且溝槽與貫槽連通且絕緣層填滿於溝槽中。
在本發明之一實施例中，溝槽形成在導線架的第一表面或第二表面。
在本發明之一實施例中，溝槽的橫切面形狀為U形、半圓形、V形、方形、梯形、香菇形、階梯形、鳩尾槽形或不規則形。
在本發明之一實施例中，溝槽分別位於引腳部的端部。
在本發明之一實施例中，導線架具有連接第一表面與第二表面之多個側壁，溝槽形成在側壁上。
在本發明之一實施例中，溝槽不連通第一表面及第二表面。
在本發明之一實施例中，溝槽連通第一表面及第二表面。
在本發明之一實施例中，電子元件封裝模組更包括一蓋體，其具有一容置凹槽，蓋體配置於第一表面上，且導線架與絕緣層密封容置凹槽而形成一容置空間，且電子元件位於容置空間中。
在本發明之一實施例中，蓋體的材質包括金屬、樹脂、樹膠、塑膠或陶瓷。
在本發明之一實施例中，蓋體的材質為導電材料，且電子元件封裝模組更包括一絕緣框體，絕緣框體設置於導線架與蓋體的邊緣之間。
在本發明之一實施例中，導線架具有多個溝槽且蓋體的材質為導電材料，引腳部之鄰近蓋體的一邊緣上形成溝槽，絕緣層之填滿於溝槽中並位於蓋體的邊緣與導線架之間。
在本發明之一實施例中，電子元件封裝模組更包括一框體，框體連接於導線架與蓋體的邊緣之間，且框體與蓋體的邊緣之間存在一超音波焊接界面。
在本發明之一實施例中，電子元件封裝模組更包括一黏著層，其連接於導線架與蓋體的邊緣之間。
在本發明之一實施例中，電子元件封裝模組更包括至少一夾扣條，其配置於容置空間外，夾扣條具有二端部與連接二端部的一中心部，二端部固定於絕緣層上，中心部向蓋體之遠離導線架的一頂面延伸，並承靠於頂面上。
在本發明之一實施例中，電子元件封裝模組更包括至少一接合結構，其具有一柱體與一擋止部，柱體具有相對的一第一端與一第二端，第一端與蓋體相連，第二端貫穿絕緣層並與擋止部相連，擋止部承靠於絕緣層的第四表面上。
在本發明之一實施例中，電子元件封裝模組更包括一卡合框，其配置於絕緣層上，且卡合框干涉緊配於蓋體的邊緣內。
在本發明之一實施例中，電子元件封裝模組更包括一軟性膠材，其填充於容置空間內。
在本發明之一實施例中，蓋體的材質為金屬材料，且電子元件之一表面直接與蓋體之一內表面接觸。
在本發明之一實施例中，各引腳部具有突出於絕緣層的一外接端。
基於上述，本發明是以蓋體取代習知的封裝膠體，故可避免習知技術中封裝膠體易吸收水氣的問題。此外，本發明是以導線架作為承載電子元件的基板，因此，電子元件於運作中所產生的熱可經由導線架迅速地傳導至外界。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖2A、圖2B與圖2C分別繪示本發明一實施例之電子元件封裝模組的示意圖、剖面圖與爆炸圖，圖2D繪示圖2A之導線架的示意圖。圖3A為圖2A之電子元件封裝模組的一種變化，圖3B為圖3A之電子元件封裝模組的爆炸圖。
請同時參照圖2A、圖2B與圖2C，本實施例之電子元件封裝模組200包括一導線架(lead frame)210、一絕緣層220、至少一電子元件230以及一蓋體240。導線架210為一圖案化金屬片，導線架210具有一第一表面212、相對於第一表面212的一第二表面214以及連通第一表面212與第二表面214的一貫槽216。在本實施例中，導線架210的第一表面212與第二表面214之間的距離H1實質上小於或等於0.5毫米，換言之，導線架210的厚度實質上小於或等於0.5毫米。本實施例中，導線架210之第二表面214曝露於封裝模組200的外部。導線架210為一單層結構且材質例如為銅。
請參照圖2D，導線架210藉由貫槽216定義出一承載部C與位於承載部C之外圍的多個引腳部L。詳細而言，貫槽216亦可將承載部C劃分成彼此分離的多個子承載部C1，且子承載部C1分別與部分的引腳部L相連接，其餘的引腳部L與承載部C分離。
請同時參照圖2A、圖2B與圖2C，絕緣層220配置於貫槽216中，且絕緣層220具有一第三表面222與一第四表面224，其中第三表面222實質上切齊於第一表面212，第四表面224實質上切齊於第二表面214。由前述可知，絕緣層220的第三表面222與第四表面224之間的距離H2(即絕緣層220的厚度)可實質上小於或等於0.5毫米。絕緣層220的熱傳導係數大於或等於0.75W/(m‧K)，絕緣層220的材質例如為樹脂或是其他熱傳導係數高的絕緣材料。值得注意的是，導線架210之各個引腳部L具有突出於絕緣層220的一外接端，以與下一階之電子裝置(例如：主機板)電性連接。
請參照圖2B與圖2C，電子元件230配置於第一表面212上且與導線架210電性連接。詳細而言，電子元件230可直接配置於第一表面212上或者透過一承載器280(如印刷線路板或陶瓷基板)配置於第一表面212上。再者，電子元件230可以是僅配置於承載部C上、同時配置於承載部C與絕緣層220上或同時配置於承載部C、引腳部L與絕緣層220上。電子元件230可為主動元件(例如：半導體元件232)或被動元件(例如：扼流器234)，且可為裸晶粒(die)、晶片(chip)或插件型態，並可以覆晶接合、打線或表面黏著等技術與導線架210電性連接。電子元件230例如是半導體元件232(如脈寬調變控制晶片)時，可透過多條導線250電性連接至導線架210之引腳部L，導線250的材質例如為金、銅或鋁，且可具有封裝膠體270包覆半導體元件232與導線250。電子元件230例如是扼流器(chock)234時，可利用表面黏著技術與導線架210電性連接。值得注意的是，在本實施例中，可將運作時會產生較多熱量的電子元件(如扼流器234或高功率晶片等)直接配置於導線架210上，以透過導線架210直接散熱，而具有良好的散熱效率。
請參照圖2B，蓋體240具有一容置凹槽242，蓋體240配置於導線架210之第一表面212上，且導線架210與絕緣層220密封容置凹槽242而形成一容置空間S，且電子元件230位於容置空間S中。蓋體240的材質例如是金屬、樹脂、樹膠、塑膠、陶瓷或是其他高熱傳導係數的材料。另外，為保護容置空間S內的電子元件230，可選擇性地在容置空間S內填充一軟性膠材(未繪示)。
值得注意的是，由於本實施例是以蓋體240取代習知的封裝膠體，因此，本實施例可避免習知技術中封裝膠體易吸收水氣的問題。此外，本實施例的蓋體240可獨立拆卸以及重新安裝，因此，本實施例之電子元件封裝模組200容易重工且容易進行元件的損壞分析。另外，由於本實施例是以導線架210作為承載電子元件230的基板且導線架210之第二表面214曝露於封裝模組200的外部，因此，電子元件230於運作中產生的熱可經由導線架210迅速地傳導至外界。並且，本實施例可採用金屬材質的蓋體240，如此一來，電子元件封裝模組200的外部結構幾乎是由導熱性質極佳的金屬(導線架210與蓋體240)所構成的，而使導熱效果提升，且金屬材質的蓋體240可提供電磁波遮蔽之效果。
再者，由於本實施例中絕緣層220採用熱傳導係數大於或等於0.75 W/(m．K)的材質，使得子承載部C1上的電子元件230的熱量可透過絕緣層220快速地分散到其餘的子承載部C1及引腳部L，而使整體封裝模組200之熱分布均勻，以提昇散熱效率。
請參照圖3A與圖3B，當蓋體240的材質為導電材料時，可在導線架210與蓋體240的邊緣244之間設置一絕緣框體260，以使導線架210與蓋體240彼此電性絕緣。絕緣框體260與絕緣層220例如為一體成型結構。值得注意的是，蓋體240的邊緣244是指蓋體240之與導線架210相鄰的邊緣(即蓋體240的下緣)。再者，當蓋體240的材質為金屬材料時，可將運作時會產生較多熱量的電子元件(例如：扼流器234)之一表面234a直接與蓋體240之一內表面242a(如圖5所示)接觸，使蓋體240作為扼流器234之散熱器，而將扼流器234的熱透過蓋體240迅速地傳導至外界。
圖4A～圖4J繪示圖2D之導線架的多種變化結構的局部示意圖。值得注意的是，圖4A～圖4J是繪示圖2D的導線架210之位於區域A的部分。此外，在圖4A～圖4J的實施例中所提及的絕緣層即為圖2A～圖2C中的絕緣層220。本實施例中，導線架210更可具有多個溝槽(如圖4A～圖4J中之212a、214a、216b~216f)，且溝槽與貫槽216連通且絕緣層(未繪示)填滿於溝槽中。溝槽可形成於導線架210之至少一表面(如第一表面212、第二表面214或連接第一表面212與第二表面214之側壁216a)上，溝槽使導線架210之表面形成一凹陷部及一突出部。在不影響電性的情況下，溝槽可以選擇性地形成在導線架210的承載部C或是引腳部L上。由於溝槽與貫槽216連通，因此，絕緣層之位於貫槽216中的部分可直接連接絕緣層之位於溝槽中的部分。如此一來，溝槽可增加導線架210與絕緣層的接觸面積，以增加導線架210與絕緣層的接合力。此外，在引腳部L上形成溝槽可加強絕緣層固定引腳部L的效果。而以下將例舉多種設計以說明溝槽之設置位置，且以下所例舉的設計僅為舉例說明，並非用以限定本發明。
請參照圖4A，溝槽212a形成在導線架210的第一表面212且未貫穿導線架210，溝槽212a可以選擇性地形成在導線架210的承載部C或是引腳部L上。當蓋體240的材質為導電材料時，可在引腳部L之鄰近蓋體240的邊緣244的部分上形成多個溝槽212a(如圖5所示)，並使絕緣層220填滿於溝槽212a中。如此一來，絕緣層220可位於蓋體240的邊緣244與導線架210之間，以使蓋體240與導線架210電性絕緣。
請參照圖4B，溝槽214a形成在導線架210的第二表面214且未貫穿導線架210，溝槽214a可以選擇性地形成在導線架210的承載部C或是引腳部L上。請參照圖4C，係結合圖4B與圖4A的實施例，分別在導線架210的第一表面212與第二表面214上分別形成多個溝槽212a以及多個溝槽214a。
請參照圖4D，溝槽216b形成在導線架210的側壁216a且溝槽216b不連通第一表面212及第二表面214，溝槽216b可以選擇性地形成在導線架210的承載部C或是引腳部L上。本實施例中，部分溝槽216b是位於引腳部L的端部E(即引腳部L面向承載部C之表面)之側壁216a上，部分溝槽216b是位於承載部C之側壁216a上。
在圖4E中，二溝槽216c分別位於一引腳部L的相對二側壁216a上，且溝槽216c皆連通第一表面212。在圖4F中，二溝槽216d分別位於一引腳部L的相對二側壁216a上，且溝槽216d皆連通第二表面214。請參照圖4G，係結合圖4E與圖4F的實施例，二溝槽216c分別位於一引腳部L的相對二側壁216a上，且溝槽216c皆連通第一表面212。另外，二溝槽216d分別位於引腳部L的側壁216a上，且溝槽216d皆連通第二表面214。
請參照圖4H，溝槽216e形成在導線架210的單一側壁216a且溝槽216e同時連通第一表面212及第二表面214，使溝槽216e旁形成一頸縮部N。請參照圖4I，溝槽216e及溝槽216f分別形成在導線架210之引腳部L的相對二側壁216a上。溝槽216e及溝槽216f同時連通第一表面212及第二表面214，且溝槽216e及溝槽216f之間具有一頸縮部N。
請參照圖4J，溝槽216g形成在導線架210的側壁216a且溝槽216g連通第一表面212及第二表面214。本實施例中，溝槽216g是位於引腳部L的端部E(即引腳部L面向承載部C之表面)之側壁216a上。
圖6A～圖6I繪示本發明一實施例之導線架的溝槽的橫切面形狀的示意圖。此外，在圖4A～圖4J的實施例中，溝槽的橫切面形狀例如為半圓形(如圖6A所示)、U形(如圖6B所示)、V形(如圖6C所示)、方形(如圖6D所示)、梯形(如圖6E所示)、鳩尾槽形(如圖6F所示)、階梯形(如圖6G所示)、香菇形(如圖6H所示)或不規則形(如圖6I所示)。
以下將介紹將圖2A的蓋體240固定在導線架210上的多種方法，且以下所例舉的多種方法僅為舉例說明，並非用以限定本發明。
圖7繪示本發明一實施例之電子元件封裝模組的示意圖。請參照圖7，當蓋體240的材質為樹脂、樹膠或塑膠時，可在導線架210與蓋體240的邊緣244之間配置一框體710，框體710的材質為樹脂、樹膠或塑膠。然後，對框體710以及蓋體240的邊緣244進行超音波焊接，並於框體710與蓋體240的邊緣244之間生成一超音波焊接界面I。
圖8繪示本發明一實施例之電子元件封裝模組的示意圖。請參照圖8，可在蓋體240的邊緣244與導線架210之間設置一黏著層810。
圖9A繪示本發明一實施例之電子元件封裝模組的示意圖，圖9B繪示圖9A之電子元件封裝模組的側視圖。請同時參照圖9A與圖9B，可在電子元件封裝模組200的容置空間外配置二夾扣條910。各夾扣條910具有二端部912、914與連接二端部912、914的一中心部916，其中二端部912、914固定於絕緣層220上，中心部916向蓋體240之遠離導線架210的一頂面246延伸，並承靠於頂面246上。在本實施例中，二夾扣條910分別配置於電子元件封裝模組200的相對二側面202、204。
圖10A繪示本發明一實施例之電子元件封裝模組的示意圖，圖10B繪示圖10A之電子元件封裝模組的側視圖。圖11A繪示本發明一實施例之電子元件封裝模組的示意圖，圖11B繪示圖11A之電子元件封裝模組的側視圖。請同時參照圖10A與圖10B，可在蓋體240上設置多個接合結構1010。接合結構1010具有一柱體1012與一擋止部1014，柱體1012具有相對的一第一端1012a與一第二端1012b，第一端1012a與蓋體240相連，第二端1012b貫穿絕緣層220並與擋止部1014相連，擋止部1014承靠於絕緣層220的第四表面224上。接合結構1010例如為一卡榫(如圖10A所示)或一鉚釘(如圖11A與圖11B所示)。
圖12A繪示本發明一實施例之電子元件封裝模組的爆炸圖，圖12B繪示圖12A之電子元件封裝模組的剖面圖。請同時參照圖12A與圖12B，可在絕緣層220上配置一卡合框1210，且使蓋體240的邊緣244與卡合框1210干涉緊配。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．系統式封裝結構
110．．．晶片
120．．．線路板
130．．．封裝膠體
140．．．導線
200．．．電子元件封裝模組
202、204．．．側面
210．．．導線架
212．．．第一表面
212a、214a．．．溝槽
214．．．第二表面
216．．．貫槽
216a．．．側壁
216b、216c、216d、216e、216f、216g．．．溝槽
220．．．絕緣層
222．．．第三表面
224．．．第四表面
230．．．電子元件
232．．．半導體元件
234．．．扼流器
234a．．．表面
240．．．蓋體
242．．．容置凹槽
242a．．．內表面
244．．．邊緣
246．．．頂面
250．．．導線
260．．．絕緣框體
270．．．封裝膠體
280．．．承載器
710．．．框體
810．．．黏著層
910．．．夾扣條
912、914、E．．．端部
916．．．中心部
1010．．．接合結構
1012．．．柱體
1012a．．．第一端
1012b．．．第二端
1014．．．擋止部
1210．．．卡合框
A．．．區域
C．．．承載部
C1．．．子承載部
H1、H2．．．距離
I．．．超音波焊接界面
L．．．引腳部
N．．．頸縮部
S．．．容置空間
圖1繪示習知之一種系統式封裝結構的剖面圖。
圖2A、圖2B與圖2C分別繪示本發明一實施例之電子元件封裝模組的示意圖、剖面圖與爆炸圖，圖2D繪示圖2A之導線架的示意圖。
圖3A為圖2A之電子元件封裝模組的一種變化，圖3B為圖3A之電子元件封裝模組的爆炸圖。
圖4A～圖4J繪示圖2D之導線架的多種變化結構的局部示意圖。
圖5繪示本發明一實施例之具有圖4A之導線架的電子元件封裝模組的剖面圖。
圖6A～圖6I繪示本發明一實施例之導線架的第一溝槽或第二溝槽的橫切面形狀的示意圖。
圖7繪示本發明一實施例之電子元件封裝模組的示意圖。
圖8繪示本發明一實施例之電子元件封裝模組的示意圖。
圖9A繪示本發明一實施例之電子元件封裝模組的示意圖，圖9B繪示圖9A之電子元件封裝模組的側視圖。
圖10A繪示本發明一實施例之電子元件封裝模組的示意圖，圖10B繪示圖10A之電子元件封裝模組的側視圖。
圖11A繪示本發明一實施例之電子元件封裝模組的示意圖，圖11B繪示圖11A之電子元件封裝模組的側視圖。
圖12A繪示本發明一實施例之電子元件封裝模組的爆炸圖，圖12B繪示圖12A之電子元件封裝模組的剖面圖。
200．．．電子元件封裝模組
210．．．導線架
212．．．第一表面
214．．．第二表面
216．．．貫槽
220．．．絕緣層
222．．．第三表面
224．．．第四表面
230．．．電子元件
232．．．半導體元件
234．．．扼流器
240．．．蓋體
242．．．容置凹槽
250．．．導線
270．．．封裝膠體
280．．．承載器
C．．．承載部
H1、H2．．．距離
L．．．引腳部
S．．．容置空間

Claims (25)

  1. 一種電子元件封裝模組，包括：一導線架，該導線架為一圖案化金屬片，該導線架具有一第一表面、相對於該第一表面的一第二表面以及連通該第一表面與該第二表面的一貫槽，該導線架藉由該貫槽定義出一承載部與位於該承載部外圍的多個引腳部，該導線架之該第二表面曝露於該電子元件封裝模組的外部；一絕緣層，配置於該貫槽中，且該絕緣層具有實質上與該第一表面切齊的一第三表面以及實質上與該第二表面切齊的一第四表面；以及至少一電子元件，配置於該第一表面上且與該導線架電性連接。
  2. 如申請專利範圍第1項所述之電子元件封裝模組，其中該絕緣層的熱傳導係數大於或等於0.75W/(m‧K)。
  3. 如申請專利範圍第1項所述之電子元件封裝模組，其中該貫槽將該承載部劃分成彼此分離的多個子承載部。
  4. 如申請專利範圍第3項所述之電子元件封裝模組，其中該些子承載部分別與至少部分的該些引腳部相連接。
  5. 如申請專利範圍第1項所述之電子元件封裝模組，其中該導線架的該第一表面與該第二表面之間的距離實質上小於或等於0.5毫米。
  6. 如申請專利範圍第1項所述之電子元件封裝模組，其中該導線架為一單層結構。
  7. 如申請專利範圍第1項所述之電子元件封裝模組，其中該導線架具有多個溝槽，且該些溝槽與該貫槽連通且該絕緣層填滿於該些溝槽中。
  8. 如申請專利範圍第7項所述之電子元件封裝模組，其中該些溝槽形成在該導線架的該第一表面或第二表面。
  9. 如申請專利範圍第7項所述之電子元件封裝模組，其中該些溝槽的橫切面形狀為U形、半圓形、V形、方形、梯形、香菇形、階梯形、鳩尾槽形或不規則形。
  10. 如申請專利範圍第7項所述之電子元件封裝模組，其中該些溝槽分別位於該些引腳部的端部，該些端部面向該承載部。
  11. 如申請專利範圍第7項所述之電子元件封裝模組，其中該導線架具有連接該第一表面與該第二表面之多個側壁，該些溝槽形成在該些側壁上。
  12. 如申請專利範圍第11項所述之電子元件封裝模組，其中該些溝槽不連通該第一表面及第二表面。
  13. 如申請專利範圍第11項所述之電子元件封裝模組，其中該些溝槽連通該第一表面及第二表面。
  14. 如申請專利範圍第1項所述之電子元件封裝模組，更包括一蓋體，該蓋體具有一容置凹槽，該蓋體配置於該第一表面上，且該導線架與該絕緣層密封該容置凹槽而形成一容置空間，且該電子元件位於該容置空間中。
  15. 如申請專利範圍第14項所述之電子元件封裝模組，其中該蓋體的材質包括金屬、樹脂、樹膠、塑膠或陶瓷。
  16. 如申請專利範圍第14項所述之電子元件封裝模組，其中該蓋體的材質為導電材料，且該電子元件封裝模組更包括一絕緣框體，該絕緣框體設置於該導線架與該蓋體的邊緣之間。
  17. 如申請專利範圍第14項所述之電子元件封裝模組，其中該導線架具有多個溝槽且該蓋體的材質為導電材料，該些引腳部之鄰近該蓋體的一邊緣上形成該些溝槽，該絕緣層之填滿於該些溝槽中並位於該蓋體的邊緣與該導線架之間。
  18. 如申請專利範圍第14項所述之電子元件封裝模組，更包括一框體，該框體連接於該導線架與該蓋體的邊緣之間，且該框體與該蓋體的邊緣之間存在一超音波焊接界面。
  19. 如申請專利範圍第14項所述之電子元件封裝模組，更包括一黏著層，連接於該導線架與該蓋體的邊緣之間。
  20. 如申請專利範圍第14項所述之電子元件封裝模組，更包括至少一夾扣條，配置於該容置空間外，該夾扣條具有二端部與連接該二端部的一中心部，該二端部固定於該絕緣層上，該中心部向該蓋體之遠離該導線架的一頂面延伸，並承靠於該頂面上。
  21. 如申請專利範圍第14項所述之電子元件封裝模組，更包括至少一接合結構，具有一柱體與一擋止部，該柱體具有相對的一第一端與一第二端，該第一端與該蓋體相連，該第二端貫穿該絕緣層並與該擋止部相連，該擋止部承靠於該絕緣層的該第四表面上。
  22. 如申請專利範圍第14項所述之電子元件封裝模組，更包括一卡合框，配置於該絕緣層上，且該卡合框干涉緊配於該蓋體的邊緣內。
  23. 如申請專利範圍第14項所述之電子元件封裝模組，更包括一軟性膠材，填充於該容置空間內。
  24. 如申請專利範圍第14項所述之電子元件封裝模組，其中該蓋體的材質為金屬材料，且該電子元件之一表面直接與該蓋體之一內表面接觸。
  25. 如申請專利範圍第1項所述之電子元件封裝模組，其中各該引腳部具有突出於該絕緣層的一外接端。
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