JP2008198988A - プラズマ処理方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
Abstract
【解決手段】半導体基板206の上に積層化された薄膜(ゲート絶縁膜205、導電膜204、マスク層203、反射防止膜202)と、該反射防止膜上に形成されたフォトレジストマスクパターン201を有する被処理材をゲート電極を形成するためにエッチング処理するにあたって、前記マスクパターン201のエッチング処理する前に、窒素ガスまたは、窒素ガスと堆積性ガスとの混合雰囲気をプラズマ化することによって該マスクパターン201にプラズマキュア処理を行い、該マスクパターン201の表面と側面の凹凸を減少させた後、該マスクパターン201より下層の積層化された薄膜202、203、204をプラズマエッチング処理する。
【選択図】図6
Description
Claims (16)
- 半導体基板上に積層された複数層の薄膜と、積層化された薄膜の上に設けたフォトレジストマスクパターンとを有する被処理材を、ゲート電極を形成するためにプラズマエッチング装置を用いてプラズマ処理する方法において、
窒素の元素を含むガスをプラズマ化することによって前記フォトレジストマスクパターンにプラズマキュア処理を行いフォトレジストマスクパターンの表面と側面の凹凸を減少させるキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いて該フォトレジストマスクパターンの下に設けた積層化された薄膜層をプラズマエッチング処理するエッチング処理工程とを備えた
ことを特徴とするプラズマ処理方法。 - 半導体基板上に積層された複数層の薄膜と、積層化された薄膜の上に設けたフォトレジストマスクパターンとを有する被処理材を、ゲート電極を形成するためにプラズマエッチング装置を用いてプラズマ処理する方法において、
窒素の元素を含むガスをプラズマ化することによって前記フォトレジストマスクパターンにプラズマキュア処理を行い、前記フォトレジストマスクパターンの表面と側面の凹凸を減少させたる第1のキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いて前記フォトレジストマスクパターン直下の薄膜層をプラズマエッチング処理する第1のエッチング処理工程と、
前記フォトレジストマスクパターンに再度プラズマキュア処理を行いフォトレジストマスクパターン表面と側面の凹凸を減少させる第2のキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いてプラズマエッチング処理を行った前記薄膜層のさらに下に設けた薄膜層をプラズマエッチング処理する第2のエッチング処理工程と、
を有し、これ以降、前記フォトレジストマスクパターンの第2のプラズマキュア処理工程と積層化された薄膜の第2のプラズマエッチング処理工程を交互に実施する
ことを特徴とするプラズマ処理方法。 - 半導体基板上に積層された複数層の薄膜と、積層化された薄膜の上に設けたフォトレジストマスクパターンとを有する被処理材を、ゲート電極を形成するためにプラズマエッチング装置を用いてプラズマ処理する方法において、
窒素の元素を含むガスと堆積性ガスとの混合雰囲気をプラズマ化することによって前記フォトレジストマスクパターンにプラズマキュア処理を行い、プラズマキュア処理中のフォトレジストマスクパターンの縦エッチングレートを抑制しながらフォトレジストマスクパターンの表面と側面の凹凸を減少させるキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いてフォトレジストマスクパターンの下に設けた積層化された薄膜層をプラズマエッチング処理するエッチング処理工程とを有する
ことを特徴とするプラズマ処理方法。 - 半導体基板上に積層された複数層の薄膜と、積層化された薄膜の上に設けたフォトレジストマスクパターンとを有する被処理材を、ゲート電極を形成するためにプラズマエッチング装置を用いてプラズマ処理する方法において、
窒素の元素を含むガスと堆積性ガスとの混合雰囲気をプラズマ化することによって前記フォトレジストマスクパターンにプラズマキュア処理を行い、プラズマキュア処理中のフォトレジストマスクパターンの縦エッチングレートを抑制しながら、フォトレジストマスクパターンの表面と側面の凹凸を減少させる第1のキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いてフォトレジストマスクパターンの直下に設けた薄膜層をプラズマエッチング処理する第1のエッチング処理工程と、
前記フォトレジストマスクパターンに再度プラズマキュア処理を行い、前記フォトレジストマスクパターン表面と側面の凹凸を減少させる第2のキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いてプラズマエッチング処理を行った前記薄膜層のさらに下に設けた薄膜層をプラズマエッチング処理する譜代2のエッチング処理工程と、
を有し、これ以降、前記フォトレジストマスクパターンの第2のプラズマキュア処理工程と積層化された薄膜の第2のプラズマエッチング処理工程を交互に実施する
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記窒素の元素を含むガスは、窒素ガス(N2)である
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記プラズマキュア処理に用いられるガスに臭化水素または希ガス元素もしくはハロゲン元素のガスの内の少なくともいずれか1以上のガスを添加し、前記フォトレジストマスクパターンにプラズマキュア処理を行い、前記フォトレジストマスクパターンの表面と側面の凹凸を減少させる
ことを特徴とするプラズマ処理方法。 - 請求項3または請求項4記載のプラズマ処理方法において、
前記堆積性ガスは、メタン(CH4)、トリフルオロメタン(CHF3)、ジフルオロメタン(CH2F2)、フルオロメタン(CH3F)、他のフルオロカーボンガス(CXFY)、四フッ化ケイ素(SiF4)の中から少なくとも1種以上のガスを含む
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記積層化された薄膜は、多結晶Si層、単結晶Si層、Si化合物、金属層、金属化合物層の内の少なくとも1層以上含む
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記積層化された薄膜は、MOS(Metal Oxide Semiconductor)トランジスタのゲート電極を形成する層を少なくとも1層以上含む
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記該プラズマエッチング処理に用いられるガスは、塩素、臭化水素、六フッ化硫黄、四フッ化炭素、三塩化ホウ素、三フッ化窒素、酸素、希ガスの内の少なくとも1種以上のガスを含む
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記フォトレジストマスクパターンのプラズマキュア処理圧力は、0.1Pa以上100Pa以下である
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記フォトレジストマスクパターンのプラズマキュア処理における被処理材に印加するRFバイアス電力は、0W以上100W以下である
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記フォトレジストマスクパターンのプラズマキュア処理における被処理材に印加するRFバイアス電力を特に0Wとし、前記プラズマキュア処理中の前記フォトレジストマスクパターンの縦エッチングレートを抑制しながら、前記フォトレジストマスクパターンの表面と側面の凹凸を減少させた後、前記フォトレジストマスクパターンの下に設けた前記積層化された薄膜層をプラズマエッチング処理する
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において
前記フォトレジストマスクパターンのプラズマキュア処理における被処理材の処理温度は、20℃以上でかつ200℃以下である
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記フォトレジストマスクパターンの前記プラズマキュア処理における被処理材の処理温度と前記プラズマエッチング処理における被処理材の処理温度を異ならせた
ことを特徴とするプラズマ処理方法。 - 請求項1ないし請求項4のいずれか1項記載のプラズマ処理方法において、
前記プラズマエッチング装置は、ECR(Electron Cyclotron Resonance)エッチング装置である
ことを特徴とするプラズマ処理方法。
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JP5108489B2 (ja) | 2012-12-26 |
KR100918864B1 (ko) | 2009-09-28 |
TWI357622B (ja) | 2012-02-01 |
US20080182419A1 (en) | 2008-07-31 |
TW200845185A (en) | 2008-11-16 |
KR20080067584A (ko) | 2008-07-21 |
US8497213B2 (en) | 2013-07-30 |
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