JP2007533156A5 - - Google Patents

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Publication number
JP2007533156A5
JP2007533156A5 JP2007508363A JP2007508363A JP2007533156A5 JP 2007533156 A5 JP2007533156 A5 JP 2007533156A5 JP 2007508363 A JP2007508363 A JP 2007508363A JP 2007508363 A JP2007508363 A JP 2007508363A JP 2007533156 A5 JP2007533156 A5 JP 2007533156A5
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JP
Japan
Prior art keywords
region
metal layer
depositing
forming
gate dielectric
Prior art date
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Granted
Application number
JP2007508363A
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English (en)
Japanese (ja)
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JP2007533156A (ja
JP4757867B2 (ja
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Publication date
Priority claimed from US10/827,202 external-priority patent/US7030001B2/en
Application filed filed Critical
Publication of JP2007533156A publication Critical patent/JP2007533156A/ja
Publication of JP2007533156A5 publication Critical patent/JP2007533156A5/ja
Application granted granted Critical
Publication of JP4757867B2 publication Critical patent/JP4757867B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007508363A 2004-04-19 2005-03-22 金属からなるゲート電極を形成するための方法 Expired - Fee Related JP4757867B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/827,202 US7030001B2 (en) 2004-04-19 2004-04-19 Method for forming a gate electrode having a metal
US10/827,202 2004-04-19
PCT/US2005/009620 WO2005106938A1 (en) 2004-04-19 2005-03-22 Method for forming a gate electrode having a metal

Publications (3)

Publication Number Publication Date
JP2007533156A JP2007533156A (ja) 2007-11-15
JP2007533156A5 true JP2007533156A5 (enExample) 2008-05-08
JP4757867B2 JP4757867B2 (ja) 2011-08-24

Family

ID=35096814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007508363A Expired - Fee Related JP4757867B2 (ja) 2004-04-19 2005-03-22 金属からなるゲート電極を形成するための方法

Country Status (6)

Country Link
US (1) US7030001B2 (enExample)
EP (1) EP1776715B1 (enExample)
JP (1) JP4757867B2 (enExample)
KR (1) KR20070014152A (enExample)
CN (1) CN100437939C (enExample)
WO (1) WO2005106938A1 (enExample)

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US7998878B2 (en) * 2009-11-20 2011-08-16 Eastman Kodak Company Method for selective deposition and devices
US20110120544A1 (en) * 2009-11-20 2011-05-26 Levy David H Deposition inhibitor composition and method of use
US8318249B2 (en) * 2009-11-20 2012-11-27 Eastman Kodak Company Method for selective deposition and devices
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US9177870B2 (en) * 2011-12-16 2015-11-03 Taiwan Semiconductor Manufacturing Company Ltd. Enhanced gate replacement process for high-K metal gate technology
US8786018B2 (en) * 2012-09-11 2014-07-22 International Business Machines Corporation Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition
US10103057B2 (en) 2014-11-11 2018-10-16 The Board Of Trustees Of The University Of Illinois Use of an inhibitor molecule in chemical vapor deposition to afford deposition of copper on a metal substrate with no deposition on adjacent SIO2 substrate
KR101747264B1 (ko) 2015-11-30 2017-06-15 엘지디스플레이 주식회사 표시 장치와 그의 제조 방법
US11584986B1 (en) 2017-11-01 2023-02-21 The Board Of Trustees Of The University Of Illinois Area selective CVD of metallic films using precursor gases and inhibitors
JP7101551B2 (ja) 2018-07-02 2022-07-15 東京エレクトロン株式会社 選択的に対象膜を形成する方法およびシステム
JP7109397B2 (ja) 2019-03-13 2022-07-29 東京エレクトロン株式会社 成膜方法
JP2021044534A (ja) 2019-09-05 2021-03-18 東京エレクトロン株式会社 成膜方法
JP7353200B2 (ja) 2020-02-06 2023-09-29 東京エレクトロン株式会社 成膜方法
JP2022091523A (ja) 2020-12-09 2022-06-21 東京エレクトロン株式会社 成膜方法
JP2022137698A (ja) 2021-03-09 2022-09-22 東京エレクトロン株式会社 成膜方法および成膜システム
WO2022203222A1 (ko) * 2021-03-26 2022-09-29 주식회사 랩토 핵생성 억제 형성용 물질 및 이를 포함하는 유기전계발광소자

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