JP2007535171A5 - - Google Patents

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Publication number
JP2007535171A5
JP2007535171A5 JP2007510795A JP2007510795A JP2007535171A5 JP 2007535171 A5 JP2007535171 A5 JP 2007535171A5 JP 2007510795 A JP2007510795 A JP 2007510795A JP 2007510795 A JP2007510795 A JP 2007510795A JP 2007535171 A5 JP2007535171 A5 JP 2007535171A5
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JP
Japan
Prior art keywords
silicon
region
metal
metal alloy
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2007510795A
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English (en)
Japanese (ja)
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JP2007535171A (ja
JP4728323B2 (ja
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Publication date
Priority claimed from US10/833,073 external-priority patent/US7078278B2/en
Application filed filed Critical
Publication of JP2007535171A publication Critical patent/JP2007535171A/ja
Publication of JP2007535171A5 publication Critical patent/JP2007535171A5/ja
Application granted granted Critical
Publication of JP4728323B2 publication Critical patent/JP4728323B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2007510795A 2004-04-28 2005-04-19 調整可能なゲート電極の仕事関数を備えたデュアルメタルのｃｍｏｓトランジスタおよびその製造方法 Expired - Lifetime JP4728323B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/833,073 2004-04-28
US10/833,073 US7078278B2 (en) 2004-04-28 2004-04-28 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same
PCT/US2005/013240 WO2005109493A1 (en) 2004-04-28 2005-04-19 Dual-metal cmos transistors with tunable gate electrode work function and method of making the same

Publications (3)

Publication Number Publication Date
JP2007535171A JP2007535171A (ja) 2007-11-29
JP2007535171A5 true JP2007535171A5 (enExample) 2008-06-19
JP4728323B2 JP4728323B2 (ja) 2011-07-20

Family

ID=34966174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007510795A Expired - Lifetime JP4728323B2 (ja) 2004-04-28 2005-04-19 調整可能なゲート電極の仕事関数を備えたデュアルメタルのｃｍｏｓトランジスタおよびその製造方法

Country Status (8)

Country Link
US (1) US7078278B2 (enExample)
EP (1) EP1741132B1 (enExample)
JP (1) JP4728323B2 (enExample)
KR (1) KR101125269B1 (enExample)
CN (1) CN100472756C (enExample)
DE (1) DE602005016790D1 (enExample)
TW (1) TWI378492B (enExample)
WO (1) WO2005109493A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645687B2 (en) * 2005-01-20 2010-01-12 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate variable work function gates for FUSI devices
JP2006253316A (ja) 2005-03-09 2006-09-21 Sony Corp 固体撮像装置
JP5015446B2 (ja) * 2005-05-16 2012-08-29 アイメック 二重の完全ケイ化ゲートを形成する方法と前記方法によって得られたデバイス
JP2007142127A (ja) * 2005-11-18 2007-06-07 Sony Corp 半導体装置およびその製造方法
JP2007157744A (ja) * 2005-11-30 2007-06-21 Toshiba Corp 半導体装置および半導体装置の製造方法
US7768072B2 (en) * 2007-03-27 2010-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided metal gate for multi-threshold voltage configuration
US7678694B2 (en) * 2007-04-18 2010-03-16 Taiwan Semicondutor Manufacturing Company, Ltd. Method for fabricating semiconductor device with silicided gate
US8183137B2 (en) * 2007-05-23 2012-05-22 Texas Instruments Incorporated Use of dopants to provide low defect gate full silicidation
US7642153B2 (en) * 2007-10-23 2010-01-05 Texas Instruments Incorporated Methods for forming gate electrodes for integrated circuits
US8124515B2 (en) 2009-05-20 2012-02-28 Globalfoundries Inc. Gate etch optimization through silicon dopant profile change
US8895426B2 (en) * 2009-06-12 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
WO2012086102A1 (ja) * 2010-12-24 2012-06-28 パナソニック株式会社 半導体装置及びその製造方法
US8440520B2 (en) * 2011-08-23 2013-05-14 Tokyo Electron Limited Diffused cap layers for modifying high-k gate dielectrics and interface layers
US8722472B2 (en) * 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8633118B2 (en) 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
US8865538B2 (en) 2012-03-30 2014-10-21 Tokyo Electron Limited Method of integrating buried threshold voltage adjustment layers for CMOS processing
CN103515319B (zh) * 2012-06-20 2015-08-19 中芯国际集成电路制造(上海)有限公司 形成cmos全硅化物金属栅的方法
US8865581B2 (en) 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
KR102311552B1 (ko) 2014-12-04 2021-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102214096B1 (ko) 2015-08-06 2021-02-09 삼성전자주식회사 반도체 장치 제조 방법
CN105097473A (zh) * 2015-09-28 2015-11-25 上海集成电路研发中心有限公司 一种双金属栅极的形成方法
US10103065B1 (en) 2017-04-25 2018-10-16 International Business Machines Corporation Gate metal patterning for tight pitch applications
CN110391233B (zh) * 2018-04-17 2022-10-14 联华电子股份有限公司 半导体元件及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04505832A (ja) 1990-10-05 1992-10-08 ゼネラル・エレクトリック・カンパニイ 改良されたソース／ドレイン接点を持つ薄膜トランジスタ構造
JPH1117181A (ja) * 1997-06-26 1999-01-22 Sony Corp 半導体装置の製造方法
JPH11284179A (ja) * 1998-03-30 1999-10-15 Sony Corp 半導体装置およびその製造方法
US6392302B1 (en) * 1998-11-20 2002-05-21 Micron Technology, Inc. Polycide structure and method for forming polycide structure
JP4237332B2 (ja) * 1999-04-30 2009-03-11 株式会社東芝 半導体装置の製造方法
JP2001284466A (ja) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4811895B2 (ja) * 2001-05-02 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US6475908B1 (en) * 2001-10-18 2002-11-05 Chartered Semiconductor Manufacturing Ltd. Dual metal gate process: metals and their silicides
US6703271B2 (en) * 2001-11-30 2004-03-09 Taiwan Semiconductor Manufacturing Company Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
US6770521B2 (en) * 2001-11-30 2004-08-03 Texas Instruments Incorporated Method of making multiple work function gates by implanting metals with metallic alloying additives
US6689676B1 (en) * 2002-07-26 2004-02-10 Motorola, Inc. Method for forming a semiconductor device structure in a semiconductor layer
JP2005019885A (ja) * 2003-06-27 2005-01-20 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
JP2005085949A (ja) * 2003-09-08 2005-03-31 Semiconductor Leading Edge Technologies Inc 半導体装置およびその製造方法
JP4457688B2 (ja) * 2004-02-12 2010-04-28 ソニー株式会社 半導体装置

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