Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
  • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
  • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide

Definitions

• the present invention relates to the field of semiconductor fabrication, and more particularly, to a fabrication process incorporating different gate metals for NMOS and PMOS devices.
• NMOS N-type metal oxide semiconductors
• PMOS P-type metal oxide semiconductor
• the NMOS and PMOS threshold voltages are conventionally adjusted by a combination of channel implants and selective doping of a polysilicon gate. It is generally effective in adjusting the threshold voltages for PMOS devices but less effective for NMOS devices.
• dual metal gate CMOS complementary MOS
• Traditional metal gate transistors are normally fabricated by dry etching of metal or metal capped with polysilicon, to form the gate.
• the work function for one of the conductivity type devices will be undesirably changed.
• providing full silicidation of the polysilicon gate electrodes of NMOS devices and PMOS devices will operate to suppress the drive current lost to polysilicon depletion effects.
• the gate ⁇ electrode for the NMOS devices will have a desirable work function
• the gate electrodes for the PMOS devices will have an undesirable work function. This concern limits the usefulness of fully suiciding the gate electrodes of both NMOS and PMOS devices in a semiconductor arrangement.
• there are other concerns with fully suicided gates include the non-uniformity of the silicidation, and the potential for making the gate oxide dielectric layer unreliable.
• a dual-metal CMOS arrangement in which the work function of the gate electrodes are tunable, without using a fully suicided gate electrode and their attendant problems.
• This and other needs are meet by embodiments of the present invention which provide a dual-metal CMOS arrangement comprising a substrate and a plurality of NMOS devices and a plurality of PMOS devices.
• the plurality of NMOS devices have gate electrodes, with each NMOS gate electrode including a first silicide region on the substrate and a first metal region on the first silicide region.
• the first silicide region of the NMOS gate electrode consists of a first silicide having a work function within +/- 0.2V of the conduction band of silicon.
• the plurality of PMOS devices have gate electrodes, with each PMOS gate electrode having a second silicide region on the substrate and a second metal region on the second silicide region.
• the second silicide region of the PMOS gate electrode consists of a second silicide having a work function within +/- 0.2V of the valence band of silicon.
• the silicon regions are converted to a first silicide region in the NMOS device regions and to a second silicide region in the PMOS device regions.
• the first silicide region consists of a first silicide having a work function within +/- 0.2V of the conduction band of silicon and the second silicide region consists of a second silicide having a work function that is within +/- 0.2V of the valence band of silicon.
• Fig. 1 is a schematic cross-sectional view of a semiconductor wafer during one phase of manufacture of dual-metal CMOS transistors in accordance with the present invention.
• Fig. 2 depicts the structure of Fig. 1 following the formation of an etch stop layer on a first silicon layer in accordance with certain embodiments of the present invention.
• Fig. 3 depicts the structure of Fig. 2 following the deposition of a second silicon layer in accordance with embodiments of the present invention.
• Fig. 4 shows the structure of Fig. 3 following the formation of a hard mask, lithography and anisotropic etching to form silicon stacks in accordance with embodiments of the present invention.
• Fig. 5 depicts the structure of Fig.
• FIG. 6 shows the structure of Fig. 5 following the deposition of a dielectric layer and the planarization of the dielectric layer in removal of the hard mask in accordance with embodiments of the present invention.
• Fig. 7 depicts the structure of Fig. 6 following a lithography step to mask the PMOS devices in accordance with embodiments of the present invention.
• Fig. 8 shows the structure of Fig. 7 following an etching of the upper portion of the silicon stack of the NMOS devices in accordance with embodiments of the present invention.
• Fig. 9 depicts the structure or fig.
• Fig. 10 shows the structure of Fig. 9 after a planarization process in accordance with embodiments of the present invention.
• Fig. 11 depicts the structure of Fig. 10 following an annealing step to form a first silicide region in the NMOS devices in accordance with embodiments of the present invention.
• Fig. 12 shows the structure of Fig. 11 following a lithography step to mask the NMOS devices in accordance with embodiments of the present invention.
• Fig. 13 depicts the structure of Fig. 12 after an etching step is performed to remove the upper portion of the silicon stacks in the PMOS devices, in accordance with embodiments of the present invention.
• Fig. 14 depicts the structure of Fig. 13 after removal of the etch stop layer in the PMOS devices and deposition of a second metal in accordance with embodiments of the present invention.
• Fig. 15 depicts the structure of Fig. 14 after a planarization process in accordance with embodiments of the present invention.
• Fig. 16 depicts the structure of Fig. 15 following an annealing step to form the second silicide regions in accordance with embodiments of the present invention.
• Fig. 17 depicts an alternate embodiment of the present invention during one phase of manufacture.
• Fig. 18 depicts the alternate embodiment of Fig. 17 following formation of the first and second silicide regions in accordance with the alternate embodiments of the present invention.
• the present invention addresses and solves problems related to the formation of dual-metal CMOS transistors, and in particular, to those problems associated with fully suicided gate electrodes, including those related to non-uniformity of silicidation and gate oxide reliability.
• the dual-metal CMOS arrangement is provided with a plurality of NMOS devices and PMOS devices that have gate electrodes.
• Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region.
• the first silicide region of the NMOS gate electrode consists of a first silicide having a work function within +/- 0.2 V of the conduction band of silicon.
• Each PMOS gate electrode includes a second silicide region on the substrate and a second metal region on the second silicide region.
• the second silicide regions of the PMOS gate electrodes consist of a second silicide having a work function within +/- 0.2 V of the valence band of silicon.
• each gate electrode is only partially suicided, and the silicide regions are respectively provided with silicide that is tunable to be compatible with the NMOS and PMOS type devices.
• the tuning of the work function is achieved employing two different kinds of metals, such as the silicide regions are formed with two different metal suicides having different work functions.
• Fig. 1 depicts a cross-sectional view of a portion of a semiconductor wafer during one stage of a semiconductor manufacturing process according to embodiments of the present invention.
• a partially completed semiconductor device is illustrated in Fig. 1.
• the device includes a substrate 10 formed of silicon, tor example.
• the substrate 10 is doped with the N- or P-type dopants with a dose of about lxlO 16 to about lxlO 21 ion/cm 2 , for example.
• a shallow trench isolation (STI) structure 16 provides separation between the P-doped region 12 and the N-doped region 14 at the device level. Conventional STI formation methodology may be employed to create the shallow trench isolation region 16.
• a gate dielectric layer 18 is formed on the substrate 10.
• the gate dielectric layer 18 may consist of a gate oxide, for example.
• the gate dielectric layer 18 is ultra-thin, and may be between about 5 to about 30A, for example.
• a first silicon layer 20 is formed on the gate dielectric layer 18.
• the first silicon layer 20 may be deposited in a conventional manner.
• the first silicon layer is relatively thin, between 10 to about 500A, for example.
• the thickness of the first silicon layer is between 50 to about 200A.
• the thickness of the first silicon layer is less than about 50A.
• a relatively thin gate silicide thickness solves problems related to those created by fully suicided gate electrodes, including non- uniformity of silicidation and gate oxide reliability.
• Fig. 2 depicts the structure of Fig. 1 following the formation of an etch stop layer 22 on the first silicon layer 20.
• the etch stop layer 22 may be an oxide layer, for example. It is desirable to form the etch stop layer 22 to be very thin, such as about 10A, for example. Any suitable method for forming such a thin layer of oxide or other etch stop material may be employed. For example, an oxidation process at 600 to
• a second layer of silicon 24 is formed by conventional methodologies on the etch stop layer 22.
• the second silicon layer 24 may be between about 700 to about 2000A, for example, and in certain embodiments, is about 1000A thick.
• Fig. 4 depicts the structure of Fig. 3 after a hard mask layer has been deposited on the second silicon layer 24, followed by etching steps to form silicon stacks 26.
• Each of the silicon stacks 26 has a hard mask 30 formed on the upper portion 28 of the silicon stack 26. The etching creates silicon regions 32 in each of the silicon stacks 26.
• the hard mask 30 may be any suitable material, such as silicon nitride, silicon oxide, etc.
• a conventional anisotropic etching technique such as reactive ion etching, is employed to etch down to the gate dielectric layer 18.
• a source/drain extension implantation process is performed to create source/drain extensions 34.
• Conventional masking and doping techniques are performed to appropriately dope the NMOS devices and PMOS devices separately with a suitable dose of dopants.
• side wall spacers 36 are created on the side walls of the silicon stack 26 by conventional techniques, such as deposition of a spacer material and etching.
• a dielectric layer 40 has been deposited and planarized.
• the dielectric layer 40 may be of any conventional suitable dielectric material, such as a low k dielectric, an oxide, etc.
• the dielectric layer 40 may tie deposited oy any suitaoie meino ⁇ oiogy, such as chemical vapor deposition (CVD), etc.
• the planarization in certain-embodiments, is chemical-mechanical polishing, for example.
• a lithography and masking step is then performed, as depicted in Fig.
• a polysilicon etch process is performed that is very selective to oxide.
• An anisotropic etch such as a reactive ion etch, can be employed. Suitable etchants include chlorine and HBr0 2 , or SF 6 , for example.
• the upper portion 28 of the silicon stack 26 is removed by this etch process. The etch stops on the etch stop layer 22 reliably. This preserves the silicon region 32.
• first metal 48 is deposited to a thickness that assures complete filling of space left by the etching of the upper portion 28 of the silicide stack 26.
• the etch stop layer 22 Prior to the depositing of the first metal 48, however, the etch stop layer 22 is removed.
• the etch stop layer 22 is an oxide, for example, a buffered oxide etch is performed to remove the etch stop layer 22.
• This etch is a short time wet etch, for example, to remove the very thin etch stop layer 22 without damaging the surrounding side wall spacer 36.
• the first metal 48 is deposited to a thickness of at least 1000A to assure complete filling of the space previously occupied by the upper portion 28 of the silicon stack 26.
• the first metal 48 is a metal or metal alloy that when reacted with silicon, forms a silicide with a work function close to the conduction band of silicon. This is defined as being within
• one suitable metal is tantalum.
• Fig. 10 depicts the structure of Fig. 9 following the removal of the excess first metal 48, performed by a metal CMP process.
• the first metal 48 is removed until the dielectric layer 40 is reached.
• an annealing process such as rapid thermal annealing, is employed to form the first silicide region 50 in each of the NMOS devices 44.
• a suitable temperature range is employed, depending upon the type of metal or metal alloy used as the first metal 48.
• An analogous process is performed in Figs. 12-16 to create the second silicide regions in the PMOS devices.
• Fig. 12 depicts a lithography step in which the NMOS devices 44 are masked and the PMOS devices 46 are exposed.
• An etching process removes the upper portion 28 of the silicon stack 26 in each of the PMOS devices 46, as depicted in Fig'. 13.
• a second metal 52 is deposited on the dielectric layer 40 and within the space previously occupied by the upper portion 28 of the silicon stack 26.
• the second metal 52 consists of a metal or metal alloy that forms a silicide with a work function that is close to the valence band of silicon.
• the work function of the silicide is within +/- 0.2V of the valence band of silicon.
• Exemplary materials may include ruthenium, rhenium, or cobalt, for example.
• Other types of materials may be employed as a second metal 52 without departing from the scope of the present invention. However, such materials should form suicides with a work function that is close to the valence band of silicon in order to achieve the desired dual work functions of the CMOS arrangement.
• an appropriate annealing process is performed to form the second silicide regions 54 in the PMOS devices 46.
• a suitable temperature range for the annealing process is selected depending upon the metal forming the second metal 52. As seen in fig. 10, tne iNiviu-.
• the CMOS arrangement also has PMOS devices with second silicide regions that consist of a second silicide having a work function within +/- 0.2V of the valence band of silicon.
• the work functions of gate electrodes of the NMOS and PMOS devices 44, 46 are thus tunable by employing different kinds of metals or metal alloys to form the metal suicides.
• Figs. 17 and 18 depict certain steps in alternate embodiments of the present invention.
• the etch stop layer 22 is not employed.
• the silicon stack 26 is recessed by a controlled wet or dry etching to substantially reduce the polysilicon thickness of the silicon stack 26 prior to silicidation.
• the PMOS device 46 is masked and the silicon stack 26 of the NMOS device is etched. A similar process occurs to etch the silicon stack 26 in the PMOS devices 46.
• the thicknesses of the remaining silicon of the silicon stacks 26 are carefully controlled to be a desired thickness.
• the thickness of a thin polysilicon affects the phases of the silicide regions that are formed, which exhibit different conductivities. In this manner, the work function of the devices can be adjusted.
• the same metal may be employed, or different metals may be employed, to form the first and second silicide regions 50, 54, respectively. This is because the thickness of the silicon regions will control the phases of the suicides that are ultimately formed.
• certain type devices may be provided with a gate electrode having a higher resistivity phase silicide, such as CoSi, and other type devices provided with a gate electrode having a lower resistivity phase silicide, such as CoSi 2 .
• annealing parameters such as time and temperature, to form the first and second silicide regions 50, 54 to have the desired silicide phases and therefore work functions, as a function of the thicknesses of the silicon regions and the metals employed in the first and second metals.

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• 2004
  • 2004-04-28 US US10/833,073 patent/US7078278B2/en not_active Expired - Lifetime
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