JP2005085949A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2005085949A JP2005085949A JP2003315743A JP2003315743A JP2005085949A JP 2005085949 A JP2005085949 A JP 2005085949A JP 2003315743 A JP2003315743 A JP 2003315743A JP 2003315743 A JP2003315743 A JP 2003315743A JP 2005085949 A JP2005085949 A JP 2005085949A
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- H01L29/41725—Source or drain electrodes for field effect devices
Abstract
【解決手段】 NMOS領域とPMOS領域とを有する半導体装置において、NMOS領域のゲート電極11は、真性シリコンおよび真性シリコンと同等の仕事関数を有する物質のいずれか一方と、真性シリコンより小さい仕事関数を有する物質とからなり、PMOS領域のゲート電極10は、真性シリコンおよび真性シリコンと同等の仕事関数を有する物質のいずれか一方と、真性シリコンより大きい仕事関数を有する物質とからなる。また、NMOS領域のソース・ドレイン領域17は、真性シリコンより小さい仕事関数を有する物質のシリサイド層を有し、PMOS領域のソース・ドレイン領域16は、真性シリコンより大きい仕事関数を有する物質のシリサイド層を有する。
【選択図】 図1
Description
2 素子分離領域
3 Nウェル
4 Pウェル
5 ゲート絶縁膜
6 多結晶シリコン膜
7,12,20,23 SiO2膜
8 レジストパターン
9 SiO2膜パターン
10,11 ゲート電極
13,14 LDD領域
15 サイドウォール
16,17 ソース・ドレイン領域
18 Ti膜
19 TiSix膜
21 Ni膜
22 NiSix膜
Claims (6)
- NMOS領域とPMOS領域とを有する半導体装置において、
前記NMOS領域のゲート電極は、真性シリコンおよび真性シリコンと同等の仕事関数を有する物質のいずれか一方と、真性シリコンより小さい仕事関数を有する物質とからなり、
前記PMOS領域のゲート電極は、真性シリコンおよび真性シリコンと同等の仕事関数を有する物質のいずれか一方と、真性シリコンより大きい仕事関数を有する物質とからなることを特徴とする半導体装置。 - 前記NMOS領域のソース・ドレイン領域は、真性シリコンより小さい仕事関数を有する物質のシリサイド層を有し、
前記PMOS領域のソース・ドレイン領域は、真性シリコンより大きい仕事関数を有する物質のシリサイド層を有する請求項1に記載の半導体装置。 - 前記真性シリコンより小さい仕事関数を有する物質は、チタン、ハフニウム、ジルコニウム、アルミニウム、ニオブ、タンタル、バナジウムおよび窒化タンタルよりなる群から選ばれるいずれか1の物質である請求項1または2に記載の半導体装置。
- 前記真性シリコンより大きい仕事関数を有する物質は、ニッケル、白金、イリジウム、レニウムおよび二酸化ルテニウムよりなる群から選ばれるいずれか1の物質である請求項1〜3に記載の半導体装置。
- シリコン基板に素子分離領域を形成して、NMOS領域とPMOS領域とに区画する工程と、
前記シリコン基板の上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上に、真性シリコンおよび真性シリコンと同等の仕事関数を有する物質のいずれか一方からなる第1の物質膜を形成する工程と、
前記第1の物質膜をゲート電極パターンにエッチングする工程と、
少なくとも前記NMOS領域にある前記第1の物質膜の上に、真性シリコンより小さい仕事関数を有する物質からなる第2の物質膜を形成する工程と、
加熱処理によって前記第2の物質膜を前記第1の物質膜と選択的に反応させて、前記第1の物質膜と前記第2の物質膜との反応膜からなるNMOSのゲート電極を形成する工程と、
未反応の前記第2の物質膜を除去する工程と、
少なくとも前記PMOS領域にある前記第1の物質膜の上に、真性シリコンより大きい仕事関数を有する物質からなる第3の物質膜を形成する工程と、
加熱処理によって前記第3の物質膜を前記第1の物質膜と選択的に反応させて、前記第1の物質膜と前記第3の物質膜との反応膜からなるPMOSのゲート電極を形成する工程と、
未反応の前記第3の物質膜を除去する工程とを有することを特徴とする半導体装置の製造方法。 - 前記第2の物質膜を形成する工程は、NMOSのソース・ドレイン領域の上にも前記第2の物質膜を形成する工程であり、
前記NMOSのゲート電極を形成する工程は、加熱処理によって前記第2の物質膜を前記NMOSのソース・ドレイン領域を構成するシリコンとも反応させて、前記NMOSのソース・ドレイン領域にシリサイド層を形成する工程でもあり、
前記第3の物質膜を形成する工程は、PMOSのソース・ドレイン領域の上にも前記第3の物質膜を形成する工程であり、
前記PMOSのゲート電極を形成する工程は、加熱処理によって前記第3の物質膜を前記PMOSのソース・ドレイン領域を構成するシリコンとも反応させて、前記PMOSのソース・ドレイン領域にシリサイド層を形成する工程でもある請求項5に記載の半導体装置の製造方法。
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JP2003315743A JP2005085949A (ja) | 2003-09-08 | 2003-09-08 | 半導体装置およびその製造方法 |
US10/910,576 US20050051845A1 (en) | 2003-09-08 | 2004-08-04 | Semiconductor device and manufacturing method therefor |
KR1020040071048A KR20050025569A (ko) | 2003-09-08 | 2004-09-07 | 반도체 장치 및 그 제조 방법 |
US11/329,236 US20060118875A1 (en) | 2003-09-08 | 2006-01-11 | Method of manufacturing semiconductor device |
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Cited By (5)
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WO2007026677A1 (ja) * | 2005-09-01 | 2007-03-08 | Nec Corporation | 半導体装置の製造方法 |
JP2007535171A (ja) * | 2004-04-28 | 2007-11-29 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 調整可能なゲート電極の仕事関数を備えたデュアルメタルのcmosトランジスタおよびその製造方法 |
WO2008013125A1 (fr) * | 2006-07-25 | 2008-01-31 | Nec Corporation | Dispositif semi-conducteur et procédé de fabrication associé |
JP2009506549A (ja) * | 2005-08-22 | 2009-02-12 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 応力が加えられたゲート金属シリサイド層を含む高性能mosfet及びその製造方法 |
JP2014203912A (ja) * | 2013-04-03 | 2014-10-27 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
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JP4116990B2 (ja) * | 2004-09-28 | 2008-07-09 | 富士通株式会社 | 電界効果型トランジスタおよびその製造方法 |
KR100724563B1 (ko) * | 2005-04-29 | 2007-06-04 | 삼성전자주식회사 | 다중 일함수 금속 질화물 게이트 전극을 갖는 모스트랜지스터들, 이를 채택하는 씨모스 집적회로 소자들 및그 제조방법들 |
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US6130123A (en) * | 1998-06-30 | 2000-10-10 | Intel Corporation | Method for making a complementary metal gate electrode technology |
US6204103B1 (en) * | 1998-09-18 | 2001-03-20 | Intel Corporation | Process to make complementary silicide metal gates for CMOS technology |
JP3264264B2 (ja) * | 1999-03-01 | 2002-03-11 | 日本電気株式会社 | 相補型集積回路とその製造方法 |
TW497120B (en) * | 2000-03-06 | 2002-08-01 | Toshiba Corp | Transistor, semiconductor device and manufacturing method of semiconductor device |
JP2001284466A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2001298193A (ja) * | 2000-04-13 | 2001-10-26 | Seiko Epson Corp | 半導体装置およびその製造方法 |
US6475908B1 (en) * | 2001-10-18 | 2002-11-05 | Chartered Semiconductor Manufacturing Ltd. | Dual metal gate process: metals and their silicides |
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2003
- 2003-09-08 JP JP2003315743A patent/JP2005085949A/ja active Pending
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2004
- 2004-08-04 US US10/910,576 patent/US20050051845A1/en not_active Abandoned
- 2004-09-07 KR KR1020040071048A patent/KR20050025569A/ko not_active Application Discontinuation
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JP2007535171A (ja) * | 2004-04-28 | 2007-11-29 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 調整可能なゲート電極の仕事関数を備えたデュアルメタルのcmosトランジスタおよびその製造方法 |
JP4728323B2 (ja) * | 2004-04-28 | 2011-07-20 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 調整可能なゲート電極の仕事関数を備えたデュアルメタルのcmosトランジスタおよびその製造方法 |
JP2009506549A (ja) * | 2005-08-22 | 2009-02-12 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 応力が加えられたゲート金属シリサイド層を含む高性能mosfet及びその製造方法 |
US8405131B2 (en) | 2005-08-22 | 2013-03-26 | International Business Machines Corporation | High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same |
WO2007026677A1 (ja) * | 2005-09-01 | 2007-03-08 | Nec Corporation | 半導体装置の製造方法 |
US7723176B2 (en) | 2005-09-01 | 2010-05-25 | Nec Corporation | Method for manufacturing semiconductor device |
WO2008013125A1 (fr) * | 2006-07-25 | 2008-01-31 | Nec Corporation | Dispositif semi-conducteur et procédé de fabrication associé |
US7859059B2 (en) | 2006-07-25 | 2010-12-28 | Nec Corporation | Semiconductor device and method for manufacturing same |
JP5126060B2 (ja) * | 2006-07-25 | 2013-01-23 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2014203912A (ja) * | 2013-04-03 | 2014-10-27 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
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US20060118875A1 (en) | 2006-06-08 |
KR20050025569A (ko) | 2005-03-14 |
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