DE602005016790D1 - Herstellungsverfahren für doppel-metall-cmos-transistoren mit abstimmbarer gate-elektroden-arbeitsfunktion - Google Patents

Herstellungsverfahren für doppel-metall-cmos-transistoren mit abstimmbarer gate-elektroden-arbeitsfunktion

Info

Publication number
DE602005016790D1
DE602005016790D1 DE602005016790T DE602005016790T DE602005016790D1 DE 602005016790 D1 DE602005016790 D1 DE 602005016790D1 DE 602005016790 T DE602005016790 T DE 602005016790T DE 602005016790 T DE602005016790 T DE 602005016790T DE 602005016790 D1 DE602005016790 D1 DE 602005016790D1
Authority
DE
Germany
Prior art keywords
metal
gate electrode
cmos transistors
working function
electrode working
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602005016790T
Other languages
German (de)
English (en)
Inventor
James Pan
Ming-Ren Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE602005016790D1 publication Critical patent/DE602005016790D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE602005016790T 2004-04-28 2005-04-19 Herstellungsverfahren für doppel-metall-cmos-transistoren mit abstimmbarer gate-elektroden-arbeitsfunktion Expired - Lifetime DE602005016790D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/833,073 US7078278B2 (en) 2004-04-28 2004-04-28 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same
PCT/US2005/013240 WO2005109493A1 (en) 2004-04-28 2005-04-19 Dual-metal cmos transistors with tunable gate electrode work function and method of making the same

Publications (1)

Publication Number Publication Date
DE602005016790D1 true DE602005016790D1 (de) 2009-11-05

Family

ID=34966174

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005016790T Expired - Lifetime DE602005016790D1 (de) 2004-04-28 2005-04-19 Herstellungsverfahren für doppel-metall-cmos-transistoren mit abstimmbarer gate-elektroden-arbeitsfunktion

Country Status (8)

Country Link
US (1) US7078278B2 (enExample)
EP (1) EP1741132B1 (enExample)
JP (1) JP4728323B2 (enExample)
KR (1) KR101125269B1 (enExample)
CN (1) CN100472756C (enExample)
DE (1) DE602005016790D1 (enExample)
TW (1) TWI378492B (enExample)
WO (1) WO2005109493A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645687B2 (en) * 2005-01-20 2010-01-12 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate variable work function gates for FUSI devices
JP2006253316A (ja) 2005-03-09 2006-09-21 Sony Corp 固体撮像装置
JP5015446B2 (ja) * 2005-05-16 2012-08-29 アイメック 二重の完全ケイ化ゲートを形成する方法と前記方法によって得られたデバイス
JP2007142127A (ja) * 2005-11-18 2007-06-07 Sony Corp 半導体装置およびその製造方法
JP2007157744A (ja) * 2005-11-30 2007-06-21 Toshiba Corp 半導体装置および半導体装置の製造方法
US7768072B2 (en) * 2007-03-27 2010-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided metal gate for multi-threshold voltage configuration
US7678694B2 (en) * 2007-04-18 2010-03-16 Taiwan Semicondutor Manufacturing Company, Ltd. Method for fabricating semiconductor device with silicided gate
US8183137B2 (en) * 2007-05-23 2012-05-22 Texas Instruments Incorporated Use of dopants to provide low defect gate full silicidation
US7642153B2 (en) * 2007-10-23 2010-01-05 Texas Instruments Incorporated Methods for forming gate electrodes for integrated circuits
US8124515B2 (en) 2009-05-20 2012-02-28 Globalfoundries Inc. Gate etch optimization through silicon dopant profile change
US8895426B2 (en) * 2009-06-12 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
WO2012086102A1 (ja) * 2010-12-24 2012-06-28 パナソニック株式会社 半導体装置及びその製造方法
US8440520B2 (en) * 2011-08-23 2013-05-14 Tokyo Electron Limited Diffused cap layers for modifying high-k gate dielectrics and interface layers
US8722472B2 (en) * 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8633118B2 (en) 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
US8865538B2 (en) 2012-03-30 2014-10-21 Tokyo Electron Limited Method of integrating buried threshold voltage adjustment layers for CMOS processing
CN103515319B (zh) * 2012-06-20 2015-08-19 中芯国际集成电路制造(上海)有限公司 形成cmos全硅化物金属栅的方法
US8865581B2 (en) 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
KR102311552B1 (ko) 2014-12-04 2021-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102214096B1 (ko) 2015-08-06 2021-02-09 삼성전자주식회사 반도체 장치 제조 방법
CN105097473A (zh) * 2015-09-28 2015-11-25 上海集成电路研发中心有限公司 一种双金属栅极的形成方法
US10103065B1 (en) 2017-04-25 2018-10-16 International Business Machines Corporation Gate metal patterning for tight pitch applications
CN110391233B (zh) * 2018-04-17 2022-10-14 联华电子股份有限公司 半导体元件及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04505832A (ja) 1990-10-05 1992-10-08 ゼネラル・エレクトリック・カンパニイ 改良されたソース／ドレイン接点を持つ薄膜トランジスタ構造
JPH1117181A (ja) * 1997-06-26 1999-01-22 Sony Corp 半導体装置の製造方法
JPH11284179A (ja) * 1998-03-30 1999-10-15 Sony Corp 半導体装置およびその製造方法
US6392302B1 (en) * 1998-11-20 2002-05-21 Micron Technology, Inc. Polycide structure and method for forming polycide structure
JP4237332B2 (ja) * 1999-04-30 2009-03-11 株式会社東芝 半導体装置の製造方法
JP2001284466A (ja) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4811895B2 (ja) * 2001-05-02 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US6475908B1 (en) * 2001-10-18 2002-11-05 Chartered Semiconductor Manufacturing Ltd. Dual metal gate process: metals and their silicides
US6703271B2 (en) * 2001-11-30 2004-03-09 Taiwan Semiconductor Manufacturing Company Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
US6770521B2 (en) * 2001-11-30 2004-08-03 Texas Instruments Incorporated Method of making multiple work function gates by implanting metals with metallic alloying additives
US6689676B1 (en) * 2002-07-26 2004-02-10 Motorola, Inc. Method for forming a semiconductor device structure in a semiconductor layer
JP2005019885A (ja) * 2003-06-27 2005-01-20 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
JP2005085949A (ja) * 2003-09-08 2005-03-31 Semiconductor Leading Edge Technologies Inc 半導体装置およびその製造方法
JP4457688B2 (ja) * 2004-02-12 2010-04-28 ソニー株式会社 半導体装置

Also Published As

Publication number Publication date
KR20070004095A (ko) 2007-01-05
EP1741132B1 (en) 2009-09-23
US7078278B2 (en) 2006-07-18
KR101125269B1 (ko) 2012-03-22
TW200540961A (en) 2005-12-16
JP2007535171A (ja) 2007-11-29
CN100472756C (zh) 2009-03-25
WO2005109493A1 (en) 2005-11-17
EP1741132A1 (en) 2007-01-10
CN1947243A (zh) 2007-04-11
US20050245016A1 (en) 2005-11-03
TWI378492B (en) 2012-12-01
JP4728323B2 (ja) 2011-07-20

Similar Documents

Publication Publication Date Title
DE602005016790D1 (de) Herstellungsverfahren für doppel-metall-cmos-transistoren mit abstimmbarer gate-elektroden-arbeitsfunktion
DE602005019797D1 (de) Thermoplastische elastomerzusammensetzung und herstellungsverfahren dafür
DE602004010297D1 (de) Organisches elektro-optisches bauelement und sein herstellungsverfahren
EP1923708A4 (en) CONDUCTIVE CONTACT AND METHOD FOR PRODUCING CONDUCTIVE CONTACT
DE602005025091D1 (de) Piezooszillator und herstellungsverfahren dafür
EP1938892A4 (en) SOLID OXYGEN SCAVENGER COMPOSITION AND MANUFACTURING METHOD THEREFOR
DE602006021036D1 (de) Substituierte benzimidazole und herstellungsverfahren dafür
DE602005020518D1 (de) Abdichtungsmittel für ölquelle mit alkalisch quellbarem latex
EP1848390A4 (en) WOUND ASSOCIATION AND MANUFACTURING METHOD THEREFOR
DE602006009540D1 (de) L und herstellungsverfahren dafür
EP1977446A4 (en) SEMICONDUCTOR TRANSISTORS WITH EXTENDED TOP PORTIONS OF TRIGGERS
DE602006003767D1 (de) Zylinderlaufbüchse und herstellungsverfahren dafür
EP2091072A4 (en) METHOD FOR FORMING A CONDUCTIVE FILM, THIN-LAYER TRANSISTOR, THIN-LAYERED TRANSISTOR TABLE, AND METHOD FOR PRODUCING A THIN-FILTER TRANSISTOR
EP2037496A4 (en) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR
DE602006020117D1 (de) Nadellager und herstellungsverfahren dafür
DE602006017185D1 (de) Innenautozierteil und herstellungsverfahren dafür
DE602006015175D1 (de) Leuchtstoff und herstellungsverfahren dafür
DE602006014713D1 (de) Ersatz-metall-gate-transistoren mit reduzierter gateoxid-leckage
DE602005009200D1 (de) Quecksilberfreisetzende zusammensetzungen und herstellungsverfahren dafür
EP1915790A4 (en) PROCESS FOR PRODUCING ORGANIC FETS
EP1966827A4 (en) High mobility power metal-oxide semiconductor field-effect transistors
DE602005017019D1 (de) Socken und herstellungsverfahren dafür
EP1939319A4 (en) SEMICONDUCTOR THIN FILM AND METHOD FOR PRODUCING THE SAME
DK1971634T3 (da) Totrinshærdningspolymidoligomerer
EP1949442A4 (en) MANUFACTURING TRANSISTORS

Legal Events

Date Code Title Description
8364 No opposition during term of opposition