KR101125269B1 - 조정가능한 게이트 전극 일함수를 갖는 이중 금속 cmos 트랜지스터 및 그 제조 방법 - Google Patents

조정가능한 게이트 전극 일함수를 갖는 이중 금속 cmos 트랜지스터 및 그 제조 방법 Download PDF

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KR101125269B1
KR101125269B1 KR1020067023670A KR20067023670A KR101125269B1 KR 101125269 B1 KR101125269 B1 KR 101125269B1 KR 1020067023670 A KR1020067023670 A KR 1020067023670A KR 20067023670 A KR20067023670 A KR 20067023670A KR 101125269 B1 KR101125269 B1 KR 101125269B1
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silicon
regions
metal
silicide
layer
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KR20070004095A (ko
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제임스 판
밍-렌 린
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020067023670A 2004-04-28 2005-04-19 조정가능한 게이트 전극 일함수를 갖는 이중 금속 cmos 트랜지스터 및 그 제조 방법 Expired - Lifetime KR101125269B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/833,073 2004-04-28
US10/833,073 US7078278B2 (en) 2004-04-28 2004-04-28 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same
PCT/US2005/013240 WO2005109493A1 (en) 2004-04-28 2005-04-19 Dual-metal cmos transistors with tunable gate electrode work function and method of making the same

Publications (2)

Publication Number Publication Date
KR20070004095A KR20070004095A (ko) 2007-01-05
KR101125269B1 true KR101125269B1 (ko) 2012-03-22

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Country Link
US (1) US7078278B2 (enExample)
EP (1) EP1741132B1 (enExample)
JP (1) JP4728323B2 (enExample)
KR (1) KR101125269B1 (enExample)
CN (1) CN100472756C (enExample)
DE (1) DE602005016790D1 (enExample)
TW (1) TWI378492B (enExample)
WO (1) WO2005109493A1 (enExample)

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US7645687B2 (en) * 2005-01-20 2010-01-12 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate variable work function gates for FUSI devices
JP2006253316A (ja) 2005-03-09 2006-09-21 Sony Corp 固体撮像装置
JP5015446B2 (ja) * 2005-05-16 2012-08-29 アイメック 二重の完全ケイ化ゲートを形成する方法と前記方法によって得られたデバイス
JP2007142127A (ja) * 2005-11-18 2007-06-07 Sony Corp 半導体装置およびその製造方法
JP2007157744A (ja) * 2005-11-30 2007-06-21 Toshiba Corp 半導体装置および半導体装置の製造方法
US7768072B2 (en) * 2007-03-27 2010-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided metal gate for multi-threshold voltage configuration
US7678694B2 (en) * 2007-04-18 2010-03-16 Taiwan Semicondutor Manufacturing Company, Ltd. Method for fabricating semiconductor device with silicided gate
US8183137B2 (en) * 2007-05-23 2012-05-22 Texas Instruments Incorporated Use of dopants to provide low defect gate full silicidation
US7642153B2 (en) * 2007-10-23 2010-01-05 Texas Instruments Incorporated Methods for forming gate electrodes for integrated circuits
US8124515B2 (en) 2009-05-20 2012-02-28 Globalfoundries Inc. Gate etch optimization through silicon dopant profile change
US8895426B2 (en) * 2009-06-12 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
WO2012086102A1 (ja) * 2010-12-24 2012-06-28 パナソニック株式会社 半導体装置及びその製造方法
US8440520B2 (en) * 2011-08-23 2013-05-14 Tokyo Electron Limited Diffused cap layers for modifying high-k gate dielectrics and interface layers
US8722472B2 (en) * 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8633118B2 (en) 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
US8865538B2 (en) 2012-03-30 2014-10-21 Tokyo Electron Limited Method of integrating buried threshold voltage adjustment layers for CMOS processing
CN103515319B (zh) * 2012-06-20 2015-08-19 中芯国际集成电路制造(上海)有限公司 形成cmos全硅化物金属栅的方法
US8865581B2 (en) 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
KR102311552B1 (ko) 2014-12-04 2021-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102214096B1 (ko) 2015-08-06 2021-02-09 삼성전자주식회사 반도체 장치 제조 방법
CN105097473A (zh) * 2015-09-28 2015-11-25 上海集成电路研发中心有限公司 一种双金属栅极的形成方法
US10103065B1 (en) 2017-04-25 2018-10-16 International Business Machines Corporation Gate metal patterning for tight pitch applications
CN110391233B (zh) * 2018-04-17 2022-10-14 联华电子股份有限公司 半导体元件及其制作方法

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JPH1117181A (ja) * 1997-06-26 1999-01-22 Sony Corp 半導体装置の製造方法
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Publication number Publication date
KR20070004095A (ko) 2007-01-05
EP1741132B1 (en) 2009-09-23
US7078278B2 (en) 2006-07-18
TW200540961A (en) 2005-12-16
JP2007535171A (ja) 2007-11-29
DE602005016790D1 (de) 2009-11-05
CN100472756C (zh) 2009-03-25
WO2005109493A1 (en) 2005-11-17
EP1741132A1 (en) 2007-01-10
CN1947243A (zh) 2007-04-11
US20050245016A1 (en) 2005-11-03
TWI378492B (en) 2012-12-01
JP4728323B2 (ja) 2011-07-20

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