JP2008522444A5 - - Google Patents

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Publication number
JP2008522444A5
JP2008522444A5 JP2007544510A JP2007544510A JP2008522444A5 JP 2008522444 A5 JP2008522444 A5 JP 2008522444A5 JP 2007544510 A JP2007544510 A JP 2007544510A JP 2007544510 A JP2007544510 A JP 2007544510A JP 2008522444 A5 JP2008522444 A5 JP 2008522444A5
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JP
Japan
Prior art keywords
well region
semiconductor device
type
metal layer
forming
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Application number
JP2007544510A
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English (en)
Japanese (ja)
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JP2008522444A (ja
JP5102628B2 (ja
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Publication date
Priority claimed from US10/904,884 external-priority patent/US7064025B1/en
Application filed filed Critical
Publication of JP2008522444A publication Critical patent/JP2008522444A/ja
Publication of JP2008522444A5 publication Critical patent/JP2008522444A5/ja
Application granted granted Critical
Publication of JP5102628B2 publication Critical patent/JP5102628B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007544510A 2004-12-02 2005-12-01 Ｃｍｏｓ技術における自己整合デュアル・サリサイド形成のための方法 Expired - Fee Related JP5102628B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/904,884 2004-12-02
US10/904,884 US7064025B1 (en) 2004-12-02 2004-12-02 Method for forming self-aligned dual salicide in CMOS technologies
PCT/US2005/043474 WO2006060575A2 (en) 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in cmos technologies

Publications (3)

Publication Number Publication Date
JP2008522444A JP2008522444A (ja) 2008-06-26
JP2008522444A5 true JP2008522444A5 (enExample) 2008-10-09
JP5102628B2 JP5102628B2 (ja) 2012-12-19

Family

ID=36565727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007544510A Expired - Fee Related JP5102628B2 (ja) 2004-12-02 2005-12-01 Ｃｍｏｓ技術における自己整合デュアル・サリサイド形成のための方法

Country Status (7)

Country Link
US (3) US7064025B1 (enExample)
EP (1) EP1825508A4 (enExample)
JP (1) JP5102628B2 (enExample)
KR (1) KR101055708B1 (enExample)
CN (1) CN101069281B (enExample)
TW (1) TWI371084B (enExample)
WO (1) WO2006060575A2 (enExample)

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US20070123042A1 (en) * 2005-11-28 2007-05-31 International Business Machines Corporation Methods to form heterogeneous silicides/germanides in cmos technology
US7544575B2 (en) * 2006-01-19 2009-06-09 Freescale Semiconductor, Inc. Dual metal silicide scheme using a dual spacer process
US20070178683A1 (en) * 2006-02-02 2007-08-02 Texas Instruments, Incorporated Semiconductive device fabricated using a two step approach to silicide a gate and source/drains
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US7569446B2 (en) * 2007-06-12 2009-08-04 International Business Machines Corporation Semiconductor structure and method of manufacture
KR101406226B1 (ko) * 2008-05-07 2014-06-13 삼성전자주식회사 반도체 소자의 제조 방법
WO2009153880A1 (ja) * 2008-06-20 2009-12-23 日本ユニサンティスエレクトロニクス株式会社 半導体記憶装置
US20100019327A1 (en) * 2008-07-22 2010-01-28 Eun Jong Shin Semiconductor Device and Method of Fabricating the Same
US8021971B2 (en) * 2009-11-04 2011-09-20 International Business Machines Corporation Structure and method to form a thermally stable silicide in narrow dimension gate stacks
CN103456691B (zh) * 2012-05-29 2015-07-29 中芯国际集成电路制造(上海)有限公司 Cmos的制造方法
KR20140101218A (ko) 2013-02-08 2014-08-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR20140108960A (ko) 2013-03-04 2014-09-15 삼성전자주식회사 듀얼 금속 실리사이드층을 갖는 반도체 장치의 제조 방법
US8999799B2 (en) 2013-08-29 2015-04-07 International Business Machines Corporation Maskless dual silicide contact formation
FR3016235B1 (fr) * 2014-01-08 2016-01-22 Commissariat Energie Atomique Procede de fabrication d'un dispositif microelectronique
US10546856B2 (en) 2014-02-25 2020-01-28 Stmicroelectronics, Inc. CMOS structure having low resistance contacts and fabrication method
US9390981B1 (en) 2015-02-05 2016-07-12 Globalfoundries Inc. Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides
US9564372B2 (en) 2015-06-16 2017-02-07 International Business Machines Corporation Dual liner silicide
US9805973B2 (en) 2015-10-30 2017-10-31 International Business Machines Corporation Dual silicide liner flow for enabling low contact resistance
US11443949B2 (en) * 2019-03-20 2022-09-13 Tokyo Electron Limited Method of selectively forming metal silicides for semiconductor devices
TWI696270B (zh) * 2019-04-15 2020-06-11 力晶積成電子製造股份有限公司 記憶體結構及其製造方法
US12094785B2 (en) * 2021-12-15 2024-09-17 Applied Materials, Inc. Dual silicide process using ruthenium silicide
US20230326764A1 (en) * 2022-04-08 2023-10-12 Tokyo Electron Limited Silicidation Process for Semiconductor Devices

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US5635426A (en) * 1993-08-26 1997-06-03 Fujitsu Limited Method of making a semiconductor device having a silicide local interconnect
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
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US6534405B1 (en) 2001-10-01 2003-03-18 Taiwan Semiconductor Manufacturing Company Method of forming a MOSFET device featuring a dual salicide process
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US6589836B1 (en) 2002-10-03 2003-07-08 Taiwan Semiconductor Manufacturing Company One step dual salicide formation for ultra shallow junction applications
JP3921437B2 (ja) * 2002-10-17 2007-05-30 富士通株式会社 半導体装置の製造方法
JP4197607B2 (ja) * 2002-11-06 2008-12-17 株式会社東芝 絶縁ゲート型電界効果トランジスタを含む半導体装置の製造方法
US6846734B2 (en) * 2002-11-20 2005-01-25 International Business Machines Corporation Method and process to make multiple-threshold metal gates CMOS technology
JP4209206B2 (ja) * 2003-01-14 2009-01-14 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
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