JP5102628B2 - Cmos技術における自己整合デュアル・サリサイド形成のための方法 - Google Patents
Cmos技術における自己整合デュアル・サリサイド形成のための方法 Download PDFInfo
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- JP5102628B2 JP5102628B2 JP2007544510A JP2007544510A JP5102628B2 JP 5102628 B2 JP5102628 B2 JP 5102628B2 JP 2007544510 A JP2007544510 A JP 2007544510A JP 2007544510 A JP2007544510 A JP 2007544510A JP 5102628 B2 JP5102628 B2 JP 5102628B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
Description
Claims (5)
- CMOSデバイスを製作する方法であって、
PFETを収容するために半導体基板の中にNウェル領域を形成するステップと、
NFETを収容するために前記半導体基板の中にPウェル領域を形成するステップと、
前記PFETおよび前記NFETのいずれか一方をマスクで遮蔽するステップと、
前記マスクで遮蔽されていない前記PFETまたは前記NFETの上に第1の金属層を堆積させるステップと、
前記第1の金属層が堆積された前記PFETまたは前記NFETのゲート領域、ソース領域およびドレイン領域の上で第1のサリサイド形成を行うステップと、
前記マスクを除去するステップと、
前記PFETおよび前記NFETの上に前記第1の金属層とは異なる材料からなる第2の金属層を堆積させるステップと、
前記第1のサリサイドが形成されていない前記PFETまたは前記NFETのゲート領域、ソース領域およびドレイン領域の上で第2のサリサイド形成を行うステップと、を含む方法。 - 前記第1の金属層を堆積させるステップに続いて、前記第1の金属層の上にキャップ層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記第2の金属層を堆積させるステップに続いて、前記第2の金属層の上にキャップ層を形成するステップをさらに含む、請求項2に記載の方法。
- 前記キャップ層は、TiN、Ti、及びTaNのいずれかを含む、請求項2または3に記載の方法。
- 前記第1の金属層及び前記第2の金属層は、Ti、Co、Ni、Pt、Re、W、Pd、Ta、Nb、及びこれらの合金の中から選択される、請求項1〜4のいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/904,884 | 2004-12-02 | ||
US10/904,884 US7064025B1 (en) | 2004-12-02 | 2004-12-02 | Method for forming self-aligned dual salicide in CMOS technologies |
PCT/US2005/043474 WO2006060575A2 (en) | 2004-12-02 | 2005-12-01 | Method for forming self-aligned dual salicide in cmos technologies |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008522444A JP2008522444A (ja) | 2008-06-26 |
JP2008522444A5 JP2008522444A5 (ja) | 2008-10-09 |
JP5102628B2 true JP5102628B2 (ja) | 2012-12-19 |
Family
ID=36565727
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007544510A Expired - Fee Related JP5102628B2 (ja) | 2004-12-02 | 2005-12-01 | Cmos技術における自己整合デュアル・サリサイド形成のための方法 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7064025B1 (ja) |
EP (1) | EP1825508A4 (ja) |
JP (1) | JP5102628B2 (ja) |
KR (1) | KR101055708B1 (ja) |
CN (1) | CN101069281B (ja) |
TW (1) | TWI371084B (ja) |
WO (1) | WO2006060575A2 (ja) |
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JP2008112857A (ja) * | 2006-10-30 | 2008-05-15 | Nec Electronics Corp | 半導体集積回路装置 |
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WO2009153880A1 (ja) * | 2008-06-20 | 2009-12-23 | 日本ユニサンティスエレクトロニクス株式会社 | 半導体記憶装置 |
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2004
- 2004-12-02 US US10/904,884 patent/US7064025B1/en active Active
-
2005
- 2005-10-20 US US11/254,929 patent/US7112481B2/en not_active Expired - Fee Related
- 2005-10-20 US US11/254,934 patent/US7067368B1/en active Active
- 2005-11-28 TW TW094141765A patent/TWI371084B/zh not_active IP Right Cessation
- 2005-12-01 KR KR1020077012730A patent/KR101055708B1/ko not_active IP Right Cessation
- 2005-12-01 EP EP05852638A patent/EP1825508A4/en not_active Withdrawn
- 2005-12-01 CN CN2005800413925A patent/CN101069281B/zh not_active Expired - Fee Related
- 2005-12-01 JP JP2007544510A patent/JP5102628B2/ja not_active Expired - Fee Related
- 2005-12-01 WO PCT/US2005/043474 patent/WO2006060575A2/en active Application Filing
Also Published As
Publication number | Publication date |
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TW200625540A (en) | 2006-07-16 |
US20060121665A1 (en) | 2006-06-08 |
WO2006060575A3 (en) | 2007-04-26 |
TWI371084B (en) | 2012-08-21 |
CN101069281A (zh) | 2007-11-07 |
US7112481B2 (en) | 2006-09-26 |
US20060121662A1 (en) | 2006-06-08 |
US20060121664A1 (en) | 2006-06-08 |
EP1825508A4 (en) | 2009-06-24 |
CN101069281B (zh) | 2012-05-30 |
EP1825508A2 (en) | 2007-08-29 |
US7067368B1 (en) | 2006-06-27 |
JP2008522444A (ja) | 2008-06-26 |
KR20070085805A (ko) | 2007-08-27 |
KR101055708B1 (ko) | 2011-08-11 |
US7064025B1 (en) | 2006-06-20 |
WO2006060575A2 (en) | 2006-06-08 |
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