JP2010502025A5 - - Google Patents

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Publication number
JP2010502025A5
JP2010502025A5 JP2009525999A JP2009525999A JP2010502025A5 JP 2010502025 A5 JP2010502025 A5 JP 2010502025A5 JP 2009525999 A JP2009525999 A JP 2009525999A JP 2009525999 A JP2009525999 A JP 2009525999A JP 2010502025 A5 JP2010502025 A5 JP 2010502025A5
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JP
Japan
Prior art keywords
field effect
effect transistor
type field
stress liner
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2009525999A
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English (en)
Japanese (ja)
Other versions
JP4558841B2 (ja
JP2010502025A (ja
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Publication date
Priority claimed from US11/468,958 external-priority patent/US7675118B2/en
Application filed filed Critical
Publication of JP2010502025A publication Critical patent/JP2010502025A/ja
Publication of JP2010502025A5 publication Critical patent/JP2010502025A5/ja
Application granted granted Critical
Publication of JP4558841B2 publication Critical patent/JP4558841B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009525999A 2006-08-31 2007-07-06 簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体 Expired - Fee Related JP4558841B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/468,958 US7675118B2 (en) 2006-08-31 2006-08-31 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
PCT/EP2007/056881 WO2008025588A1 (en) 2006-08-31 2007-07-06 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration

Publications (3)

Publication Number Publication Date
JP2010502025A JP2010502025A (ja) 2010-01-21
JP2010502025A5 true JP2010502025A5 (enExample) 2010-05-06
JP4558841B2 JP4558841B2 (ja) 2010-10-06

Family

ID=38535491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009525999A Expired - Fee Related JP4558841B2 (ja) 2006-08-31 2007-07-06 簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体

Country Status (5)

Country Link
US (1) US7675118B2 (enExample)
JP (1) JP4558841B2 (enExample)
KR (1) KR101071787B1 (enExample)
CN (1) CN101512771A (enExample)
WO (1) WO2008025588A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101007242B1 (ko) 2007-02-22 2011-01-13 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
WO2008126264A1 (ja) * 2007-03-30 2008-10-23 Fujitsu Microelectronics Limited 半導体集積回路装置
CN102412203A (zh) * 2011-05-13 2012-04-11 上海华力微电子有限公司 一种提高半导体器件应力记忆技术效果的方法
US9023696B2 (en) 2011-05-26 2015-05-05 Globalfoundries Inc. Method of forming contacts for devices with multiple stress liners
CN103094108B (zh) * 2011-10-29 2015-12-02 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
US10056382B2 (en) 2016-10-19 2018-08-21 International Business Machines Corporation Modulating transistor performance
US11721722B2 (en) 2021-08-27 2023-08-08 Globalfoundries U.S. Inc. Bipolar junction transistors including a stress liner

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
FR2846789B1 (fr) * 2002-11-05 2005-06-24 St Microelectronics Sa Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur
JP4557508B2 (ja) * 2003-06-16 2010-10-06 パナソニック株式会社 半導体装置
US6905922B2 (en) * 2003-10-03 2005-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Dual fully-silicided gate MOSFETs
US7190033B2 (en) * 2004-04-15 2007-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of manufacture
US7314836B2 (en) * 2004-06-30 2008-01-01 Intel Corporation Enhanced nitride layers for metal oxide semiconductors
JP4444027B2 (ja) * 2004-07-08 2010-03-31 富士通マイクロエレクトロニクス株式会社 ｎチャネルＭＯＳトランジスタおよびＣＭＯＳ集積回路装置
US7824811B2 (en) 2004-07-13 2010-11-02 Honda Motor Co., Ltd. Fuel cell discharge-gas processing device
JP2006059980A (ja) * 2004-08-19 2006-03-02 Renesas Technology Corp 半導体装置及びその製造方法
DE102004052617B4 (de) * 2004-10-29 2010-08-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement mit Halbleitergebieten, die unterschiedlich verformte Kanalgebiete aufweisen
JP2008518476A (ja) * 2004-10-29 2008-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 異なるように歪ませた歪みチャネル領域を有する半導体領域を含む、半導体デバイスおよびその製造方法
US7645687B2 (en) * 2005-01-20 2010-01-12 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate variable work function gates for FUSI devices
US7649230B2 (en) * 2005-06-17 2010-01-19 The Regents Of The University Of California Complementary field-effect transistors having enhanced performance with a single capping layer
US20070108526A1 (en) * 2005-11-14 2007-05-17 Toshiba America Electronic Components, Inc. Strained silicon CMOS devices
JP2007141903A (ja) * 2005-11-15 2007-06-07 Renesas Technology Corp 半導体装置およびその製造方法
JP4765598B2 (ja) * 2005-12-08 2011-09-07 ソニー株式会社 半導体装置の製造方法
US7439120B2 (en) * 2006-08-11 2008-10-21 Advanced Micro Devices, Inc. Method for fabricating stress enhanced MOS circuits
JP5268084B2 (ja) * 2006-12-22 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8154107B2 (en) * 2007-02-07 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method of fabricating the device

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