JP4558841B2 - 簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体 - Google Patents
簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体 Download PDFInfo
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- JP4558841B2 JP4558841B2 JP2009525999A JP2009525999A JP4558841B2 JP 4558841 B2 JP4558841 B2 JP 4558841B2 JP 2009525999 A JP2009525999 A JP 2009525999A JP 2009525999 A JP2009525999 A JP 2009525999A JP 4558841 B2 JP4558841 B2 JP 4558841B2
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Description
半導体基板の表面上に配置された少なくとも1つのn型電界効果トランジスタ(nFET)であって、ゲート誘電体の上にある完全にシリサイド化されたゲート電極を含む材料スタックと、材料スタックの垂直側壁上に配置された少なくとも1つのスペーサとを含む、少なくとも1つのn型電界効果トランジスタ(nFET)と、
半導体基板上に配置され、かつ、少なくとも1つのnFETを部分的に包み込む第1の応力ライナであって、nFETの完全にシリサイド化されたゲート電極の上面と実質的に同一平面にある上面を有する、第1の応力ライナと、
第1の応力ライナの上面上及び少なくとも1つのnFETの上に配置された、第1の応力ライナのものと反対の応力型の第2の応力ライナと、
を含む。
半導体構造体の表面上に配置された少なくとも1つのn型電界効果トランジスタ及び少なくとも1つのp型電界効果トランジスタであって、ゲート誘電体の上にある完全にシリサイド化されたゲート電極によって形成された材料スタックと、材料スタックの垂直壁面上に配置された少なくとも1つのスペーサとを含む、少なくとも1つのn型電界効果トランジスタ及び少なくとも1つのp型電界効果トランジスタと、
少なくとも1つのn型電界効果トランジスタを含む半導体基板の部分の上に配置された引張応力ライナであって、少なくとも1つのn型電界効果トランジスタを部分的に包み込み、かつ、完全にシリサイド化されたゲート電極の上面と実質的に同一平面にある上面を有する、引張応力ライナと、
第1の応力ライナの上面上及び少なくとも1つのn型電界効果トランジスタの上に配置された圧縮応力ライナであって、少なくとも1つのp型電界効果トランジスタを完全に囲む、圧縮応力ライナと、
を含む。
半導体構造体の表面上に少なくとも1つのn型電界効果トランジスタ(nFET)を準備することであって、少なくとも1つのnFETは、ゲート誘電体の上にある完全にシリサイド化されたゲート電極を形成する材料スタックと、材料スタックの垂直側壁上に配置された少なくとも1つのスペーサとを含む、ことと、
半導体基板上に第1の応力ライナを形成することであって、第1の応力ライナは、少なくとも1つのnFETを部分的に包み込み、かつ、完全にシリサイド化されたゲート電極の上面と実質的に同一平面にある上面を有する、ことと、
第1の応力ライナの上面上及び少なくとも1つのnFETの上に、第1の応力ライナのものと反対の型の第2の応力ライナを形成することと、
を含む。
12:半導体基板
12A:下部半導体層
12B:埋め込み絶縁層
12C:上部半導体層
14:分離領域
16、16´:ゲート誘電体
18、18´:完全にシリサイド化されたゲート電極
20:スペーサ
22:nFET
25:pFET
100:nFET領域
102:pFET領域
Claims (16)
- 半導体基板に配置された少なくとも1つのn型電界効果トランジスタであって、ゲート誘電体の上にある完全にシリサイド化されたゲート電極と、前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサとを含む、少なくとも1つのn型電界効果トランジスタと、
前記半導体基板上に配置され、かつ、前記少なくとも1つのn型電界効果トランジスタの前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサを囲む引張応力ライナであって、前記少なくとも1つのn型電界効果トランジスタの前記完全にシリサイド化されたゲート電極の上面と同一平面にある上面を有する、引張応力ライナと、
前記引張応力ライナの前記上面上及び前記少なくとも1つのn型電界効果トランジスタの上に配置された圧縮応力ライナと、
を備える半導体構造体。 - 前記半導体基板は、バルク半導体材料又は半導体オン・インシュレータである、請求項1に記載の半導体構造体。
- 前記半導体基板は、異なる結晶配向の表面領域を有するハイブリッド基板であり、前記少なくとも1つのn型電界効果トランジスタは、前記ハイブリッド基板の(100)結晶面上に配置される、請求項1に記載の半導体構造体。
- 前記完全にシリサイド化されたゲート電極は金属シリサイドを含み、前記金属は、Ti、Ta、W、Co、Ni、Pt、Pd、又はそれらの合金を含む、請求項1に記載の半導体構造体。
- 前記完全にシリサイド化されたゲート電極は、10nmから50nmまでの垂直方向高さを有する、請求項1に記載の半導体構造体。
- 前記半導体基板に配置された少なくとも1つのp型電界効果トランジスタをさらに備え、前記少なくとも1つのp型電界効果トランジスタは、トレンチ分離領域によって前記少なくとも1つのn型電界効果トランジスタから部分的に分離され、前記圧縮応力ライナは、前記少なくとも1つのp型電界効果トランジスタのゲート電極を完全に囲む、請求項1に記載の半導体構造体。
- 半導体基板に配置された少なくとも1つのn型電界効果トランジスタであって、ゲート誘電体の上にある完全にシリサイド化されたゲート電極と、前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサとを含む、少なくとも1つのn型電界効果トランジスタと、
前記半導体基板上に配置され、かつ、前記少なくとも1つのn型電界効果トランジスタの前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサを囲む引張応力窒化物ライナであって、前記完全にシリサイド化されたゲート電極の上面と同一平面にある上面を有する、引張応力窒化物ライナと、
前記引張応力窒化物ライナの前記上面上及び前記少なくとも1つのn型電界効果トランジスタの上に配置された圧縮応力窒化物ライナと、
を備える半導体構造体。 - 前記引張応力窒化物ライナは内因性引張応力を有する、請求項7に記載の半導体構造体。
- 前記半導体基板は、バルク半導体材料又は半導体オン・インシュレータである、請求項7に記載の半導体構造体。
- 半導体基板に配置された少なくとも1つのn型電界効果トランジスタ及び少なくとも1つのp型電界効果トランジスタであって、ゲート誘電体の上にある完全にシリサイド化されたゲート電極と、前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサとを含む、少なくとも1つのn型電界効果トランジスタ及び少なくとも1つのp型電界効果トランジスタと、
前記半導体基板上に配置され、かつ、前記少なくとも1つのn型電界効果トランジスタの前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサを囲む引張応力ライナであって、前記少なくとも1つのn型電界効果トランジスタの前記完全にシリサイド化されたゲート電極の上面と同一平面にある上面を有する、引張応力ライナと、
前記引張応力ライナの前記上面上及び前記少なくとも1つのn型電界効果トランジスタの上に配置された圧縮応力ライナであって、前記少なくとも1つのp型電界効果トランジスタを完全に囲む、圧縮応力ライナと、
を備える半導体構造体。 - 前記引張応力ライナ及び前記圧縮応力ライナは、両方とも窒化物である、請求項10に記載の半導体構造体。
- 前記引張応力ライナは内因性引張応力を有する、請求項11に記載の半導体構造体。
- 半導体構造体を形成する方法であって、
半導体基板に少なくとも1つのn型電界効果トランジスタを準備することであって、前記少なくとも1つのn型電界効果トランジスタは、ゲート誘電体の上にある完全にシリサイド化されたゲート電極と、前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサとを含む、ことと、
前記半導体基板上に引張応力ライナを形成することであって、前記引張応力ライナは、前記少なくとも1つのn型電界効果トランジスタの前記ゲート電極の両側の垂直側壁上にそれぞれ配置されたスペーサを囲み、かつ、前記n型電界効果トランジスタの前記完全にシリサイド化されたゲート電極の上面と同一平面にある上面を有する、ことと、
前記引張応力ライナの前記上面上及び前記少なくとも1つのn型電界効果トランジスタの上に圧縮応力ライナを形成することと、
を含む方法。 - 前記少なくとも1つのn型電界効果トランジスタを準備することは、前記ゲート誘電体及びSi含有材料を含むスタックを形成することと、前記スタックをパターン形成することと、前記パターン形成されたスタックの両側の垂直側壁上にそれぞれ前記スペーサを形成することと、前記Si含有材料の部分を選択的に除去し、一部のSi含有材料が前記ゲート誘電体上に残るようにすることと、前記残りのSi含有材料上に金属層を形成することと、前記金属層と前記残りのSi含有材料との間に反応を引き起こす少なくとも1つのアニール・プロセスを行なうこととを含む、請求項13に記載の方法。
- 前記引張応力ライナを形成することは、少なくとも1つの引張応力誘起材料の化学気相堆積と、前記少なくとも1つの電界効果トランジスタの上に前記引張応力ライナの部分を露出させる平坦化材料を形成することと、前記引張応力ライナ材料の前記露出された部分を選択的に除去することと、前記平坦化材料を除去することとを含む、請求項13に記載の方法。
- 前記半導体基板上の少なくとも1つのp型電界効果トランジスタをさらに含み、前記少なくとも1つのp型電界効果トランジスタは、分離領域によって前記少なくとも1つのn型電界効果トランジスタから分離され、前記圧縮応力ライナは、前記少なくとも1つのp型電界効果トランジスタのゲート電極を完全に囲む、請求項13に記載の方法。
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CN101641778B (zh) * | 2007-03-30 | 2014-12-17 | 富士通半导体股份有限公司 | 半导体集成电路装置 |
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US9023696B2 (en) | 2011-05-26 | 2015-05-05 | Globalfoundries Inc. | Method of forming contacts for devices with multiple stress liners |
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US10056382B2 (en) | 2016-10-19 | 2018-08-21 | International Business Machines Corporation | Modulating transistor performance |
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US6905922B2 (en) * | 2003-10-03 | 2005-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual fully-silicided gate MOSFETs |
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US7824811B2 (en) | 2004-07-13 | 2010-11-02 | Honda Motor Co., Ltd. | Fuel cell discharge-gas processing device |
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US7645687B2 (en) * | 2005-01-20 | 2010-01-12 | Chartered Semiconductor Manufacturing, Ltd. | Method to fabricate variable work function gates for FUSI devices |
US7649230B2 (en) * | 2005-06-17 | 2010-01-19 | The Regents Of The University Of California | Complementary field-effect transistors having enhanced performance with a single capping layer |
US20070108526A1 (en) * | 2005-11-14 | 2007-05-17 | Toshiba America Electronic Components, Inc. | Strained silicon CMOS devices |
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JP4765598B2 (ja) * | 2005-12-08 | 2011-09-07 | ソニー株式会社 | 半導体装置の製造方法 |
US7439120B2 (en) * | 2006-08-11 | 2008-10-21 | Advanced Micro Devices, Inc. | Method for fabricating stress enhanced MOS circuits |
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US8154107B2 (en) * | 2007-02-07 | 2012-04-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method of fabricating the device |
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