JP5268084B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L21/3105—After-treatment
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Description
(A)半導体基板(10)に複数の構造体(15、18−21)を形成する工程と、
(B)前記半導体基板(10)の全面に、前記複数の構造体(15、18−21)を被覆する有機膜(16、24)を形成する工程と、
(C)前記複数の構造体(15、18−21)のうち加工対象である加工対象構造体の上方に開口を有するレジスト(17、25)を形成する工程と、
(D)前記開口の内側において前記半導体基板(10)が前記コーティング膜(16、24)で被覆された状態を維持しながら前記レジスト(17、25)をマスクとして前記コーティング膜(16、24)をエッチングし、前記加工対象構造体の一部を露出させる工程と、
(E)前記開口の内側において前記コーティング膜(16、24)を残存させながら、前記加工対象構造体の少なくとも一部である加工対象部分をエッチングする工程と、
(F)前記レジスト(17、25)と前記コーティング膜(16、24)とを除去する工程
とを具備する。コーティング膜(16、24)としては、有機膜が最も好適に使用される。
図3A〜図3Hは、本発明の第1の実施形態の半導体装置の製造方法を示す断面図である。第1の実施形態では、ゲート電極を複数形成し、更に、そのうちの一部を選択的に除去するプロセスが行われる。
図6A乃至図6Fは、第2の実施形態における半導体装置の製造方法を示す断面図である。第2の実施形態では、FUSIプロセスにおいて、一部のゲート電極のポリシリコンを選択的にシリサイド化するプロセスが行われる。
図7A乃至図7Mは、第3の実施形態における半導体装置の製造方法を示す断面図である。第3の実施形態では、シリコン基板10の全面が図7Aに示されているように窒化シリコンで形成されたストッパー窒化膜21によって被覆されている場合に、ポリシリコン電極18をNMOS領域とPMOS領域とで別々にシリサイド化するプロセスが行われる。ポリシリコン電極18は、シリサイド化された上でMOSトランジスタのゲート電極として使用される。当業者には容易に理解されるように、ポリシリコン電極18のシリサイド化がNMOS領域とPMOS領域とで別々に行われるのは、シリサイド化によって形成されたゲート電極の仕事関数を制御するためである。
有機反射防止膜16は、典型的には、スピン塗布を用いて形成される。スピン塗布に使用される溶液の濃度は、ストッパー窒化膜21が露出せず、且つ、シリコン基板10の全面が有機反射防止膜16によって被覆されるように選択される。
図8A乃至図8Lは、第4の実施形態における半導体装置の製造方法を示す断面図である。第4の実施形態の半導体装置の製造方法は、第3の実施形態の半導体装置の製造方法とほぼ同様である。相違点は、図8Aに示されているように、ゲート絶縁膜11の上に2層のポリシリコン電極18A、18Bが形成され、その間に保護窒化膜19が形成されることである。第4の実施形態では、ポリシリコン電極18A、18Bのうちポリシリコン電極18Aのみがシリサイド化される。即ち、ポリシリコン電極18Bは、ポリシリコン電極18Aのシリサイド化の前に除去される。このような工程が採用されるのは、シリサイド化によって形成されたシリサイドゲート電極に含まれるシリコンと金属元素(例えばニッケル)の組成比を制御するためである。シリコンと金属元素の組成比を制御することにより、シリサイドゲート電極の仕事関数を制御することができる。
11:ゲート絶縁膜
12:ポリシリコン膜
13:有機反射防止膜
14:レジスト
14A:第1ハードマスク層
14B:第2ハードマスク層
15:ゲート電極
16:有機反射防止膜
17:レジスト
18、18A、18B:ポリシリコン電極
19:保護窒化膜
20:サイドウォール
21:ストッパー窒化膜
22:シリサイドゲート電極
23:ストッパー窒化膜
24:有機反射防止膜
25:レジスト
26:ストッパー窒化膜
110:半導体基板
111:ゲート電極
112:ポリシリコン膜
113:WSi膜
114:保護膜
401:塗布膜
402:レジスト
Claims (8)
- (A)半導体基板に複数の構造体を形成する工程と、
(B)前記半導体基板の全面に、前記複数の構造体を被覆する有機膜であるコーティング膜を、スピン塗布を用いて形成する工程と、
(C)前記複数の構造体のうち加工対象である加工対象構造体の上方に開口を有するレジストを形成する工程と、
(D)前記開口の内側において前記半導体基板が前記コーティング膜で被覆された状態を維持しながら前記レジストをマスクとして前記コーティング膜をエッチングし、前記加工対象構造体の一部を露出させる工程と、
(E)前記開口の内側において前記コーティング膜を残存させながら、前記加工対象構造体の少なくとも一部である加工対象部分をエッチングする工程と、
(F)前記レジストと前記コーティング膜とを除去する工程
とを具備する
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記(D)工程のエッチングは、前記コーティング膜のエッチングレートが前記加工対象部分のエッチングレートよりも高い条件で行われ、
前記(E)工程のエッチングは、前記加工対象部分のエッチングレートが前記コーティング膜のエッチングレートよりも高い条件で行われる
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記有機膜は、有機反射防止膜である
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記(F)工程において、前記レジストと前記コーティング膜が、アッシング、薬液処理、オゾン処理、又はそれらの組み合わせによって除去される
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記複数の構造体は、ポリシリコンで形成された複数のゲート電極を含み、
前記加工対象構造体は、前記複数のゲート構造体のうちの一部のゲート電極である
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記加工対象構造体は、
ポリシリコン電極と、
前記ポリシリコン電極を被覆する窒化シリコンで形成された保護窒化膜
とを含み、
前記(E)ステップでは、前記保護窒化膜が、前記加工対象部分としてエッチングされる
半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法であって、
前記加工対象構造体は、
ポリシリコン電極と、
前記ポリシリコン電極を被覆する窒化シリコンで形成された保護窒化膜と、
前記ポリシリコン電極と前記保護窒化膜の側面を被覆するサイドウォールと、
前記保護窒化膜と前記サイドウォールとを被覆する、窒化シリコンで形成されたストッパー窒化膜
とを含み、
前記(E)ステップでは、前記ストッパー窒化膜の一部と前記保護窒化膜とが、前記加工対象部分としてエッチングされる
半導体装置の製造方法。 - 請求項6又は請求項7に記載の半導体装置の製造方法であって、
更に、
(G)前記ポリシリコン電極に対してシリサイド化を行う工程
を具備する
半導体装置の製造方法。
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JP2006346642A JP5268084B2 (ja) | 2006-12-22 | 2006-12-22 | 半導体装置の製造方法 |
CN2007101600991A CN101207008B (zh) | 2006-12-22 | 2007-12-24 | 制造半导体器件的方法 |
US11/964,074 US20080214008A1 (en) | 2006-12-22 | 2007-12-26 | Method of manufacturing semiconductor device |
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US7675118B2 (en) * | 2006-08-31 | 2010-03-09 | International Business Machines Corporation | Semiconductor structure with enhanced performance using a simplified dual stress liner configuration |
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CN107706106A (zh) * | 2017-09-21 | 2018-02-16 | 信利(惠州)智能显示有限公司 | Amoled显示面板的制备方法 |
CN114695092A (zh) * | 2020-12-25 | 2022-07-01 | 联华电子股份有限公司 | 形成半导体元件的方法 |
TWI756003B (zh) * | 2021-01-04 | 2022-02-21 | 力晶積成電子製造股份有限公司 | 平坦化方法 |
CN113611603A (zh) * | 2021-07-29 | 2021-11-05 | 矽磐微电子(重庆)有限公司 | 半导体结构的制造方法 |
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US6004843A (en) * | 1998-05-07 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company | Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip |
JP2001015704A (ja) * | 1999-06-29 | 2001-01-19 | Hitachi Ltd | 半導体集積回路 |
US6338993B1 (en) * | 1999-08-18 | 2002-01-15 | Worldwide Semiconductor Manufacturing Corp. | Method to fabricate embedded DRAM with salicide logic cell structure |
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JP3449998B2 (ja) * | 2000-10-05 | 2003-09-22 | 沖電気工業株式会社 | 半導体装置におけるコンタクトホールの形成方法 |
KR100448592B1 (ko) * | 2001-12-29 | 2004-09-13 | 주식회사 하이닉스반도체 | 반도체 소자의 구리배선 형성 방법 |
JP4278338B2 (ja) * | 2002-04-01 | 2009-06-10 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US6979626B2 (en) * | 2002-08-13 | 2005-12-27 | Newport Fab, Llc | Method for fabricating a self-aligned bipolar transistor having increased manufacturability and related structure |
US7122903B2 (en) * | 2003-10-21 | 2006-10-17 | Sharp Kabushiki Kaisha | Contact plug processing and a contact plug |
KR100583957B1 (ko) * | 2003-12-03 | 2006-05-26 | 삼성전자주식회사 | 희생금속산화막을 채택하여 이중다마신 금속배선을형성하는 방법 |
US7098114B1 (en) * | 2004-06-22 | 2006-08-29 | Integrated Device Technology, Inc. | Method for forming cmos device with self-aligned contacts and region formed using salicide process |
JP2006024835A (ja) * | 2004-07-09 | 2006-01-26 | Seiko Epson Corp | 配線パターンの修復方法及び、電子デバイスの製造方法 |
JP4440080B2 (ja) * | 2004-11-12 | 2010-03-24 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7341933B2 (en) * | 2004-12-08 | 2008-03-11 | Texas Instruments Incorporated | Method for manufacturing a silicided gate electrode using a buffer layer |
US7291553B2 (en) * | 2005-03-08 | 2007-11-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming dual damascene with improved etch profiles |
JP2006294877A (ja) * | 2005-04-11 | 2006-10-26 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
JP2007165558A (ja) * | 2005-12-13 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2008130798A (ja) * | 2006-11-21 | 2008-06-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
2006
- 2006-12-22 JP JP2006346642A patent/JP5268084B2/ja not_active Expired - Fee Related
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2007
- 2007-12-24 CN CN2007101600991A patent/CN101207008B/zh not_active Expired - Fee Related
- 2007-12-26 US US11/964,074 patent/US20080214008A1/en not_active Abandoned
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JP2008159809A (ja) | 2008-07-10 |
CN101207008B (zh) | 2010-12-08 |
CN101207008A (zh) | 2008-06-25 |
US20080214008A1 (en) | 2008-09-04 |
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