JP4558841B2 - 簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体 - Google Patents

簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体 Download PDF

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JP4558841B2
JP4558841B2 JP2009525999A JP2009525999A JP4558841B2 JP 4558841 B2 JP4558841 B2 JP 4558841B2 JP 2009525999 A JP2009525999 A JP 2009525999A JP 2009525999 A JP2009525999 A JP 2009525999A JP 4558841 B2 JP4558841 B2 JP 4558841B2
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field effect
effect transistor
type field
stress liner
tensile stress
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JP2010502025A5 (enExample
JP2010502025A (ja
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チダンバラオ、デュレセティ
リュー、ヤオチェン
ヘンソン、ウィリアム
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2009525999A 2006-08-31 2007-07-06 簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体 Expired - Fee Related JP4558841B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/468,958 US7675118B2 (en) 2006-08-31 2006-08-31 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
PCT/EP2007/056881 WO2008025588A1 (en) 2006-08-31 2007-07-06 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration

Publications (3)

Publication Number Publication Date
JP2010502025A JP2010502025A (ja) 2010-01-21
JP2010502025A5 JP2010502025A5 (enExample) 2010-05-06
JP4558841B2 true JP4558841B2 (ja) 2010-10-06

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JP2009525999A Expired - Fee Related JP4558841B2 (ja) 2006-08-31 2007-07-06 簡単化されたデュアル応力ライナ構成を用いる向上した性能をもつ半導体構造体

Country Status (5)

Country Link
US (1) US7675118B2 (enExample)
JP (1) JP4558841B2 (enExample)
KR (1) KR101071787B1 (enExample)
CN (1) CN101512771A (enExample)
WO (1) WO2008025588A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5359863B2 (ja) 2007-02-22 2013-12-04 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5299268B2 (ja) * 2007-03-30 2013-09-25 富士通セミコンダクター株式会社 半導体集積回路装置およびその製造方法
CN102412203A (zh) * 2011-05-13 2012-04-11 上海华力微电子有限公司 一种提高半导体器件应力记忆技术效果的方法
US9023696B2 (en) 2011-05-26 2015-05-05 Globalfoundries Inc. Method of forming contacts for devices with multiple stress liners
CN103094108B (zh) * 2011-10-29 2015-12-02 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
US10056382B2 (en) 2016-10-19 2018-08-21 International Business Machines Corporation Modulating transistor performance
US11721722B2 (en) 2021-08-27 2023-08-08 Globalfoundries U.S. Inc. Bipolar junction transistors including a stress liner

Family Cites Families (19)

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Publication number Priority date Publication date Assignee Title
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
FR2846789B1 (fr) * 2002-11-05 2005-06-24 St Microelectronics Sa Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur
JP4557508B2 (ja) * 2003-06-16 2010-10-06 パナソニック株式会社 半導体装置
US6905922B2 (en) * 2003-10-03 2005-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Dual fully-silicided gate MOSFETs
US7190033B2 (en) * 2004-04-15 2007-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of manufacture
US7314836B2 (en) * 2004-06-30 2008-01-01 Intel Corporation Enhanced nitride layers for metal oxide semiconductors
JP4444027B2 (ja) * 2004-07-08 2010-03-31 富士通マイクロエレクトロニクス株式会社 ｎチャネルＭＯＳトランジスタおよびＣＭＯＳ集積回路装置
US7824811B2 (en) 2004-07-13 2010-11-02 Honda Motor Co., Ltd. Fuel cell discharge-gas processing device
JP2006059980A (ja) * 2004-08-19 2006-03-02 Renesas Technology Corp 半導体装置及びその製造方法
KR20070069160A (ko) * 2004-10-29 2007-07-02 어드밴스드 마이크로 디바이시즈, 인코포레이티드 서로 다른 스트레인드 채널 영역들을 갖는 반도체 영역들을포함하는 반도체 디바이스 및 이를 제조하는 방법
DE102004052617B4 (de) * 2004-10-29 2010-08-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement mit Halbleitergebieten, die unterschiedlich verformte Kanalgebiete aufweisen
US7645687B2 (en) * 2005-01-20 2010-01-12 Chartered Semiconductor Manufacturing, Ltd. Method to fabricate variable work function gates for FUSI devices
US7649230B2 (en) * 2005-06-17 2010-01-19 The Regents Of The University Of California Complementary field-effect transistors having enhanced performance with a single capping layer
US20070108526A1 (en) * 2005-11-14 2007-05-17 Toshiba America Electronic Components, Inc. Strained silicon CMOS devices
JP2007141903A (ja) * 2005-11-15 2007-06-07 Renesas Technology Corp 半導体装置およびその製造方法
JP4765598B2 (ja) * 2005-12-08 2011-09-07 ソニー株式会社 半導体装置の製造方法
US7439120B2 (en) * 2006-08-11 2008-10-21 Advanced Micro Devices, Inc. Method for fabricating stress enhanced MOS circuits
JP5268084B2 (ja) * 2006-12-22 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8154107B2 (en) * 2007-02-07 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method of fabricating the device

Also Published As

Publication number Publication date
KR20090046822A (ko) 2009-05-11
US7675118B2 (en) 2010-03-09
WO2008025588A1 (en) 2008-03-06
KR101071787B1 (ko) 2011-10-11
US20080054357A1 (en) 2008-03-06
CN101512771A (zh) 2009-08-19
JP2010502025A (ja) 2010-01-21

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