CN101069281B - 在cmos技术中形成自对准双重硅化物的方法 - Google Patents

在cmos技术中形成自对准双重硅化物的方法 Download PDF

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Publication number
CN101069281B
CN101069281B CN2005800413925A CN200580041392A CN101069281B CN 101069281 B CN101069281 B CN 101069281B CN 2005800413925 A CN2005800413925 A CN 2005800413925A CN 200580041392 A CN200580041392 A CN 200580041392A CN 101069281 B CN101069281 B CN 101069281B
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forming
well region
type semiconductor
metal layer
region
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Expired - Fee Related
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CN2005800413925A
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Chinese (zh)
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CN101069281A (zh
Inventor
小希里尔·卡布莱尔
切斯特·T.·齐奥波科夫斯基
约汉·J.·爱丽斯-莫纳甘
方隼飞
克里斯蒂安·拉沃伊
骆志炯
詹姆斯·S.·纳考斯
安·L.·斯廷根
克莱门特·H.·万
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
CN2005800413925A 2004-12-02 2005-12-01 在cmos技术中形成自对准双重硅化物的方法 Expired - Fee Related CN101069281B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/904,884 US7064025B1 (en) 2004-12-02 2004-12-02 Method for forming self-aligned dual salicide in CMOS technologies
US10/904,884 2004-12-02
PCT/US2005/043474 WO2006060575A2 (en) 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in cmos technologies

Publications (2)

Publication Number Publication Date
CN101069281A CN101069281A (zh) 2007-11-07
CN101069281B true CN101069281B (zh) 2012-05-30

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Family Applications (1)

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CN2005800413925A Expired - Fee Related CN101069281B (zh) 2004-12-02 2005-12-01 在cmos技术中形成自对准双重硅化物的方法

Country Status (7)

Country Link
US (3) US7064025B1 (enExample)
EP (1) EP1825508A4 (enExample)
JP (1) JP5102628B2 (enExample)
KR (1) KR101055708B1 (enExample)
CN (1) CN101069281B (enExample)
TW (1) TWI371084B (enExample)
WO (1) WO2006060575A2 (enExample)

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US20070123042A1 (en) * 2005-11-28 2007-05-31 International Business Machines Corporation Methods to form heterogeneous silicides/germanides in cmos technology
US7544575B2 (en) * 2006-01-19 2009-06-09 Freescale Semiconductor, Inc. Dual metal silicide scheme using a dual spacer process
US20070178683A1 (en) * 2006-02-02 2007-08-02 Texas Instruments, Incorporated Semiconductive device fabricated using a two step approach to silicide a gate and source/drains
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JP2008112857A (ja) * 2006-10-30 2008-05-15 Nec Electronics Corp 半導体集積回路装置
US7750426B2 (en) 2007-05-30 2010-07-06 Intersil Americas, Inc. Junction barrier Schottky diode with dual silicides
US7569446B2 (en) * 2007-06-12 2009-08-04 International Business Machines Corporation Semiconductor structure and method of manufacture
KR101406226B1 (ko) * 2008-05-07 2014-06-13 삼성전자주식회사 반도체 소자의 제조 방법
WO2009153880A1 (ja) * 2008-06-20 2009-12-23 日本ユニサンティスエレクトロニクス株式会社 半導体記憶装置
US20100019327A1 (en) * 2008-07-22 2010-01-28 Eun Jong Shin Semiconductor Device and Method of Fabricating the Same
US8021971B2 (en) * 2009-11-04 2011-09-20 International Business Machines Corporation Structure and method to form a thermally stable silicide in narrow dimension gate stacks
CN103456691B (zh) * 2012-05-29 2015-07-29 中芯国际集成电路制造(上海)有限公司 Cmos的制造方法
KR20140101218A (ko) 2013-02-08 2014-08-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR20140108960A (ko) 2013-03-04 2014-09-15 삼성전자주식회사 듀얼 금속 실리사이드층을 갖는 반도체 장치의 제조 방법
US8999799B2 (en) 2013-08-29 2015-04-07 International Business Machines Corporation Maskless dual silicide contact formation
FR3016235B1 (fr) * 2014-01-08 2016-01-22 Commissariat Energie Atomique Procede de fabrication d'un dispositif microelectronique
US10546856B2 (en) 2014-02-25 2020-01-28 Stmicroelectronics, Inc. CMOS structure having low resistance contacts and fabrication method
US9390981B1 (en) 2015-02-05 2016-07-12 Globalfoundries Inc. Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides
US9564372B2 (en) 2015-06-16 2017-02-07 International Business Machines Corporation Dual liner silicide
US9805973B2 (en) 2015-10-30 2017-10-31 International Business Machines Corporation Dual silicide liner flow for enabling low contact resistance
WO2020191068A1 (en) * 2019-03-20 2020-09-24 Tokyo Electron Limited Method of selectively forming metal silicides for semiconductor devices
TWI696270B (zh) * 2019-04-15 2020-06-11 力晶積成電子製造股份有限公司 記憶體結構及其製造方法
US12094785B2 (en) * 2021-12-15 2024-09-17 Applied Materials, Inc. Dual silicide process using ruthenium silicide
US20230326764A1 (en) * 2022-04-08 2023-10-12 Tokyo Electron Limited Silicidation Process for Semiconductor Devices

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US6787464B1 (en) * 2002-07-02 2004-09-07 Advanced Micro Devices, Inc. Method of forming silicide layers over a plurality of semiconductor devices

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US5824578A (en) * 1996-12-12 1998-10-20 Mosel Vitelic Inc. Method of making a CMOS transistor using liquid phase deposition
US5989950A (en) * 1998-01-26 1999-11-23 Texas Instruments - Acer Incorporated Reduced mask CMOS salicided process
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Also Published As

Publication number Publication date
KR101055708B1 (ko) 2011-08-11
US20060121664A1 (en) 2006-06-08
JP5102628B2 (ja) 2012-12-19
TWI371084B (en) 2012-08-21
KR20070085805A (ko) 2007-08-27
CN101069281A (zh) 2007-11-07
US7067368B1 (en) 2006-06-27
US20060121662A1 (en) 2006-06-08
WO2006060575A3 (en) 2007-04-26
WO2006060575A2 (en) 2006-06-08
US20060121665A1 (en) 2006-06-08
EP1825508A4 (en) 2009-06-24
US7064025B1 (en) 2006-06-20
US7112481B2 (en) 2006-09-26
EP1825508A2 (en) 2007-08-29
TW200625540A (en) 2006-07-16
JP2008522444A (ja) 2008-06-26

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